--- qemu/roms/seabios/src/config.h	2018/04/24 17:36:48	1.1.1.1
+++ qemu/roms/seabios/src/config.h	2018/04/24 18:27:41	1.1.1.4
@@ -36,12 +36,22 @@
 #define CONFIG_USB_UHCI 1
 // Support USB OHCI controllers
 #define CONFIG_USB_OHCI 1
+// Support USB EHCI controllers
+#define CONFIG_USB_EHCI 1
+// Support USB disks
+#define CONFIG_USB_MSC 1
+// Support USB hubs
+#define CONFIG_USB_HUB 1
 // Support USB keyboards
 #define CONFIG_USB_KEYBOARD 1
+// Support USB mice
+#define CONFIG_USB_MOUSE 1
 // Support PS2 ports (keyboard and mouse)
 #define CONFIG_PS2PORT 1
 // Support for IDE disk code
 #define CONFIG_ATA 1
+// Detect and try to use ATA bus mastering DMA controllers.
+#define CONFIG_ATA_DMA 0
 // Use 32bit PIO accesses on ATA (minor optimization on PCI transfers)
 #define CONFIG_ATA_PIO32 0
 // Support for booting from a CD
@@ -79,7 +89,7 @@
 #define CONFIG_PCI_ROOT1 0x00
 #define CONFIG_PCI_ROOT2 0x00
 // Support searching coreboot flash format.
-#define CONFIG_COREBOOT_FLASH 0
+#define CONFIG_COREBOOT_FLASH 1
 // Support floppy images in the coreboot flash.
 #define CONFIG_FLASH_FLOPPY 1
 // Support the lzma decompression algorighm.
@@ -111,19 +121,24 @@
 #define CONFIG_S3_RESUME 1
 // Run the vga rom during S3 resume.
 #define CONFIG_S3_RESUME_VGA_INIT 0
+// Support boot splash
+#define CONFIG_BOOTSPLASH 0
+// boot splash X resolution
+#define CONFIG_BOOTSPLASH_X 1024
+// boot splash Y resolution
+#define CONFIG_BOOTSPLASH_Y 768
+// boot splash color depth
+#define CONFIG_BOOTSPLASH_DEPTH 16
+// boot splash VESA mode (could be generated)
+#define CONFIG_BOOTSPLASH_VESA_MODE 0x117
 // define it if the (emulated) hardware supports SMM mode
 #define CONFIG_USE_SMM 1
 // Maximum number of map entries in the e820 map
 #define CONFIG_MAX_E820 32
-// Space to reserve in f-segment for run-time built bios tables.
+// Space to reserve in f-segment for dynamic allocations
 #define CONFIG_MAX_BIOSTABLE 2048
 // Space to reserve in high-memory for tables
 #define CONFIG_MAX_HIGHTABLE (64*1024)
-
-// Maximum number of ATA controllers to support
-#define CONFIG_MAX_ATA_INTERFACES 4
-// Maximum number of internal drives supported
-#define CONFIG_MAX_DRIVES 8
 // Largest supported externaly facing drive id
 #define CONFIG_MAX_EXTDRIVE 16
 
@@ -131,6 +146,9 @@
 #define CONFIG_SUBMODEL_ID   0x00
 #define CONFIG_BIOS_REVISION 0x01
 
+// Support boot from virtio storage
+#define CONFIG_VIRTIO_BLK 1
+
 // Various memory addresses used by the code.
 #define BUILD_STACK_ADDR          0x7000
 #define BUILD_S3RESUME_STACK_ADDR 0x1000
@@ -142,6 +160,25 @@
 #define BUILD_BIOS_SIZE           0x10000
 // 32KB for shadow ram copying (works around emulator deficiencies)
 #define BUILD_BIOS_TMP_ADDR       0x30000
+#define BUILD_MAX_HIGHMEM         0xe0000000
+
+// Support old pci mem assignment behaviour
+//#define CONFIG_OLD_PCIMEM_ASSIGNMENT    1
+#if CONFIG_OLD_PCIMEM_ASSIGNMENT
+#define BUILD_PCIMEM_START        0xf0000000
+#define BUILD_PCIMEM_SIZE         (BUILD_PCIMEM_END - BUILD_PCIMEM_START)
+#define BUILD_PCIMEM_END          0xfec00000    /* IOAPIC is mapped at */
+#define BUILD_PCIPREFMEM_START    0
+#define BUILD_PCIPREFMEM_SIZE     0
+#define BUILD_PCIPREFMEM_END      0
+#else
+#define BUILD_PCIMEM_START        0xf0000000
+#define BUILD_PCIMEM_SIZE         0x08000000    /* half- of pci window */
+#define BUILD_PCIMEM_END          (BUILD_PCIMEM_START + BUILD_PCIMEM_SIZE)
+#define BUILD_PCIPREFMEM_START    BUILD_PCIMEM_END
+#define BUILD_PCIPREFMEM_SIZE     (BUILD_PCIPREFMEM_END - BUILD_PCIPREFMEM_START)
+#define BUILD_PCIPREFMEM_END      0xfec00000    /* IOAPIC is mapped at */
+#endif
 
 #define BUILD_APIC_ADDR           0xfee00000
 #define BUILD_IOAPIC_ADDR         0xfec00000
@@ -191,6 +228,8 @@
 #define DEBUG_ISR_hwpic2 5
 #define DEBUG_HDL_pnp 1
 #define DEBUG_HDL_pmm 1
+#define DEBUG_HDL_pcibios32 9
+#define DEBUG_HDL_apm 9
 
 #define DEBUG_unimplemented 2
 #define DEBUG_invalid 3