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Annotation of qemu/roms/seabios/src/dev-i440fx.c, revision 1.1

1.1     ! root        1: // initialization function which are specific to i440fx chipset
        !             2: //
        !             3: // Copyright (C) 2008  Kevin O'Connor <[email protected]>
        !             4: // Copyright (C) 2006 Fabrice Bellard
        !             5: //
        !             6: // Copyright (C) 2010 Isaku Yamahata <yamahata at valinux co jp>
        !             7: // Split out from pciinit.c
        !             8: //
        !             9: // This file may be distributed under the terms of the GNU LGPLv3 license.
        !            10: //
        !            11: 
        !            12: #include "config.h" // CONFIG_DEBUG_LEVEL
        !            13: #include "util.h" // dprintf
        !            14: #include "ioport.h" // outb
        !            15: #include "pci.h" // pci_config_writeb
        !            16: #include "pci_regs.h" // PCI_INTERRUPT_LINE
        !            17: #include "dev-i440fx.h"
        !            18: 
        !            19: /* PIIX3/PIIX4 PCI to ISA bridge */
        !            20: void piix_isa_bridge_init(u16 bdf, void *arg)
        !            21: {
        !            22:     int i, irq;
        !            23:     u8 elcr[2];
        !            24: 
        !            25:     elcr[0] = 0x00;
        !            26:     elcr[1] = 0x00;
        !            27:     for (i = 0; i < 4; i++) {
        !            28:         irq = pci_irqs[i];
        !            29:         /* set to trigger level */
        !            30:         elcr[irq >> 3] |= (1 << (irq & 7));
        !            31:         /* activate irq remapping in PIIX */
        !            32:         pci_config_writeb(bdf, 0x60 + i, irq);
        !            33:     }
        !            34:     outb(elcr[0], 0x4d0);
        !            35:     outb(elcr[1], 0x4d1);
        !            36:     dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
        !            37: }
        !            38: 
        !            39: /* PIIX3/PIIX4 IDE */
        !            40: void piix_ide_init(u16 bdf, void *arg)
        !            41: {
        !            42:     pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
        !            43:     pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
        !            44:     pci_bios_allocate_regions(bdf, NULL);
        !            45: }
        !            46: 
        !            47: /* PIIX4 Power Management device (for ACPI) */
        !            48: void piix4_pm_init(u16 bdf, void *arg)
        !            49: {
        !            50:     // acpi sci is hardwired to 9
        !            51:     pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
        !            52: 
        !            53:     pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
        !            54:     pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
        !            55:     pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
        !            56:     pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
        !            57: }

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