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Annotation of qemu/roms/seabios/src/misc.c, revision 1.1

1.1     ! root        1: // Code for misc 16bit handlers and variables.
        !             2: //
        !             3: // Copyright (C) 2008,2009  Kevin O'Connor <[email protected]>
        !             4: // Copyright (C) 2002  MandrakeSoft S.A.
        !             5: //
        !             6: // This file may be distributed under the terms of the GNU LGPLv3 license.
        !             7: 
        !             8: #include "bregs.h" // struct bregs
        !             9: #include "biosvar.h" // GET_BDA
        !            10: #include "util.h" // debug_enter
        !            11: #include "pic.h" // enable_hwirq
        !            12: 
        !            13: // Amount of continuous ram under 4Gig
        !            14: u32 RamSize VAR16VISIBLE;
        !            15: // Amount of continuous ram >4Gig
        !            16: u64 RamSizeOver4G;
        !            17: // Space for bios tables built an run-time.
        !            18: char BiosTableSpace[CONFIG_MAX_BIOSTABLE] __aligned(MALLOC_MIN_ALIGN) VAR16VISIBLE;
        !            19: 
        !            20: 
        !            21: /****************************************************************
        !            22:  * Misc 16bit ISRs
        !            23:  ****************************************************************/
        !            24: 
        !            25: // INT 12h Memory Size Service Entry Point
        !            26: void VISIBLE16
        !            27: handle_12(struct bregs *regs)
        !            28: {
        !            29:     debug_enter(regs, DEBUG_HDL_12);
        !            30:     regs->ax = GET_BDA(mem_size_kb);
        !            31: }
        !            32: 
        !            33: // INT 11h Equipment List Service Entry Point
        !            34: void VISIBLE16
        !            35: handle_11(struct bregs *regs)
        !            36: {
        !            37:     debug_enter(regs, DEBUG_HDL_11);
        !            38:     regs->ax = GET_BDA(equipment_list_flags);
        !            39: }
        !            40: 
        !            41: // INT 05h Print Screen Service Entry Point
        !            42: void VISIBLE16
        !            43: handle_05(struct bregs *regs)
        !            44: {
        !            45:     debug_enter(regs, DEBUG_HDL_05);
        !            46: }
        !            47: 
        !            48: // INT 10h Video Support Service Entry Point
        !            49: void VISIBLE16
        !            50: handle_10(struct bregs *regs)
        !            51: {
        !            52:     debug_enter(regs, DEBUG_HDL_10);
        !            53:     // dont do anything, since the VGA BIOS handles int10h requests
        !            54: }
        !            55: 
        !            56: // NMI handler
        !            57: void VISIBLE16
        !            58: handle_02()
        !            59: {
        !            60:     debug_isr(DEBUG_ISR_02);
        !            61: }
        !            62: 
        !            63: void
        !            64: mathcp_setup()
        !            65: {
        !            66:     dprintf(3, "math cp init\n");
        !            67:     // 80x87 coprocessor installed
        !            68:     SETBITS_BDA(equipment_list_flags, 0x02);
        !            69:     enable_hwirq(13, entry_75);
        !            70: }
        !            71: 
        !            72: // INT 75 - IRQ13 - MATH COPROCESSOR EXCEPTION
        !            73: void VISIBLE16
        !            74: handle_75()
        !            75: {
        !            76:     debug_isr(DEBUG_ISR_75);
        !            77: 
        !            78:     // clear irq13
        !            79:     outb(0, PORT_MATH_CLEAR);
        !            80:     // clear interrupt
        !            81:     eoi_pic2();
        !            82:     // legacy nmi call
        !            83:     u32 eax=0, flags;
        !            84:     call16_simpint(0x02, &eax, &flags);
        !            85: }
        !            86: 
        !            87: 
        !            88: /****************************************************************
        !            89:  * BIOS_CONFIG_TABLE
        !            90:  ****************************************************************/
        !            91: 
        !            92: // DMA channel 3 used by hard disk BIOS
        !            93: #define CBT_F1_DMA3USED (1<<7)
        !            94: // 2nd interrupt controller (8259) installed
        !            95: #define CBT_F1_2NDPIC   (1<<6)
        !            96: // Real-Time Clock installed
        !            97: #define CBT_F1_RTC      (1<<5)
        !            98: // INT 15/AH=4Fh called upon INT 09h
        !            99: #define CBT_F1_INT154F  (1<<4)
        !           100: // wait for external event (INT 15/AH=41h) supported
        !           101: #define CBT_F1_WAITEXT  (1<<3)
        !           102: // extended BIOS area allocated (usually at top of RAM)
        !           103: #define CBT_F1_EBDA     (1<<2)
        !           104: // bus is Micro Channel instead of ISA
        !           105: #define CBT_F1_MCA      (1<<1)
        !           106: // system has dual bus (Micro Channel + ISA)
        !           107: #define CBT_F1_MCAISA   (1<<0)
        !           108: 
        !           109: // INT 16/AH=09h (keyboard functionality) supported
        !           110: #define CBT_F2_INT1609  (1<<6)
        !           111: 
        !           112: struct bios_config_table_s BIOS_CONFIG_TABLE VAR16FIXED(0xe6f5) = {
        !           113:     .size     = sizeof(BIOS_CONFIG_TABLE) - 2,
        !           114:     .model    = CONFIG_MODEL_ID,
        !           115:     .submodel = CONFIG_SUBMODEL_ID,
        !           116:     .biosrev  = CONFIG_BIOS_REVISION,
        !           117:     .feature1 = (
        !           118:         CBT_F1_2NDPIC | CBT_F1_RTC | CBT_F1_EBDA
        !           119:         | (CONFIG_KBD_CALL_INT15_4F ? CBT_F1_INT154F : 0)),
        !           120:     .feature2 = CBT_F2_INT1609,
        !           121:     .feature3 = 0,
        !           122:     .feature4 = 0,
        !           123:     .feature5 = 0,
        !           124: };
        !           125: 
        !           126: 
        !           127: /****************************************************************
        !           128:  * GDT and IDT tables
        !           129:  ****************************************************************/
        !           130: 
        !           131: // Real mode IDT descriptor
        !           132: struct descloc_s rmode_IDT_info VAR16VISIBLE = {
        !           133:     .length = sizeof(struct rmode_IVT) - 1,
        !           134:     .addr = (u32)MAKE_FLATPTR(SEG_IVT, 0),
        !           135: };
        !           136: 
        !           137: // Dummy IDT that forces a machine shutdown if an irq happens in
        !           138: // protected mode.
        !           139: u8 dummy_IDT VAR16VISIBLE;
        !           140: 
        !           141: // Protected mode IDT descriptor
        !           142: struct descloc_s pmode_IDT_info VAR16VISIBLE = {
        !           143:     .length = sizeof(dummy_IDT) - 1,
        !           144:     .addr = (u32)MAKE_FLATPTR(SEG_BIOS, &dummy_IDT),
        !           145: };
        !           146: 
        !           147: // GDT
        !           148: u64 rombios32_gdt[] VAR16VISIBLE __aligned(8) = {
        !           149:     // First entry can't be used.
        !           150:     0x0000000000000000LL,
        !           151:     // 32 bit flat code segment (SEG32_MODE32_CS)
        !           152:     GDT_LIMIT(0xfffff) | GDT_CODE | GDT_B | GDT_G,
        !           153:     // 32 bit flat data segment (SEG32_MODE32_DS)
        !           154:     GDT_LIMIT(0xfffff) | GDT_DATA | GDT_B | GDT_G,
        !           155:     // 16 bit code segment base=0xf0000 limit=0xffff (SEG32_MODE16_CS)
        !           156:     GDT_LIMIT(0x0ffff) | GDT_CODE | GDT_BASE(0xf0000),
        !           157:     // 16 bit data segment base=0x0 limit=0xffff (SEG32_MODE16_DS)
        !           158:     GDT_LIMIT(0x0ffff) | GDT_DATA,
        !           159:     // 16 bit code segment base=0 limit=0xffffffff (SEG32_MODE16BIG_CS)
        !           160:     GDT_LIMIT(0xfffff) | GDT_CODE | GDT_G,
        !           161:     // 16 bit data segment base=0 limit=0xffffffff (SEG32_MODE16BIG_DS)
        !           162:     GDT_LIMIT(0xfffff) | GDT_DATA | GDT_G,
        !           163: };
        !           164: 
        !           165: // GDT descriptor
        !           166: struct descloc_s rombios32_gdt_48 VAR16VISIBLE = {
        !           167:     .length = sizeof(rombios32_gdt) - 1,
        !           168:     .addr = (u32)MAKE_FLATPTR(SEG_BIOS, rombios32_gdt),
        !           169: };
        !           170: 
        !           171: 
        !           172: /****************************************************************
        !           173:  * Misc fixed vars
        !           174:  ****************************************************************/
        !           175: 
        !           176: char BiosCopyright[] VAR16FIXED(0xff00) =
        !           177:     "(c) 2002 MandrakeSoft S.A. Written by Kevin Lawton & the Bochs team.";
        !           178: 
        !           179: // BIOS build date
        !           180: char BiosDate[] VAR16FIXED(0xfff5) = "06/23/99";
        !           181: 
        !           182: u8 BiosModelId VAR16FIXED(0xfffe) = CONFIG_MODEL_ID;
        !           183: 
        !           184: u8 BiosChecksum VAR16FIXED(0xffff);
        !           185: 
        !           186: // XXX - Initial Interrupt Vector Offsets Loaded by POST
        !           187: u8 InitVectors[13] VAR16FIXED(0xfef3);
        !           188: 
        !           189: // XXX - INT 1D - SYSTEM DATA - VIDEO PARAMETER TABLES
        !           190: u8 VideoParams[88] VAR16FIXED(0xf0a4);

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