--- qemu/roms/seabios/src/pcibios.c	2018/04/24 17:36:46	1.1.1.1
+++ qemu/roms/seabios/src/pcibios.c	2018/04/24 19:23:41	1.1.1.3
@@ -12,6 +12,10 @@
 #include "biosvar.h" // GET_EBDA
 #include "pci_regs.h" // PCI_VENDOR_ID
 
+// romlayout.S
+extern void entry_bios32(void);
+extern void entry_pcibios32(void);
+
 #define RET_FUNC_NOT_SUPPORTED 0x81
 #define RET_BAD_VENDOR_ID      0x83
 #define RET_DEVICE_NOT_FOUND   0x86
@@ -21,17 +25,11 @@
 static void
 handle_1ab101(struct bregs *regs)
 {
-    // Find max bus.
-    int bdf, max;
-    foreachpci(bdf, max) {
-    }
-
     regs->al = 0x01; // Flags - "Config Mechanism #1" supported.
     regs->bx = 0x0210; // PCI version 2.10
-    regs->cl = pci_bdf_to_bus(max - 1);
+    regs->cl = GET_GLOBAL(MaxPCIBus);
     regs->edx = 0x20494350; // "PCI "
-    // XXX - bochs bios code sets edi to point to 32bit code - but no
-    // reference to this in spec.
+    regs->edi = (u32)entry_pcibios32 + BUILD_BIOS_ADDR;
     set_code_success(regs);
 }
 
@@ -41,16 +39,20 @@ handle_1ab102(struct bregs *regs)
 {
     u32 id = (regs->cx << 16) | regs->dx;
     int count = regs->si;
-    int bdf, max;
-    foreachpci(bdf, max) {
-        u32 v = pci_config_readl(bdf, PCI_VENDOR_ID);
-        if (v != id)
-            continue;
-        if (count--)
-            continue;
-        regs->bx = bdf;
-        set_code_success(regs);
-        return;
+    int bus = -1;
+    while (bus < GET_GLOBAL(MaxPCIBus)) {
+        bus++;
+        int bdf;
+        foreachbdf(bdf, bus) {
+            u32 v = pci_config_readl(bdf, PCI_VENDOR_ID);
+            if (v != id)
+                continue;
+            if (count--)
+                continue;
+            regs->bx = bdf;
+            set_code_success(regs);
+            return;
+        }
     }
     set_code_invalid(regs, RET_DEVICE_NOT_FOUND);
 }
@@ -61,16 +63,20 @@ handle_1ab103(struct bregs *regs)
 {
     int count = regs->si;
     u32 classprog = regs->ecx;
-    int bdf, max;
-    foreachpci(bdf, max) {
-        u32 v = pci_config_readl(bdf, PCI_CLASS_REVISION);
-        if ((v>>8) != classprog)
-            continue;
-        if (count--)
-            continue;
-        regs->bx = bdf;
-        set_code_success(regs);
-        return;
+    int bus = -1;
+    while (bus < GET_GLOBAL(MaxPCIBus)) {
+        bus++;
+        int bdf;
+        foreachbdf(bdf, bus) {
+            u32 v = pci_config_readl(bdf, PCI_CLASS_REVISION);
+            if ((v>>8) != classprog)
+                continue;
+            if (count--)
+                continue;
+            regs->bx = bdf;
+            set_code_success(regs);
+            return;
+        }
     }
     set_code_invalid(regs, RET_DEVICE_NOT_FOUND);
 }
@@ -154,7 +160,8 @@ handle_1ab10e(struct bregs *regs)
 
     // Memcpy pir table slots to dest buffer.
     memcpy_far(buf_seg, buf_far
-               , get_global_seg(), pirtable_g->slots
+               , get_global_seg()
+               , (void*)(pirtable_g->slots) + get_global_offset()
                , pirsize);
 
     // XXX - bochs bios sets bx to (1 << 9) | (1 << 11)
@@ -192,3 +199,39 @@ handle_1ab1(struct bregs *regs)
     default:   handle_1ab1XX(regs); break;
     }
 }
+
+
+/****************************************************************
+ * 32bit interface
+ ****************************************************************/
+
+// Entry point for 32bit pci bios functions.
+void VISIBLE32SEG
+handle_pcibios32(struct bregs *regs)
+{
+    debug_enter(regs, DEBUG_HDL_pcibios32);
+    handle_1ab1(regs);
+}
+
+struct bios32_s {
+    u32 signature;
+    u32 entry;
+    u8 version;
+    u8 length;
+    u8 checksum;
+    u8 reserved[5];
+} PACKED;
+
+struct bios32_s BIOS32HEADER __aligned(16) VAR16EXPORT = {
+    .signature = 0x5f32335f, // _32_
+    .length = sizeof(BIOS32HEADER) / 16,
+};
+
+void
+bios32_setup(void)
+{
+    dprintf(3, "init bios32\n");
+
+    BIOS32HEADER.entry = (u32)entry_bios32;
+    BIOS32HEADER.checksum -= checksum(&BIOS32HEADER, sizeof(BIOS32HEADER));
+}