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1.1 root 1: // Initialize PCI devices (on emulators)
2: //
3: // Copyright (C) 2008 Kevin O'Connor <[email protected]>
4: // Copyright (C) 2006 Fabrice Bellard
5: //
6: // This file may be distributed under the terms of the GNU LGPLv3 license.
7:
8: #include "util.h" // dprintf
9: #include "pci.h" // pci_config_readl
10: #include "biosvar.h" // GET_EBDA
11: #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12: #include "pci_regs.h" // PCI_COMMAND
1.1.1.4 root 13: #include "dev-i440fx.h"
1.1 root 14:
15: #define PCI_ROM_SLOT 6
16: #define PCI_NUM_REGIONS 7
17:
1.1.1.4 root 18: static void pci_bios_init_device_in_bus(int bus);
19:
1.1 root 20: static u32 pci_bios_io_addr;
21: static u32 pci_bios_mem_addr;
1.1.1.4 root 22: static u32 pci_bios_prefmem_addr;
1.1 root 23: /* host irqs corresponding to PCI irqs A-D */
1.1.1.4 root 24: const u8 pci_irqs[4] = {
1.1 root 25: 10, 10, 11, 11
26: };
27:
1.1.1.4 root 28: static u32 pci_bar(u16 bdf, int region_num)
29: {
30: if (region_num != PCI_ROM_SLOT) {
31: return PCI_BASE_ADDRESS_0 + region_num * 4;
32: }
33:
34: #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
35: u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
36: type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
37: return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
38: }
39:
1.1 root 40: static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
41: {
1.1.1.5 ! root 42: u32 ofs;
1.1 root 43:
1.1.1.4 root 44: ofs = pci_bar(bdf, region_num);
1.1 root 45:
46: pci_config_writel(bdf, ofs, addr);
47: dprintf(1, "region %d: 0x%08x\n", region_num, addr);
48: }
49:
1.1.1.4 root 50: /*
51: * return value
52: * 0: 32bit BAR
53: * non 0: 64bit BAR
54: */
55: static int pci_bios_allocate_region(u16 bdf, int region_num)
56: {
57: u32 *paddr;
58: u32 ofs = pci_bar(bdf, region_num);
59:
60: u32 old = pci_config_readl(bdf, ofs);
61: u32 mask;
62: if (region_num == PCI_ROM_SLOT) {
63: mask = PCI_ROM_ADDRESS_MASK;
64: pci_config_writel(bdf, ofs, mask);
65: } else {
66: if (old & PCI_BASE_ADDRESS_SPACE_IO)
67: mask = PCI_BASE_ADDRESS_IO_MASK;
68: else
69: mask = PCI_BASE_ADDRESS_MEM_MASK;
70: pci_config_writel(bdf, ofs, ~0);
71: }
72: u32 val = pci_config_readl(bdf, ofs);
73: pci_config_writel(bdf, ofs, old);
74:
75: u32 size = (~(val & mask)) + 1;
76: if (val != 0) {
77: if (val & PCI_BASE_ADDRESS_SPACE_IO) {
78: paddr = &pci_bios_io_addr;
79: if (ALIGN(*paddr, size) + size >= 64 * 1024) {
80: dprintf(1,
81: "io region of (bdf 0x%x bar %d) can't be mapped.\n",
82: bdf, region_num);
83: size = 0;
84: }
85: } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
86: /* keep behaviour on bus = 0 */
87: pci_bdf_to_bus(bdf) != 0 &&
88: /* If pci_bios_prefmem_addr == 0, keep old behaviour */
89: pci_bios_prefmem_addr != 0) {
90: paddr = &pci_bios_prefmem_addr;
91: if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) {
92: dprintf(1,
93: "prefmem region of (bdf 0x%x bar %d) can't be mapped. "
94: "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n",
95: bdf, region_num, BUILD_PCIPREFMEM_SIZE);
96: size = 0;
97: }
98: } else {
99: paddr = &pci_bios_mem_addr;
100: if (ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) {
101: dprintf(1,
102: "mem region of (bdf 0x%x bar %d) can't be mapped. "
103: "increase BUILD_PCIMEM_SIZE and recompile. size %x\n",
104: bdf, region_num, BUILD_PCIMEM_SIZE);
105: size = 0;
106: }
107: }
108: if (size > 0) {
109: *paddr = ALIGN(*paddr, size);
110: pci_set_io_region_addr(bdf, region_num, *paddr);
111: *paddr += size;
112: }
113: }
114:
115: int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
116: (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
1.1.1.5 ! root 117: if (is_64bit && size > 0) {
! 118: pci_config_writel(bdf, ofs + 4, 0);
1.1.1.4 root 119: }
120: return is_64bit;
121: }
122:
123: void pci_bios_allocate_regions(u16 bdf, void *arg)
124: {
125: int i;
126: for (i = 0; i < PCI_NUM_REGIONS; i++) {
127: int is_64bit = pci_bios_allocate_region(bdf, i);
128: if (is_64bit){
129: i++;
130: }
131: }
132: }
133:
1.1 root 134: /* return the global irq number corresponding to a given device irq
135: pin. We could also use the bus number to have a more precise
136: mapping. */
137: static int pci_slot_get_pirq(u16 bdf, int irq_num)
138: {
139: int slot_addend = pci_bdf_to_dev(bdf) - 1;
140: return (irq_num + slot_addend) & 3;
141: }
142:
1.1.1.4 root 143: static const struct pci_device_id pci_isa_bridge_tbl[] = {
144: /* PIIX3/PIIX4 PCI to ISA bridge */
145: PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
146: piix_isa_bridge_init),
147: PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
148: piix_isa_bridge_init),
149:
150: PCI_DEVICE_END
151: };
152:
153: #define PCI_IO_ALIGN 4096
154: #define PCI_IO_SHIFT 8
155: #define PCI_MEMORY_ALIGN (1UL << 20)
156: #define PCI_MEMORY_SHIFT 16
157: #define PCI_PREF_MEMORY_ALIGN (1UL << 20)
158: #define PCI_PREF_MEMORY_SHIFT 16
159:
160: static void pci_bios_init_device_bridge(u16 bdf, void *arg)
1.1 root 161: {
1.1.1.4 root 162: pci_bios_allocate_region(bdf, 0);
163: pci_bios_allocate_region(bdf, 1);
164: pci_bios_allocate_region(bdf, PCI_ROM_SLOT);
165:
166: u32 io_old = pci_bios_io_addr;
167: u32 mem_old = pci_bios_mem_addr;
168: u32 prefmem_old = pci_bios_prefmem_addr;
169:
170: /* IO BASE is assumed to be 16 bit */
171: pci_bios_io_addr = ALIGN(pci_bios_io_addr, PCI_IO_ALIGN);
172: pci_bios_mem_addr = ALIGN(pci_bios_mem_addr, PCI_MEMORY_ALIGN);
173: pci_bios_prefmem_addr =
174: ALIGN(pci_bios_prefmem_addr, PCI_PREF_MEMORY_ALIGN);
175:
176: u32 io_base = pci_bios_io_addr;
177: u32 mem_base = pci_bios_mem_addr;
178: u32 prefmem_base = pci_bios_prefmem_addr;
179:
180: u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
181: if (secbus > 0) {
182: pci_bios_init_device_in_bus(secbus);
183: }
1.1 root 184:
1.1.1.4 root 185: pci_bios_io_addr = ALIGN(pci_bios_io_addr, PCI_IO_ALIGN);
186: pci_bios_mem_addr = ALIGN(pci_bios_mem_addr, PCI_MEMORY_ALIGN);
187: pci_bios_prefmem_addr =
188: ALIGN(pci_bios_prefmem_addr, PCI_PREF_MEMORY_ALIGN);
189:
190: u32 io_end = pci_bios_io_addr;
191: if (io_end == io_base) {
192: pci_bios_io_addr = io_old;
193: io_base = 0xffff;
194: io_end = 1;
1.1 root 195: }
1.1.1.4 root 196: pci_config_writeb(bdf, PCI_IO_BASE, io_base >> PCI_IO_SHIFT);
197: pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
198: pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT);
199: pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
200:
201: u32 mem_end = pci_bios_mem_addr;
202: if (mem_end == mem_base) {
203: pci_bios_mem_addr = mem_old;
204: mem_base = 0xffffffff;
205: mem_end = 1;
206: }
207: pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT);
208: pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT);
209:
210: u32 prefmem_end = pci_bios_prefmem_addr;
211: if (prefmem_end == prefmem_base) {
212: pci_bios_prefmem_addr = prefmem_old;
213: prefmem_base = 0xffffffff;
214: prefmem_end = 1;
215: }
216: pci_config_writew(bdf, PCI_PREF_MEMORY_BASE,
217: prefmem_base >> PCI_PREF_MEMORY_SHIFT);
218: pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT,
219: (prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT);
220: pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
221: pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
222:
223: dprintf(1, "PCI: br io = [0x%x, 0x%x)\n", io_base, io_end);
224: dprintf(1, "PCI: br mem = [0x%x, 0x%x)\n", mem_base, mem_end);
225: dprintf(1, "PCI: br pref = [0x%x, 0x%x)\n", prefmem_base, prefmem_end);
226:
227: u16 cmd = pci_config_readw(bdf, PCI_COMMAND);
228: cmd &= ~PCI_COMMAND_IO;
229: if (io_end > io_base) {
230: cmd |= PCI_COMMAND_IO;
231: }
232: cmd &= ~PCI_COMMAND_MEMORY;
233: if (mem_end > mem_base || prefmem_end > prefmem_base) {
234: cmd |= PCI_COMMAND_MEMORY;
235: }
236: cmd |= PCI_COMMAND_MASTER;
237: pci_config_writew(bdf, PCI_COMMAND, cmd);
238:
239: pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
240: }
241:
242: static void storage_ide_init(u16 bdf, void *arg)
243: {
244: /* IDE: we map it as in ISA mode */
245: pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
246: pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
247: pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
248: pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
249: }
250:
251: static void pic_ibm_init(u16 bdf, void *arg)
252: {
253: /* PIC, IBM, MPIC & MPIC2 */
254: pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
1.1 root 255: }
256:
1.1.1.4 root 257: static void apple_macio_init(u16 bdf, void *arg)
258: {
259: /* macio bridge */
260: pci_set_io_region_addr(bdf, 0, 0x80800000);
261: }
262:
263: static const struct pci_device_id pci_class_tbl[] = {
264: /* STORAGE IDE */
265: PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
266: PCI_CLASS_STORAGE_IDE, piix_ide_init),
267: PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
268: PCI_CLASS_STORAGE_IDE, piix_ide_init),
269: PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
270: storage_ide_init),
271:
272: /* PIC, IBM, MIPC & MPIC2 */
273: PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
274: pic_ibm_init),
275: PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
276: pic_ibm_init),
277:
278: /* 0xff00 */
279: PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
280: PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
281:
282: /* PCI bridge */
283: PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
284: pci_bios_init_device_bridge),
285:
286: /* default */
287: PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions),
288:
289: PCI_DEVICE_END,
290: };
291:
292: static const struct pci_device_id pci_device_tbl[] = {
293: /* PIIX4 Power Management device (for ACPI) */
294: PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
295: piix4_pm_init),
296:
297: PCI_DEVICE_END,
298: };
299:
1.1 root 300: static void pci_bios_init_device(u16 bdf)
301: {
1.1.1.4 root 302: int pin, pic_irq, vendor_id, device_id;
1.1 root 303:
304: vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
305: device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
306: dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
307: , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
1.1.1.4 root 308: pci_init_device(pci_class_tbl, bdf, NULL);
1.1 root 309:
310: /* enable memory mappings */
311: pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
312:
313: /* map the interrupt */
314: pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
315: if (pin != 0) {
316: pin = pci_slot_get_pirq(bdf, pin - 1);
317: pic_irq = pci_irqs[pin];
318: pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
319: }
320:
1.1.1.4 root 321: pci_init_device(pci_device_tbl, bdf, NULL);
322: }
323:
324: static void pci_bios_init_device_in_bus(int bus)
325: {
326: int bdf, max;
327: foreachpci_in_bus(bdf, max, bus) {
328: pci_bios_init_device(bdf);
1.1 root 329: }
330: }
331:
1.1.1.4 root 332: static void
333: pci_bios_init_bus_rec(int bus, u8 *pci_bus)
334: {
335: int bdf, max;
336: u16 class;
337:
338: dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
339:
340: /* prevent accidental access to unintended devices */
341: foreachpci_in_bus(bdf, max, bus) {
342: class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
343: if (class == PCI_CLASS_BRIDGE_PCI) {
344: pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
345: pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
346: }
347: }
348:
349: foreachpci_in_bus(bdf, max, bus) {
350: class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
351: if (class != PCI_CLASS_BRIDGE_PCI) {
352: continue;
353: }
354: dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
355:
356: u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
357: if (pribus != bus) {
358: dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
359: pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
360: } else {
361: dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
362: }
363:
364: u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
365: (*pci_bus)++;
366: if (*pci_bus != secbus) {
367: dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
368: secbus, *pci_bus);
369: secbus = *pci_bus;
370: pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
371: } else {
372: dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
373: }
374:
375: /* set to max for access to all subordinate buses.
376: later set it to accurate value */
377: u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
378: pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
379:
380: pci_bios_init_bus_rec(secbus, pci_bus);
381:
382: if (subbus != *pci_bus) {
383: dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
384: subbus, *pci_bus);
385: subbus = *pci_bus;
386: } else {
387: dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
388: }
389: pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
390: }
391: }
392:
393: static void
394: pci_bios_init_bus(void)
395: {
396: u8 pci_bus = 0;
397: pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
398: }
399:
1.1 root 400: void
401: pci_setup(void)
402: {
403: if (CONFIG_COREBOOT)
404: // Already done by coreboot.
405: return;
406:
407: dprintf(3, "pci setup\n");
408:
409: pci_bios_io_addr = 0xc000;
1.1.1.3 root 410: pci_bios_mem_addr = BUILD_PCIMEM_START;
1.1.1.4 root 411: pci_bios_prefmem_addr = BUILD_PCIPREFMEM_START;
412:
413: pci_bios_init_bus();
1.1 root 414:
415: int bdf, max;
416: foreachpci(bdf, max) {
1.1.1.4 root 417: pci_init_device(pci_isa_bridge_tbl, bdf, NULL);
1.1 root 418: }
1.1.1.4 root 419: pci_bios_init_device_in_bus(0 /* host bus */);
1.1 root 420: }
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