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1.1 root 1: // Initialize PCI devices (on emulators)
2: //
3: // Copyright (C) 2008 Kevin O'Connor <[email protected]>
4: // Copyright (C) 2006 Fabrice Bellard
5: //
6: // This file may be distributed under the terms of the GNU LGPLv3 license.
7:
8: #include "util.h" // dprintf
9: #include "pci.h" // pci_config_readl
10: #include "biosvar.h" // GET_EBDA
11: #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12: #include "pci_regs.h" // PCI_COMMAND
1.1.1.7 root 13: #include "xen.h" // usingXen
1.1 root 14:
1.1.1.7 root 15: #define PCI_IO_INDEX_SHIFT 2
16: #define PCI_MEM_INDEX_SHIFT 12
17:
18: #define PCI_BRIDGE_IO_MIN 0x1000
19: #define PCI_BRIDGE_MEM_MIN 0x100000
20:
21: enum pci_region_type {
22: PCI_REGION_TYPE_IO,
23: PCI_REGION_TYPE_MEM,
24: PCI_REGION_TYPE_PREFMEM,
25: PCI_REGION_TYPE_COUNT,
26: };
27:
28: static const char *region_type_name[] = {
29: [ PCI_REGION_TYPE_IO ] = "io",
30: [ PCI_REGION_TYPE_MEM ] = "mem",
31: [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
32: };
33:
1.1.1.8 ! root 34: struct pci_bus {
1.1.1.7 root 35: struct {
36: /* pci region stats */
37: u32 count[32 - PCI_MEM_INDEX_SHIFT];
38: u32 sum, max;
39: /* seconday bus region sizes */
40: u32 size;
41: /* pci region assignments */
42: u32 bases[32 - PCI_MEM_INDEX_SHIFT];
43: u32 base;
44: } r[PCI_REGION_TYPE_COUNT];
1.1.1.8 ! root 45: struct pci_device *bus_dev;
! 46: };
1.1.1.4 root 47:
1.1.1.7 root 48: static int pci_size_to_index(u32 size, enum pci_region_type type)
49: {
50: int index = __fls(size);
51: int shift = (type == PCI_REGION_TYPE_IO) ?
52: PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
53:
54: if (index < shift)
55: index = shift;
56: index -= shift;
57: return index;
58: }
59:
60: static u32 pci_index_to_size(int index, enum pci_region_type type)
61: {
62: int shift = (type == PCI_REGION_TYPE_IO) ?
63: PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
64:
65: return 0x1 << (index + shift);
66: }
67:
68: static enum pci_region_type pci_addr_to_type(u32 addr)
69: {
70: if (addr & PCI_BASE_ADDRESS_SPACE_IO)
71: return PCI_REGION_TYPE_IO;
72: if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
73: return PCI_REGION_TYPE_PREFMEM;
74: return PCI_REGION_TYPE_MEM;
75: }
76:
1.1.1.8 ! root 77: static u32 pci_bar(struct pci_device *pci, int region_num)
1.1.1.4 root 78: {
79: if (region_num != PCI_ROM_SLOT) {
80: return PCI_BASE_ADDRESS_0 + region_num * 4;
81: }
82:
83: #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
1.1.1.8 ! root 84: u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1.1.1.4 root 85: return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
86: }
87:
1.1.1.8 ! root 88: static void
! 89: pci_set_io_region_addr(struct pci_device *pci, int region_num, u32 addr)
1.1 root 90: {
1.1.1.8 ! root 91: pci_config_writel(pci->bdf, pci_bar(pci, region_num), addr);
! 92: }
1.1 root 93:
94:
1.1.1.8 ! root 95: /****************************************************************
! 96: * Misc. device init
! 97: ****************************************************************/
1.1.1.4 root 98:
1.1.1.8 ! root 99: /* host irqs corresponding to PCI irqs A-D */
! 100: const u8 pci_irqs[4] = {
! 101: 10, 10, 11, 11
! 102: };
! 103:
! 104: // Return the global irq number corresponding to a host bus device irq pin.
! 105: static int pci_slot_get_irq(u16 bdf, int pin)
1.1 root 106: {
107: int slot_addend = pci_bdf_to_dev(bdf) - 1;
1.1.1.8 ! root 108: return pci_irqs[(pin - 1 + slot_addend) & 3];
1.1 root 109: }
110:
1.1.1.7 root 111: /* PIIX3/PIIX4 PCI to ISA bridge */
112: static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
113: {
114: int i, irq;
115: u8 elcr[2];
116:
117: elcr[0] = 0x00;
118: elcr[1] = 0x00;
119: for (i = 0; i < 4; i++) {
120: irq = pci_irqs[i];
121: /* set to trigger level */
122: elcr[irq >> 3] |= (1 << (irq & 7));
123: /* activate irq remapping in PIIX */
124: pci_config_writeb(pci->bdf, 0x60 + i, irq);
125: }
126: outb(elcr[0], 0x4d0);
127: outb(elcr[1], 0x4d1);
128: dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
129: }
130:
1.1.1.4 root 131: static const struct pci_device_id pci_isa_bridge_tbl[] = {
132: /* PIIX3/PIIX4 PCI to ISA bridge */
133: PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
134: piix_isa_bridge_init),
135: PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
136: piix_isa_bridge_init),
137:
138: PCI_DEVICE_END
139: };
140:
1.1.1.7 root 141: static void storage_ide_init(struct pci_device *pci, void *arg)
1.1.1.4 root 142: {
143: /* IDE: we map it as in ISA mode */
1.1.1.8 ! root 144: pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE);
! 145: pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE);
! 146: pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE);
! 147: pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE);
1.1.1.4 root 148: }
149:
1.1.1.7 root 150: /* PIIX3/PIIX4 IDE */
151: static void piix_ide_init(struct pci_device *pci, void *arg)
152: {
153: u16 bdf = pci->bdf;
154: pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
155: pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
156: }
157:
158: static void pic_ibm_init(struct pci_device *pci, void *arg)
1.1.1.4 root 159: {
160: /* PIC, IBM, MPIC & MPIC2 */
1.1.1.8 ! root 161: pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000);
1.1 root 162: }
163:
1.1.1.7 root 164: static void apple_macio_init(struct pci_device *pci, void *arg)
1.1.1.4 root 165: {
166: /* macio bridge */
1.1.1.8 ! root 167: pci_set_io_region_addr(pci, 0, 0x80800000);
1.1.1.4 root 168: }
169:
170: static const struct pci_device_id pci_class_tbl[] = {
171: /* STORAGE IDE */
172: PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
173: PCI_CLASS_STORAGE_IDE, piix_ide_init),
174: PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
175: PCI_CLASS_STORAGE_IDE, piix_ide_init),
176: PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
177: storage_ide_init),
178:
179: /* PIC, IBM, MIPC & MPIC2 */
180: PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
181: pic_ibm_init),
182: PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
183: pic_ibm_init),
184:
185: /* 0xff00 */
186: PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
187: PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
188:
189: PCI_DEVICE_END,
190: };
191:
1.1.1.7 root 192: /* PIIX4 Power Management device (for ACPI) */
193: static void piix4_pm_init(struct pci_device *pci, void *arg)
194: {
195: u16 bdf = pci->bdf;
196: // acpi sci is hardwired to 9
197: pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
198:
199: pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
200: pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
201: pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
202: pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
203: }
204:
1.1.1.4 root 205: static const struct pci_device_id pci_device_tbl[] = {
206: /* PIIX4 Power Management device (for ACPI) */
207: PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
208: piix4_pm_init),
209:
210: PCI_DEVICE_END,
211: };
212:
1.1.1.7 root 213: static void pci_bios_init_device(struct pci_device *pci)
1.1 root 214: {
1.1.1.7 root 215: u16 bdf = pci->bdf;
1.1.1.8 ! root 216: dprintf(1, "PCI: init bdf=%02x:%02x.%x id=%04x:%04x\n"
! 217: , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)
1.1.1.7 root 218: , pci->vendor, pci->device);
1.1.1.8 ! root 219:
1.1.1.7 root 220: pci_init_device(pci_class_tbl, pci, NULL);
1.1 root 221:
222: /* enable memory mappings */
223: pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
224:
225: /* map the interrupt */
1.1.1.8 ! root 226: int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
! 227: if (pin != 0)
! 228: pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(bdf, pin));
1.1 root 229:
1.1.1.7 root 230: pci_init_device(pci_device_tbl, pci, NULL);
1.1.1.4 root 231: }
232:
1.1.1.8 ! root 233: static void pci_bios_init_devices(void)
1.1.1.4 root 234: {
1.1.1.7 root 235: struct pci_device *pci;
236: foreachpci(pci) {
1.1.1.8 ! root 237: if (pci_bdf_to_bus(pci->bdf) != 0)
! 238: // Only init devices on host bus.
1.1.1.7 root 239: break;
240: pci_bios_init_device(pci);
1.1 root 241: }
1.1.1.8 ! root 242:
! 243: foreachpci(pci) {
! 244: pci_init_device(pci_isa_bridge_tbl, pci, NULL);
! 245: }
1.1 root 246: }
247:
1.1.1.8 ! root 248:
! 249: /****************************************************************
! 250: * Bus initialization
! 251: ****************************************************************/
! 252:
1.1.1.4 root 253: static void
254: pci_bios_init_bus_rec(int bus, u8 *pci_bus)
255: {
1.1.1.7 root 256: int bdf;
1.1.1.4 root 257: u16 class;
258:
259: dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
260:
261: /* prevent accidental access to unintended devices */
1.1.1.7 root 262: foreachbdf(bdf, bus) {
1.1.1.4 root 263: class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
264: if (class == PCI_CLASS_BRIDGE_PCI) {
265: pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
266: pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
267: }
268: }
269:
1.1.1.7 root 270: foreachbdf(bdf, bus) {
1.1.1.4 root 271: class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
272: if (class != PCI_CLASS_BRIDGE_PCI) {
273: continue;
274: }
275: dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
276:
277: u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
278: if (pribus != bus) {
279: dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
280: pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
281: } else {
282: dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
283: }
284:
285: u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
286: (*pci_bus)++;
287: if (*pci_bus != secbus) {
288: dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
289: secbus, *pci_bus);
290: secbus = *pci_bus;
291: pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
292: } else {
293: dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
294: }
295:
296: /* set to max for access to all subordinate buses.
297: later set it to accurate value */
298: u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
299: pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
300:
301: pci_bios_init_bus_rec(secbus, pci_bus);
302:
303: if (subbus != *pci_bus) {
304: dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
305: subbus, *pci_bus);
306: subbus = *pci_bus;
307: } else {
308: dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
309: }
310: pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
311: }
312: }
313:
314: static void
315: pci_bios_init_bus(void)
316: {
317: u8 pci_bus = 0;
318: pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
1.1.1.7 root 319: }
320:
1.1.1.8 ! root 321:
! 322: /****************************************************************
! 323: * Bus sizing
! 324: ****************************************************************/
! 325:
! 326: static u32 pci_size_roundup(u32 size)
1.1.1.7 root 327: {
1.1.1.8 ! root 328: int index = __fls(size-1)+1;
! 329: return 0x1 << index;
! 330: }
! 331:
! 332: static void
! 333: pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size)
! 334: {
! 335: u32 ofs = pci_bar(pci, bar);
! 336: u16 bdf = pci->bdf;
1.1.1.7 root 337: u32 old = pci_config_readl(bdf, ofs);
338: u32 mask;
339:
340: if (bar == PCI_ROM_SLOT) {
341: mask = PCI_ROM_ADDRESS_MASK;
342: pci_config_writel(bdf, ofs, mask);
343: } else {
344: if (old & PCI_BASE_ADDRESS_SPACE_IO)
345: mask = PCI_BASE_ADDRESS_IO_MASK;
346: else
347: mask = PCI_BASE_ADDRESS_MEM_MASK;
348: pci_config_writel(bdf, ofs, ~0);
349: }
350: *val = pci_config_readl(bdf, ofs);
351: pci_config_writel(bdf, ofs, old);
352: *size = (~(*val & mask)) + 1;
353: }
354:
355: static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
356: {
357: u32 index;
358:
359: index = pci_size_to_index(size, type);
360: size = pci_index_to_size(index, type);
361: bus->r[type].count[index]++;
362: bus->r[type].sum += size;
363: if (bus->r[type].max < size)
364: bus->r[type].max = size;
365: }
366:
1.1.1.8 ! root 367: static void pci_bios_check_devices(struct pci_bus *busses)
1.1.1.7 root 368: {
1.1.1.8 ! root 369: dprintf(1, "PCI: check devices\n");
1.1.1.7 root 370:
1.1.1.8 ! root 371: // Calculate resources needed for regular (non-bus) devices.
! 372: struct pci_device *pci;
! 373: foreachpci(pci) {
! 374: if (pci->class == PCI_CLASS_BRIDGE_PCI) {
! 375: busses[pci->secondary_bus].bus_dev = pci;
! 376: continue;
! 377: }
! 378: struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
! 379: int i;
! 380: for (i = 0; i < PCI_NUM_REGIONS; i++) {
! 381: u32 val, size;
! 382: pci_bios_get_bar(pci, i, &val, &size);
! 383: if (val == 0)
! 384: continue;
1.1.1.7 root 385:
1.1.1.8 ! root 386: pci_bios_bus_reserve(bus, pci_addr_to_type(val), size);
! 387: pci->bars[i].addr = val;
! 388: pci->bars[i].size = size;
! 389: pci->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
! 390: (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
! 391: == PCI_BASE_ADDRESS_MEM_TYPE_64);
! 392:
! 393: if (pci->bars[i].is64)
! 394: i++;
1.1.1.7 root 395: }
1.1.1.8 ! root 396: }
! 397:
! 398: // Propagate required bus resources to parent busses.
! 399: int secondary_bus;
! 400: for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
! 401: struct pci_bus *s = &busses[secondary_bus];
! 402: if (!s->bus_dev)
! 403: continue;
! 404: struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
! 405: int type;
1.1.1.7 root 406: for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
1.1.1.8 ! root 407: u32 limit = (type == PCI_REGION_TYPE_IO) ?
1.1.1.7 root 408: PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
409: s->r[type].size = s->r[type].sum;
410: if (s->r[type].size < limit)
411: s->r[type].size = limit;
412: s->r[type].size = pci_size_roundup(s->r[type].size);
1.1.1.8 ! root 413: pci_bios_bus_reserve(parent, type, s->r[type].size);
1.1.1.7 root 414: }
415: dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
1.1.1.8 ! root 416: secondary_bus,
1.1.1.7 root 417: s->r[PCI_REGION_TYPE_IO].size,
418: s->r[PCI_REGION_TYPE_MEM].size,
419: s->r[PCI_REGION_TYPE_PREFMEM].size);
420: }
1.1.1.8 ! root 421: }
1.1.1.7 root 422:
1.1.1.8 ! root 423: #define ROOT_BASE(top, sum, max) ALIGN_DOWN((top)-(sum),(max) ?: 1)
1.1.1.7 root 424:
1.1.1.8 ! root 425: // Setup region bases (given the regions' size and alignment)
! 426: static int pci_bios_init_root_regions(struct pci_bus *bus, u32 start, u32 end)
! 427: {
! 428: bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
! 429:
! 430: int reg1 = PCI_REGION_TYPE_PREFMEM, reg2 = PCI_REGION_TYPE_MEM;
! 431: if (bus->r[reg1].sum < bus->r[reg2].sum) {
! 432: // Swap regions so larger area is more likely to align well.
! 433: reg1 = PCI_REGION_TYPE_MEM;
! 434: reg2 = PCI_REGION_TYPE_PREFMEM;
! 435: }
! 436: bus->r[reg2].base = ROOT_BASE(end, bus->r[reg2].sum, bus->r[reg2].max);
! 437: bus->r[reg1].base = ROOT_BASE(bus->r[reg2].base, bus->r[reg1].sum
! 438: , bus->r[reg1].max);
! 439: if (bus->r[reg1].base < start)
! 440: // Memory range requested is larger than available.
! 441: return -1;
! 442: return 0;
1.1.1.7 root 443: }
444:
1.1.1.8 ! root 445:
! 446: /****************************************************************
! 447: * BAR assignment
! 448: ****************************************************************/
! 449:
! 450: static void pci_bios_init_bus_bases(struct pci_bus *bus)
1.1.1.7 root 451: {
1.1.1.8 ! root 452: u32 base, newbase, size;
1.1.1.7 root 453: int type, i;
454:
1.1.1.8 ! root 455: for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
! 456: dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
! 457: bus->r[type].max, bus->r[type].sum, bus->r[type].base);
! 458: base = bus->r[type].base;
! 459: for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
! 460: size = pci_index_to_size(i, type);
! 461: if (!bus->r[type].count[i])
! 462: continue;
! 463: newbase = base + size * bus->r[type].count[i];
! 464: dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
! 465: size, bus->r[type].count[i], base, newbase - 1);
! 466: bus->r[type].bases[i] = base;
! 467: base = newbase;
1.1.1.7 root 468: }
1.1.1.8 ! root 469: }
! 470: }
! 471:
! 472: static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size)
! 473: {
! 474: u32 index, addr;
! 475:
! 476: index = pci_size_to_index(size, type);
! 477: addr = bus->r[type].bases[index];
! 478: bus->r[type].bases[index] += pci_index_to_size(index, type);
! 479: return addr;
! 480: }
! 481:
! 482: #define PCI_IO_SHIFT 8
! 483: #define PCI_MEMORY_SHIFT 16
! 484: #define PCI_PREF_MEMORY_SHIFT 16
! 485:
! 486: static void pci_bios_map_devices(struct pci_bus *busses)
! 487: {
! 488: // Setup bases for root bus.
! 489: dprintf(1, "PCI: init bases bus 0 (primary)\n");
! 490: pci_bios_init_bus_bases(&busses[0]);
1.1.1.7 root 491:
1.1.1.8 ! root 492: // Map regions on each secondary bus.
! 493: int secondary_bus;
! 494: for (secondary_bus=1; secondary_bus<=MaxPCIBus; secondary_bus++) {
! 495: struct pci_bus *s = &busses[secondary_bus];
! 496: if (!s->bus_dev)
! 497: continue;
! 498: u16 bdf = s->bus_dev->bdf;
! 499: struct pci_bus *parent = &busses[pci_bdf_to_bus(bdf)];
! 500: int type;
1.1.1.7 root 501: for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
1.1.1.8 ! root 502: s->r[type].base = pci_bios_bus_get_addr(
! 503: parent, type, s->r[type].size);
1.1.1.7 root 504: }
1.1.1.8 ! root 505: dprintf(1, "PCI: init bases bus %d (secondary)\n", secondary_bus);
1.1.1.7 root 506: pci_bios_init_bus_bases(s);
507:
1.1.1.8 ! root 508: u32 base = s->r[PCI_REGION_TYPE_IO].base;
! 509: u32 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
1.1.1.7 root 510: pci_config_writeb(bdf, PCI_IO_BASE, base >> PCI_IO_SHIFT);
511: pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
512: pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
513: pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
514:
515: base = s->r[PCI_REGION_TYPE_MEM].base;
516: limit = base + s->r[PCI_REGION_TYPE_MEM].size - 1;
517: pci_config_writew(bdf, PCI_MEMORY_BASE, base >> PCI_MEMORY_SHIFT);
518: pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
519:
520: base = s->r[PCI_REGION_TYPE_PREFMEM].base;
521: limit = base + s->r[PCI_REGION_TYPE_PREFMEM].size - 1;
522: pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, base >> PCI_PREF_MEMORY_SHIFT);
523: pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
524: pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
525: pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
526: }
527:
1.1.1.8 ! root 528: // Map regions on each device.
1.1.1.7 root 529: struct pci_device *pci;
530: foreachpci(pci) {
1.1.1.8 ! root 531: if (pci->class == PCI_CLASS_BRIDGE_PCI)
1.1.1.7 root 532: continue;
1.1.1.8 ! root 533: u16 bdf = pci->bdf;
! 534: dprintf(1, "PCI: map device bdf=%02x:%02x.%x\n"
! 535: , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
! 536: struct pci_bus *bus = &busses[pci_bdf_to_bus(bdf)];
! 537: int i;
! 538: for (i = 0; i < PCI_NUM_REGIONS; i++) {
! 539: if (pci->bars[i].addr == 0)
! 540: continue;
1.1.1.7 root 541:
1.1.1.8 ! root 542: int type = pci_addr_to_type(pci->bars[i].addr);
! 543: u32 addr = pci_bios_bus_get_addr(bus, type, pci->bars[i].size);
! 544: dprintf(1, " bar %d, addr %x, size %x [%s]\n",
! 545: i, addr, pci->bars[i].size, region_type_name[type]);
! 546: pci_set_io_region_addr(pci, i, addr);
1.1.1.7 root 547:
1.1.1.8 ! root 548: if (pci->bars[i].is64) {
! 549: i++;
! 550: pci_set_io_region_addr(pci, i, 0);
! 551: }
1.1.1.7 root 552: }
553: }
554: }
555:
556:
1.1.1.8 ! root 557: /****************************************************************
! 558: * Main setup code
! 559: ****************************************************************/
1.1.1.4 root 560:
1.1 root 561: void
562: pci_setup(void)
563: {
1.1.1.7 root 564: if (CONFIG_COREBOOT || usingXen()) {
565: // PCI setup already done by coreboot or Xen - just do probe.
1.1.1.8 ! root 566: pci_probe_devices();
1.1 root 567: return;
1.1.1.7 root 568: }
1.1 root 569:
570: dprintf(3, "pci setup\n");
571:
1.1.1.7 root 572: u32 start = BUILD_PCIMEM_START;
573: u32 end = BUILD_PCIMEM_END;
1.1.1.4 root 574:
1.1.1.7 root 575: dprintf(1, "=== PCI bus & bridge init ===\n");
1.1.1.8 ! root 576: if (pci_probe_host() != 0) {
! 577: return;
! 578: }
1.1.1.4 root 579: pci_bios_init_bus();
1.1 root 580:
1.1.1.7 root 581: dprintf(1, "=== PCI device probing ===\n");
1.1.1.8 ! root 582: pci_probe_devices();
1.1.1.7 root 583:
584: dprintf(1, "=== PCI new allocation pass #1 ===\n");
1.1.1.8 ! root 585: struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
! 586: if (!busses) {
! 587: warn_noalloc();
! 588: return;
! 589: }
! 590: memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
! 591: pci_bios_check_devices(busses);
! 592: if (pci_bios_init_root_regions(&busses[0], start, end) != 0) {
1.1.1.7 root 593: panic("PCI: out of address space\n");
1.1 root 594: }
1.1.1.7 root 595:
596: dprintf(1, "=== PCI new allocation pass #2 ===\n");
1.1.1.8 ! root 597: pci_bios_map_devices(busses);
1.1.1.7 root 598:
1.1.1.8 ! root 599: pci_bios_init_devices();
1.1.1.7 root 600:
601: free(busses);
1.1 root 602: }
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