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1.1 root 1: // QEMU Cirrus CLGD 54xx VGABIOS Extension.
2: //
3: // Copyright (C) 2009 Kevin O'Connor <[email protected]>
4: // Copyright (c) 2004 Makoto Suzuki (suzu)
5: //
6: // This file may be distributed under the terms of the GNU LGPLv3 license.
7:
1.1.1.3 ! root 8: #include "clext.h" // clext_init
! 9: #include "vgabios.h" // VBE_VENDOR_STRING
1.1 root 10: #include "biosvar.h" // GET_GLOBAL
11: #include "util.h" // dprintf
1.1.1.3 ! root 12: #include "bregs.h" // struct bregs
! 13: #include "stdvga.h" // VGAREG_SEQU_ADDRESS
! 14: #include "pci.h" // pci_config_readl
! 15: #include "pci_regs.h" // PCI_BASE_ADDRESS_0
1.1 root 16:
1.1.1.3 ! root 17:
! 18: /****************************************************************
! 19: * Cirrus mode tables
! 20: ****************************************************************/
1.1 root 21:
22: /* VGA */
23: static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
24: static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
25: static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
26:
27: /* extensions */
28: static u16 cgraph_svgacolor[] VAR16 = {
29: 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
30: 0x0009,0x000a,0x000b,
31: 0xffff
32: };
33: /* 640x480x8 */
34: static u16 cseq_640x480x8[] VAR16 = {
35: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
36: 0x580b,0x580c,0x580d,0x580e,
37: 0x0412,0x0013,0x2017,
38: 0x331b,0x331c,0x331d,0x331e,
39: 0xffff
40: };
41: static u16 ccrtc_640x480x8[] VAR16 = {
42: 0x2c11,
43: 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
44: 0x4009,0x000c,0x000d,
45: 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
46: 0x001a,0x221b,0x001d,
47: 0xffff
48: };
49: /* 640x480x16 */
50: static u16 cseq_640x480x16[] VAR16 = {
51: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
52: 0x580b,0x580c,0x580d,0x580e,
53: 0x0412,0x0013,0x2017,
54: 0x331b,0x331c,0x331d,0x331e,
55: 0xffff
56: };
57: static u16 ccrtc_640x480x16[] VAR16 = {
58: 0x2c11,
59: 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
60: 0x4009,0x000c,0x000d,
61: 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
62: 0x001a,0x221b,0x001d,
63: 0xffff
64: };
65: /* 640x480x24 */
66: static u16 cseq_640x480x24[] VAR16 = {
67: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
68: 0x580b,0x580c,0x580d,0x580e,
69: 0x0412,0x0013,0x2017,
70: 0x331b,0x331c,0x331d,0x331e,
71: 0xffff
72: };
73: static u16 ccrtc_640x480x24[] VAR16 = {
74: 0x2c11,
75: 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
76: 0x4009,0x000c,0x000d,
1.1.1.3 ! root 77: 0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
! 78: 0x001a,0x221b,0x001d,
1.1 root 79: 0xffff
80: };
81: /* 800x600x8 */
82: static u16 cseq_800x600x8[] VAR16 = {
83: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
84: 0x230b,0x230c,0x230d,0x230e,
85: 0x0412,0x0013,0x2017,
86: 0x141b,0x141c,0x141d,0x141e,
87: 0xffff
88: };
89: static u16 ccrtc_800x600x8[] VAR16 = {
90: 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
91: 0x6009,0x000c,0x000d,
92: 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
93: 0x001a,0x221b,0x001d,
94: 0xffff
95: };
96: /* 800x600x16 */
97: static u16 cseq_800x600x16[] VAR16 = {
98: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
99: 0x230b,0x230c,0x230d,0x230e,
100: 0x0412,0x0013,0x2017,
101: 0x141b,0x141c,0x141d,0x141e,
102: 0xffff
103: };
104: static u16 ccrtc_800x600x16[] VAR16 = {
105: 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
106: 0x6009,0x000c,0x000d,
107: 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
108: 0x001a,0x221b,0x001d,
109: 0xffff
110: };
111: /* 800x600x24 */
112: static u16 cseq_800x600x24[] VAR16 = {
113: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
114: 0x230b,0x230c,0x230d,0x230e,
115: 0x0412,0x0013,0x2017,
116: 0x141b,0x141c,0x141d,0x141e,
117: 0xffff
118: };
119: static u16 ccrtc_800x600x24[] VAR16 = {
120: 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
121: 0x6009,0x000c,0x000d,
122: 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
123: 0x001a,0x321b,0x001d,
124: 0xffff
125: };
126: /* 1024x768x8 */
127: static u16 cseq_1024x768x8[] VAR16 = {
128: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
129: 0x760b,0x760c,0x760d,0x760e,
130: 0x0412,0x0013,0x2017,
131: 0x341b,0x341c,0x341d,0x341e,
132: 0xffff
133: };
134: static u16 ccrtc_1024x768x8[] VAR16 = {
135: 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
136: 0x6009,0x000c,0x000d,
137: 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
138: 0x001a,0x221b,0x001d,
139: 0xffff
140: };
141: /* 1024x768x16 */
142: static u16 cseq_1024x768x16[] VAR16 = {
143: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
144: 0x760b,0x760c,0x760d,0x760e,
145: 0x0412,0x0013,0x2017,
146: 0x341b,0x341c,0x341d,0x341e,
147: 0xffff
148: };
149: static u16 ccrtc_1024x768x16[] VAR16 = {
150: 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
151: 0x6009,0x000c,0x000d,
152: 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
153: 0x001a,0x321b,0x001d,
154: 0xffff
155: };
156: /* 1024x768x24 */
157: static u16 cseq_1024x768x24[] VAR16 = {
158: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
159: 0x760b,0x760c,0x760d,0x760e,
160: 0x0412,0x0013,0x2017,
161: 0x341b,0x341c,0x341d,0x341e,
162: 0xffff
163: };
164: static u16 ccrtc_1024x768x24[] VAR16 = {
165: 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
166: 0x6009,0x000c,0x000d,
167: 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
168: 0x001a,0x321b,0x001d,
169: 0xffff
170: };
171: /* 1280x1024x8 */
172: static u16 cseq_1280x1024x8[] VAR16 = {
173: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
174: 0x760b,0x760c,0x760d,0x760e,
175: 0x0412,0x0013,0x2017,
176: 0x341b,0x341c,0x341d,0x341e,
177: 0xffff
178: };
179: static u16 ccrtc_1280x1024x8[] VAR16 = {
180: 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
181: 0x6009,0x000c,0x000d,
182: 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
183: 0x001a,0x221b,0x001d,
184: 0xffff
185: };
186: /* 1280x1024x16 */
187: static u16 cseq_1280x1024x16[] VAR16 = {
188: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
189: 0x760b,0x760c,0x760d,0x760e,
190: 0x0412,0x0013,0x2017,
191: 0x341b,0x341c,0x341d,0x341e,
192: 0xffff
193: };
194: static u16 ccrtc_1280x1024x16[] VAR16 = {
195: 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
196: 0x6009,0x000c,0x000d,
197: 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
198: 0x001a,0x321b,0x001d,
199: 0xffff
200: };
201:
202: /* 1600x1200x8 */
203: static u16 cseq_1600x1200x8[] VAR16 = {
204: 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
205: 0x760b,0x760c,0x760d,0x760e,
206: 0x0412,0x0013,0x2017,
207: 0x341b,0x341c,0x341d,0x341e,
208: 0xffff
209: };
210: static u16 ccrtc_1600x1200x8[] VAR16 = {
211: 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
212: 0x6009,0x000c,0x000d,
1.1.1.3 ! root 213: 0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
1.1 root 214: 0x001a,0x221b,0x001d,
215: 0xffff
216: };
217:
1.1.1.3 ! root 218: struct cirrus_mode_s {
! 219: u16 mode, vesamode;
! 220: struct vgamode_s info;
1.1 root 221:
1.1.1.3 ! root 222: u16 hidden_dac; /* 0x3c6 */
! 223: u16 *seq; /* 0x3c4 */
! 224: u16 *graph; /* 0x3ce */
! 225: u16 *crtc; /* 0x3d4 */
1.1 root 226: };
227:
1.1.1.3 ! root 228: static struct cirrus_mode_s cirrus_modes[] VAR16 = {
! 229: {0x5f,0x101,{MM_PACKED,640,480,8,8,16,SEG_GRAPH},0x00,
! 230: cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
! 231: {0x64,0x111,{MM_DIRECT,640,480,16,8,16,SEG_GRAPH},0xe1,
! 232: cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
! 233: {0x66,0x110,{MM_DIRECT,640,480,15,8,16,SEG_GRAPH},0xf0,
! 234: cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
! 235: {0x71,0x112,{MM_DIRECT,640,480,24,8,16,SEG_GRAPH},0xe5,
! 236: cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
! 237:
! 238: {0x5c,0x103,{MM_PACKED,800,600,8,8,16,SEG_GRAPH},0x00,
! 239: cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
! 240: {0x65,0x114,{MM_DIRECT,800,600,16,8,16,SEG_GRAPH},0xe1,
! 241: cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
! 242: {0x67,0x113,{MM_DIRECT,800,600,15,8,16,SEG_GRAPH},0xf0,
! 243: cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
! 244:
! 245: {0x60,0x105,{MM_PACKED,1024,768,8,8,16,SEG_GRAPH},0x00,
! 246: cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
! 247: {0x74,0x117,{MM_DIRECT,1024,768,16,8,16,SEG_GRAPH},0xe1,
! 248: cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
! 249: {0x68,0x116,{MM_DIRECT,1024,768,15,8,16,SEG_GRAPH},0xf0,
! 250: cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
! 251:
! 252: {0x78,0x115,{MM_DIRECT,800,600,24,8,16,SEG_GRAPH},0xe5,
! 253: cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
! 254: {0x79,0x118,{MM_DIRECT,1024,768,24,8,16,SEG_GRAPH},0xe5,
! 255: cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
! 256:
! 257: {0x6d,0x107,{MM_PACKED,1280,1024,8,8,16,SEG_GRAPH},0x00,
! 258: cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
! 259: {0x69,0x119,{MM_DIRECT,1280,1024,15,8,16,SEG_GRAPH},0xf0,
! 260: cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
! 261: {0x75,0x11a,{MM_DIRECT,1280,1024,16,8,16,SEG_GRAPH},0xe1,
! 262: cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
! 263:
! 264: {0x7b,0xffff,{MM_PACKED,1600,1200,8,8,16,SEG_GRAPH},0x00,
! 265: cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
! 266: };
! 267:
! 268: static struct cirrus_mode_s mode_switchback VAR16 =
! 269: {0xfe,0xffff,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
! 270:
! 271: int
! 272: is_cirrus_mode(struct vgamode_s *vmode_g)
! 273: {
! 274: return (vmode_g >= &cirrus_modes[0].info
! 275: && vmode_g <= &cirrus_modes[ARRAY_SIZE(cirrus_modes)-1].info);
! 276: }
! 277:
! 278: struct vgamode_s *
! 279: clext_find_mode(int mode)
1.1 root 280: {
281: struct cirrus_mode_s *table_g = cirrus_modes;
282: while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
1.1.1.3 ! root 283: if (GET_GLOBAL(table_g->mode) == mode
! 284: || GET_GLOBAL(table_g->vesamode) == mode)
! 285: return &table_g->info;
1.1 root 286: table_g++;
287: }
1.1.1.3 ! root 288: return stdvga_find_mode(mode);
! 289: }
! 290:
! 291: void
! 292: clext_list_modes(u16 seg, u16 *dest, u16 *last)
! 293: {
! 294: int i;
! 295: for (i=0; i<ARRAY_SIZE(cirrus_modes) && dest<last; i++) {
! 296: u16 mode = GET_GLOBAL(cirrus_modes[i].vesamode);
! 297: if (mode == 0xffff)
! 298: continue;
! 299: SET_FARVAR(seg, *dest, mode);
! 300: dest++;
! 301: }
! 302: stdvga_list_modes(seg, dest, last);
! 303: }
! 304:
! 305:
! 306: /****************************************************************
! 307: * helper functions
! 308: ****************************************************************/
! 309:
! 310: int
! 311: clext_get_window(struct vgamode_s *vmode_g, int window)
! 312: {
! 313: return stdvga_grdc_read(window + 9);
1.1 root 314: }
315:
1.1.1.3 ! root 316: int
! 317: clext_set_window(struct vgamode_s *vmode_g, int window, int val)
! 318: {
! 319: if (val >= 0x100)
! 320: return -1;
! 321: stdvga_grdc_write(window + 9, val);
! 322: return 0;
! 323: }
! 324:
! 325: int
! 326: clext_get_linelength(struct vgamode_s *vmode_g)
! 327: {
! 328: u16 crtc_addr = stdvga_get_crtc();
! 329: u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13);
! 330: u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b);
! 331: return (((reg1b & 0x10) << 4) + reg13) * stdvga_bpp_factor(vmode_g) * 2;
! 332: }
! 333:
! 334: int
! 335: clext_set_linelength(struct vgamode_s *vmode_g, int val)
! 336: {
! 337: u16 crtc_addr = stdvga_get_crtc();
! 338: int factor = stdvga_bpp_factor(vmode_g) * 2;
! 339: int new_line_offset = DIV_ROUND_UP(val, factor);
! 340: stdvga_crtc_write(crtc_addr, 0x13, new_line_offset);
! 341: stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (new_line_offset & 0x100) >> 4);
! 342: return 0;
! 343: }
! 344:
! 345: int
! 346: clext_get_displaystart(struct vgamode_s *vmode_g)
! 347: {
! 348: u16 crtc_addr = stdvga_get_crtc();
! 349: u8 b2 = stdvga_crtc_read(crtc_addr, 0x0c);
! 350: u8 b1 = stdvga_crtc_read(crtc_addr, 0x0d);
! 351: u8 b3 = stdvga_crtc_read(crtc_addr, 0x1b);
! 352: u8 b4 = stdvga_crtc_read(crtc_addr, 0x1d);
! 353: int val = (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
! 354: | ((b4 & 0x80) << 12));
! 355: return val * stdvga_bpp_factor(vmode_g);
! 356: }
! 357:
! 358: int
! 359: clext_set_displaystart(struct vgamode_s *vmode_g, int val)
! 360: {
! 361: u16 crtc_addr = stdvga_get_crtc();
! 362: val /= stdvga_bpp_factor(vmode_g);
! 363: stdvga_crtc_write(crtc_addr, 0x0d, val);
! 364: stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
! 365: stdvga_crtc_mask(crtc_addr, 0x1d, 0x80, (val & 0x0800) >> 4);
! 366: stdvga_crtc_mask(crtc_addr, 0x1b, 0x0d
! 367: , ((val & 0x0100) >> 8) | ((val & 0x0600) >> 7));
! 368: return 0;
! 369: }
! 370:
! 371: int
! 372: clext_size_state(int states)
! 373: {
! 374: if (states & 8)
! 375: return -1;
! 376: return stdvga_size_state(states);
! 377: }
! 378:
! 379: int
! 380: clext_save_state(u16 seg, void *data, int states)
! 381: {
! 382: if (states & 8)
! 383: return -1;
! 384: return stdvga_save_state(seg, data, states);
! 385: }
! 386:
! 387: int
! 388: clext_restore_state(u16 seg, void *data, int states)
! 389: {
! 390: if (states & 8)
! 391: return -1;
! 392: return stdvga_restore_state(seg, data, states);
! 393: }
! 394:
! 395:
! 396: /****************************************************************
! 397: * Mode setting
! 398: ****************************************************************/
! 399:
1.1 root 400: static void
401: cirrus_switch_mode_setregs(u16 *data, u16 port)
402: {
403: for (;;) {
404: u16 val = GET_GLOBAL(*data);
405: if (val == 0xffff)
406: return;
407: outw(val, port);
408: data++;
409: }
410: }
411:
412: static void
413: cirrus_switch_mode(struct cirrus_mode_s *table)
414: {
415: // Unlock cirrus special
1.1.1.3 ! root 416: stdvga_sequ_write(0x06, 0x12);
1.1 root 417: cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
418: cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
1.1.1.3 ! root 419: cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
1.1 root 420:
1.1.1.3 ! root 421: stdvga_pelmask_write(0x00);
! 422: stdvga_pelmask_read();
! 423: stdvga_pelmask_read();
! 424: stdvga_pelmask_read();
! 425: stdvga_pelmask_read();
! 426: stdvga_pelmask_write(GET_GLOBAL(table->hidden_dac));
! 427: stdvga_pelmask_write(0xff);
! 428:
! 429: u8 memmodel = GET_GLOBAL(table->info.memmodel);
! 430: u8 on = 0;
! 431: if (memmodel == MM_PLANAR)
! 432: on = 0x41;
! 433: else if (memmodel != MM_TEXT)
! 434: on = 0x01;
! 435: stdvga_attr_mask(0x10, 0x01, on);
1.1 root 436: }
437:
1.1.1.3 ! root 438: static void
! 439: cirrus_enable_16k_granularity(void)
! 440: {
! 441: stdvga_grdc_mask(0x0b, 0x00, 0x20);
! 442: }
! 443:
! 444: static void
! 445: cirrus_clear_vram(void)
1.1 root 446: {
1.1.1.3 ! root 447: cirrus_enable_16k_granularity();
! 448: u8 count = GET_GLOBAL(VBE_total_memory) / (16 * 1024);
! 449: u8 i;
! 450: for (i=0; i<count; i++) {
! 451: stdvga_grdc_write(0x09, i);
! 452: memset16_far(SEG_GRAPH, 0, 0, 16 * 1024);
1.1 root 453: }
1.1.1.3 ! root 454: stdvga_grdc_write(0x09, 0x00);
! 455: }
! 456:
! 457: int
! 458: clext_set_mode(struct vgamode_s *vmode_g, int flags)
! 459: {
! 460: if (!is_cirrus_mode(vmode_g)) {
! 461: cirrus_switch_mode(&mode_switchback);
! 462: dprintf(1, "cirrus mode switch regular\n");
! 463: return stdvga_set_mode(vmode_g, flags);
! 464: }
! 465: struct cirrus_mode_s *table_g = container_of(
! 466: vmode_g, struct cirrus_mode_s, info);
1.1 root 467: cirrus_switch_mode(table_g);
1.1.1.3 ! root 468: if (!(flags & MF_LINEARFB))
! 469: cirrus_enable_16k_granularity();
! 470: if (!(flags & MF_NOCLEARMEM))
! 471: cirrus_clear_vram();
! 472: return 0;
! 473: }
! 474:
! 475:
! 476: /****************************************************************
! 477: * extbios
! 478: ****************************************************************/
! 479:
! 480: static void
! 481: clext_101280(struct bregs *regs)
! 482: {
! 483: u8 v = stdvga_crtc_read(stdvga_get_crtc(), 0x27);
! 484: if (v == 0xa0)
! 485: // 5430
! 486: regs->ax = 0x0032;
! 487: else if (v == 0xb8)
! 488: // 5446
! 489: regs->ax = 0x0039;
! 490: else
! 491: regs->ax = 0x00ff;
! 492: regs->bx = 0x00;
! 493: return;
! 494: }
! 495:
! 496: static void
! 497: clext_101281(struct bregs *regs)
! 498: {
! 499: // XXX
! 500: regs->ax = 0x0100;
1.1 root 501: }
502:
1.1.1.3 ! root 503: static void
! 504: clext_101282(struct bregs *regs)
! 505: {
! 506: regs->al = stdvga_crtc_read(stdvga_get_crtc(), 0x27) & 0x03;
! 507: regs->ah = 0xAF;
! 508: }
! 509:
! 510: static void
! 511: clext_101285(struct bregs *regs)
! 512: {
! 513: regs->al = GET_GLOBAL(VBE_total_memory) / (64*1024);
! 514: }
! 515:
! 516: static void
! 517: clext_10129a(struct bregs *regs)
! 518: {
! 519: regs->ax = 0x4060;
! 520: regs->cx = 0x1132;
! 521: }
! 522:
! 523: extern void a0h_callback(void);
! 524: ASM16(
! 525: // fatal: not implemented yet
! 526: "a0h_callback:"
! 527: "cli\n"
! 528: "hlt\n"
! 529: "lretw");
! 530:
! 531: static void
! 532: clext_1012a0(struct bregs *regs)
! 533: {
! 534: struct vgamode_s *table_g = clext_find_mode(regs->al & 0x7f);
! 535: regs->ah = (table_g ? 1 : 0);
! 536: regs->bx = (u32)a0h_callback;
! 537: regs->ds = regs->si = regs->es = regs->di = 0xffff;
! 538: }
! 539:
! 540: static void
! 541: clext_1012a1(struct bregs *regs)
! 542: {
! 543: regs->bx = 0x0e00; // IBM 8512/8513, color
! 544: }
! 545:
! 546: static void
! 547: clext_1012a2(struct bregs *regs)
! 548: {
! 549: regs->al = 0x07; // HSync 31.5 - 64.0 kHz
! 550: }
! 551:
! 552: static void
! 553: clext_1012ae(struct bregs *regs)
! 554: {
! 555: regs->al = 0x01; // High Refresh 75Hz
! 556: }
! 557:
! 558: static void
! 559: clext_1012XX(struct bregs *regs)
! 560: {
! 561: debug_stub(regs);
! 562: }
! 563:
! 564: void
! 565: clext_1012(struct bregs *regs)
! 566: {
! 567: switch (regs->bl) {
! 568: case 0x80: clext_101280(regs); break;
! 569: case 0x81: clext_101281(regs); break;
! 570: case 0x82: clext_101282(regs); break;
! 571: case 0x85: clext_101285(regs); break;
! 572: case 0x9a: clext_10129a(regs); break;
! 573: case 0xa0: clext_1012a0(regs); break;
! 574: case 0xa1: clext_1012a1(regs); break;
! 575: case 0xa2: clext_1012a2(regs); break;
! 576: case 0xae: clext_1012ae(regs); break;
! 577: default: clext_1012XX(regs); break;
! 578: }
! 579: }
! 580:
! 581:
! 582: /****************************************************************
! 583: * init
! 584: ****************************************************************/
! 585:
1.1 root 586: static int
1.1.1.2 root 587: cirrus_check(void)
1.1 root 588: {
1.1.1.3 ! root 589: stdvga_sequ_write(0x06, 0x92);
! 590: return stdvga_sequ_read(0x06) == 0x12;
1.1 root 591: }
592:
1.1.1.3 ! root 593: static u8
! 594: cirrus_get_memsize(void)
! 595: {
! 596: // get DRAM band width
! 597: u8 v = stdvga_sequ_read(0x0f);
! 598: u8 x = (v >> 3) & 0x03;
! 599: if (x == 0x03 && v & 0x80)
! 600: // 4MB
! 601: return 0x40;
! 602: return 0x04 << x;
! 603: }
! 604:
! 605: int
! 606: clext_init(void)
1.1 root 607: {
1.1.1.3 ! root 608: int ret = stdvga_init();
! 609: if (ret)
! 610: return ret;
! 611:
1.1 root 612: dprintf(1, "cirrus init\n");
613: if (! cirrus_check())
1.1.1.3 ! root 614: return -1;
1.1 root 615: dprintf(1, "cirrus init 2\n");
616:
617: // memory setup
1.1.1.3 ! root 618: stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
1.1 root 619: // set vga mode
1.1.1.3 ! root 620: stdvga_sequ_write(0x07, 0x00);
1.1 root 621: // reset bitblt
1.1.1.3 ! root 622: stdvga_grdc_write(0x31, 0x04);
! 623: stdvga_grdc_write(0x31, 0x00);
! 624:
! 625: if (GET_GLOBAL(HaveRunInit))
! 626: return 0;
! 627:
! 628: u32 lfb_addr = 0;
! 629: int bdf = GET_GLOBAL(VgaBDF);
! 630: if (CONFIG_VGA_PCI && bdf >= 0)
! 631: lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
! 632: & PCI_BASE_ADDRESS_MEM_MASK);
! 633: SET_VGA(VBE_framebuffer, lfb_addr);
! 634: u16 totalmem = cirrus_get_memsize();
! 635: SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
! 636: SET_VGA(VBE_win_granularity, 16);
! 637:
! 638: return 0;
1.1 root 639: }
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