File:  [Qemu by Fabrice Bellard] / qemu / sparc-dis.c
Revision 1.1.1.7 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 18:24:37 2018 UTC (3 years, 5 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu1101, qemu1001, qemu1000, qemu0151, qemu0150, qemu0141, qemu0140, qemu0130, HEAD
qemu 0.13.0

    1: /*
    2:  * These files from binutils are concatenated:
    3:  * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
    4:  */
    5: 
    6: /* include/opcode/sparc.h */
    7: 
    8: /* Definitions for opcode table for the sparc.
    9:    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
   10:    2003, 2005 Free Software Foundation, Inc.
   11: 
   12:    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   13:    the GNU Binutils.
   14: 
   15:    GAS/GDB is free software; you can redistribute it and/or modify
   16:    it under the terms of the GNU General Public License as published by
   17:    the Free Software Foundation; either version 2, or (at your option)
   18:    any later version.
   19: 
   20:    GAS/GDB is distributed in the hope that it will be useful,
   21:    but WITHOUT ANY WARRANTY; without even the implied warranty of
   22:    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
   23:    GNU General Public License for more details.
   24: 
   25:    You should have received a copy of the GNU General Public License
   26:    along with GAS or GDB; see the file COPYING. If not,
   27:    see <http://www.gnu.org/licenses/>.  */
   28: 
   29: #include <stdlib.h>
   30: #include "dis-asm.h"
   31: 
   32: /* The SPARC opcode table (and other related data) is defined in
   33:    the opcodes library in sparc-opc.c.  If you change anything here, make
   34:    sure you fix up that file, and vice versa.  */
   35: 
   36:  /* FIXME-someday: perhaps the ,a's and such should be embedded in the
   37:     instruction's name rather than the args.  This would make gas faster, pinsn
   38:     slower, but would mess up some macros a bit.  xoxorich. */
   39: 
   40: /* List of instruction sets variations.
   41:    These values are such that each element is either a superset of a
   42:    preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
   43:    returns non-zero.
   44:    The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
   45:    Don't change this without updating sparc-opc.c.  */
   46: 
   47: enum sparc_opcode_arch_val
   48: {
   49:   SPARC_OPCODE_ARCH_V6 = 0,
   50:   SPARC_OPCODE_ARCH_V7,
   51:   SPARC_OPCODE_ARCH_V8,
   52:   SPARC_OPCODE_ARCH_SPARCLET,
   53:   SPARC_OPCODE_ARCH_SPARCLITE,
   54:   /* V9 variants must appear last.  */
   55:   SPARC_OPCODE_ARCH_V9,
   56:   SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions.  */
   57:   SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions.  */
   58:   SPARC_OPCODE_ARCH_BAD  /* Error return from sparc_opcode_lookup_arch.  */
   59: };
   60: 
   61: /* The highest architecture in the table.  */
   62: #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
   63: 
   64: /* Given an enum sparc_opcode_arch_val, return the bitmask to use in
   65:    insn encoding/decoding.  */
   66: #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
   67: 
   68: /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */
   69: #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
   70: 
   71: /* Table of cpu variants.  */
   72: 
   73: typedef struct sparc_opcode_arch
   74: {
   75:   const char *name;
   76:   /* Mask of sparc_opcode_arch_val's supported.
   77:      EG: For v7 this would be
   78:      (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
   79:      These are short's because sparc_opcode.architecture is.  */
   80:   short supported;
   81: } sparc_opcode_arch;
   82: 
   83: static const struct sparc_opcode_arch sparc_opcode_archs[];
   84: 
   85: /* Return the bitmask of supported architectures for ARCH.  */
   86: #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
   87: 
   88: /* Non-zero if ARCH1 conflicts with ARCH2.
   89:    IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */
   90: #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
   91:  (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
   92:    != SPARC_OPCODE_SUPPORTED (ARCH1)) \
   93:   && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
   94:      != SPARC_OPCODE_SUPPORTED (ARCH2)))
   95: 
   96: /* Structure of an opcode table entry.  */
   97: 
   98: typedef struct sparc_opcode
   99: {
  100:   const char *name;
  101:   unsigned long match;  /* Bits that must be set.  */
  102:   unsigned long lose;   /* Bits that must not be set.  */
  103:   const char *args;
  104:   /* This was called "delayed" in versions before the flags.  */
  105:   char flags;
  106:   short architecture;   /* Bitmask of sparc_opcode_arch_val's.  */
  107: } sparc_opcode;
  108: 
  109: #define F_DELAYED       1       /* Delayed branch.  */
  110: #define F_ALIAS         2       /* Alias for a "real" instruction.  */
  111: #define F_UNBR          4       /* Unconditional branch.  */
  112: #define F_CONDBR        8       /* Conditional branch.  */
  113: #define F_JSR           16      /* Subroutine call.  */
  114: #define F_FLOAT         32      /* Floating point instruction (not a branch).  */
  115: #define F_FBR           64      /* Floating point branch.  */
  116: /* FIXME: Add F_ANACHRONISTIC flag for v9.  */
  117: 
  118: /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
  119:    macro), which is 64 bits. It is handled as a special case.
  120: 
  121:    The match component is a mask saying which bits must match a particular
  122:    opcode in order for an instruction to be an instance of that opcode.
  123: 
  124:    The args component is a string containing one character for each operand of the
  125:    instruction.
  126: 
  127:    Kinds of operands:
  128:         #       Number used by optimizer.       It is ignored.
  129:         1       rs1 register.
  130:         2       rs2 register.
  131:         d       rd register.
  132:         e       frs1 floating point register.
  133:         v       frs1 floating point register (double/even).
  134:         V       frs1 floating point register (quad/multiple of 4).
  135:         f       frs2 floating point register.
  136:         B       frs2 floating point register (double/even).
  137:         R       frs2 floating point register (quad/multiple of 4).
  138:         g       frsd floating point register.
  139:         H       frsd floating point register (double/even).
  140:         J       frsd floating point register (quad/multiple of 4).
  141:         b       crs1 coprocessor register
  142:         c       crs2 coprocessor register
  143:         D       crsd coprocessor register
  144:         m       alternate space register (asr) in rd
  145:         M       alternate space register (asr) in rs1
  146:         h       22 high bits.
  147:         X       5 bit unsigned immediate
  148:         Y       6 bit unsigned immediate
  149:         3       SIAM mode (3 bits). (v9b)
  150:         K       MEMBAR mask (7 bits). (v9)
  151:         j       10 bit Immediate. (v9)
  152:         I       11 bit Immediate. (v9)
  153:         i       13 bit Immediate.
  154:         n       22 bit immediate.
  155:         k       2+14 bit PC relative immediate. (v9)
  156:         G       19 bit PC relative immediate. (v9)
  157:         l       22 bit PC relative immediate.
  158:         L       30 bit PC relative immediate.
  159:         a       Annul.  The annul bit is set.
  160:         A       Alternate address space. Stored as 8 bits.
  161:         C       Coprocessor state register.
  162:         F       floating point state register.
  163:         p       Processor state register.
  164:         N       Branch predict clear ",pn" (v9)
  165:         T       Branch predict set ",pt" (v9)
  166:         z       %icc. (v9)
  167:         Z       %xcc. (v9)
  168:         q       Floating point queue.
  169:         r       Single register that is both rs1 and rd.
  170:         O       Single register that is both rs2 and rd.
  171:         Q       Coprocessor queue.
  172:         S       Special case.
  173:         t       Trap base register.
  174:         w       Window invalid mask register.
  175:         y       Y register.
  176:         u       sparclet coprocessor registers in rd position
  177:         U       sparclet coprocessor registers in rs1 position
  178:         E       %ccr. (v9)
  179:         s       %fprs. (v9)
  180:         P       %pc.  (v9)
  181:         W       %tick.  (v9)
  182:         o       %asi. (v9)
  183:         6       %fcc0. (v9)
  184:         7       %fcc1. (v9)
  185:         8       %fcc2. (v9)
  186:         9       %fcc3. (v9)
  187:         !       Privileged Register in rd (v9)
  188:         ?       Privileged Register in rs1 (v9)
  189:         *       Prefetch function constant. (v9)
  190:         x       OPF field (v9 impdep).
  191:         0       32/64 bit immediate for set or setx (v9) insns
  192:         _       Ancillary state register in rd (v9a)
  193:         /       Ancillary state register in rs1 (v9a)
  194: 
  195:   The following chars are unused: (note: ,[] are used as punctuation)
  196:   [45].  */
  197: 
  198: #define OP2(x)          (((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */
  199: #define OP3(x)          (((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */
  200: #define OP(x)           ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns.  */
  201: #define OPF(x)          (((x) & 0x1ff) << 5) /* Opf field of float insns.  */
  202: #define OPF_LOW5(x)     OPF ((x) & 0x1f)     /* V9.  */
  203: #define F3F(x, y, z)    (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
  204: #define F3I(x)          (((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
  205: #define F2(x, y)        (OP (x) | OP2(y))    /* Format 2 insns.  */
  206: #define F3(x, y, z)     (OP (x) | OP3(y) | F3I(z)) /* Format3 insns.  */
  207: #define F1(x)           (OP (x))
  208: #define DISP30(x)       ((x) & 0x3fffffff)
  209: #define ASI(x)          (((x) & 0xff) << 5)  /* Asi field of format3 insns.  */
  210: #define RS2(x)          ((x) & 0x1f)         /* Rs2 field.  */
  211: #define SIMM13(x)       ((x) & 0x1fff)       /* Simm13 field.  */
  212: #define RD(x)           (((x) & 0x1f) << 25) /* Destination register field.  */
  213: #define RS1(x)          (((x) & 0x1f) << 14) /* Rs1 field.  */
  214: #define ASI_RS2(x)      (SIMM13 (x))
  215: #define MEMBAR(x)       ((x) & 0x7f)
  216: #define SLCPOP(x)       (((x) & 0x7f) << 6)  /* Sparclet cpop.  */
  217: 
  218: #define ANNUL   (1 << 29)
  219: #define BPRED   (1 << 19)       /* V9.  */
  220: #define IMMED   F3I (1)
  221: #define RD_G0   RD (~0)
  222: #define RS1_G0  RS1 (~0)
  223: #define RS2_G0  RS2 (~0)
  224: 
  225: static const struct sparc_opcode sparc_opcodes[];
  226: 
  227: static const char *sparc_decode_asi_v8 (int);
  228: static const char *sparc_decode_asi_v9 (int);
  229: static const char *sparc_decode_membar (int);
  230: static const char *sparc_decode_prefetch (int);
  231: static const char *sparc_decode_sparclet_cpreg (int);
  232: 
  233: /* Local Variables:
  234:    fill-column: 131
  235:    comment-column: 0
  236:    End: */
  237: 
  238: /* opcodes/sparc-opc.c */
  239: 
  240: /* Table of opcodes for the sparc.
  241:    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
  242:    2000, 2002, 2004, 2005
  243:    Free Software Foundation, Inc.
  244: 
  245:    This file is part of the BFD library.
  246: 
  247:    BFD is free software; you can redistribute it and/or modify it under
  248:    the terms of the GNU General Public License as published by the Free
  249:    Software Foundation; either version 2, or (at your option) any later
  250:    version.
  251: 
  252:    BFD is distributed in the hope that it will be useful, but WITHOUT ANY
  253:    WARRANTY; without even the implied warranty of MERCHANTABILITY or
  254:    FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  255:    for more details.
  256: 
  257:    You should have received a copy of the GNU General Public License
  258:    along with this software; see the file COPYING.  If not,
  259:    see <http://www.gnu.org/licenses/>.  */
  260: 
  261: /* FIXME-someday: perhaps the ,a's and such should be embedded in the
  262:    instruction's name rather than the args.  This would make gas faster, pinsn
  263:    slower, but would mess up some macros a bit.  xoxorich. */
  264: 
  265: /* Some defines to make life easy.  */
  266: #define MASK_V6         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
  267: #define MASK_V7         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
  268: #define MASK_V8         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
  269: #define MASK_SPARCLET   SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
  270: #define MASK_SPARCLITE  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
  271: #define MASK_V9         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
  272: #define MASK_V9A        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
  273: #define MASK_V9B        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
  274: 
  275: /* Bit masks of architectures supporting the insn.  */
  276: 
  277: #define v6              (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
  278:                          | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
  279: /* v6 insns not supported on the sparclet.  */
  280: #define v6notlet        (MASK_V6 | MASK_V7 | MASK_V8 \
  281:                          | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
  282: #define v7              (MASK_V7 | MASK_V8 | MASK_SPARCLET \
  283:                          | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
  284: /* Although not all insns are implemented in hardware, sparclite is defined
  285:    to be a superset of v8.  Unimplemented insns trap and are then theoretically
  286:    implemented in software.
  287:    It's not clear that the same is true for sparclet, although the docs
  288:    suggest it is.  Rather than complicating things, the sparclet assembler
  289:    recognizes all v8 insns.  */
  290: #define v8              (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
  291:                          | MASK_V9 | MASK_V9A | MASK_V9B)
  292: #define sparclet        (MASK_SPARCLET)
  293: #define sparclite       (MASK_SPARCLITE)
  294: #define v9              (MASK_V9 | MASK_V9A | MASK_V9B)
  295: #define v9a             (MASK_V9A | MASK_V9B)
  296: #define v9b             (MASK_V9B)
  297: /* v6 insns not supported by v9.  */
  298: #define v6notv9         (MASK_V6 | MASK_V7 | MASK_V8 \
  299:                          | MASK_SPARCLET | MASK_SPARCLITE)
  300: /* v9a instructions which would appear to be aliases to v9's impdep's
  301:    otherwise.  */
  302: #define v9notv9a        (MASK_V9)
  303: 
  304: /* Table of opcode architectures.
  305:    The order is defined in opcode/sparc.h.  */
  306: 
  307: static const struct sparc_opcode_arch sparc_opcode_archs[] =
  308: {
  309:   { "v6", MASK_V6 },
  310:   { "v7", MASK_V6 | MASK_V7 },
  311:   { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
  312:   { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
  313:   { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
  314:   /* ??? Don't some v8 privileged insns conflict with v9?  */
  315:   { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
  316:   /* v9 with ultrasparc additions */
  317:   { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
  318:   /* v9 with cheetah additions */
  319:   { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
  320:   { NULL, 0 }
  321: };
  322: 
  323: /* Branch condition field.  */
  324: #define COND(x)         (((x) & 0xf) << 25)
  325: 
  326: /* v9: Move (MOVcc and FMOVcc) condition field.  */
  327: #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
  328: 
  329: /* v9: Move register (MOVRcc and FMOVRcc) condition field.  */
  330: #define RCOND(x)        (((x) & 0x7) << 10)     /* v9 */
  331: 
  332: #define CONDA   (COND (0x8))
  333: #define CONDCC  (COND (0xd))
  334: #define CONDCS  (COND (0x5))
  335: #define CONDE   (COND (0x1))
  336: #define CONDG   (COND (0xa))
  337: #define CONDGE  (COND (0xb))
  338: #define CONDGU  (COND (0xc))
  339: #define CONDL   (COND (0x3))
  340: #define CONDLE  (COND (0x2))
  341: #define CONDLEU (COND (0x4))
  342: #define CONDN   (COND (0x0))
  343: #define CONDNE  (COND (0x9))
  344: #define CONDNEG (COND (0x6))
  345: #define CONDPOS (COND (0xe))
  346: #define CONDVC  (COND (0xf))
  347: #define CONDVS  (COND (0x7))
  348: 
  349: #define CONDNZ  CONDNE
  350: #define CONDZ   CONDE
  351: #define CONDGEU CONDCC
  352: #define CONDLU  CONDCS
  353: 
  354: #define FCONDA          (COND (0x8))
  355: #define FCONDE          (COND (0x9))
  356: #define FCONDG          (COND (0x6))
  357: #define FCONDGE         (COND (0xb))
  358: #define FCONDL          (COND (0x4))
  359: #define FCONDLE         (COND (0xd))
  360: #define FCONDLG         (COND (0x2))
  361: #define FCONDN          (COND (0x0))
  362: #define FCONDNE         (COND (0x1))
  363: #define FCONDO          (COND (0xf))
  364: #define FCONDU          (COND (0x7))
  365: #define FCONDUE         (COND (0xa))
  366: #define FCONDUG         (COND (0x5))
  367: #define FCONDUGE        (COND (0xc))
  368: #define FCONDUL         (COND (0x3))
  369: #define FCONDULE        (COND (0xe))
  370: 
  371: #define FCONDNZ FCONDNE
  372: #define FCONDZ  FCONDE
  373: 
  374: #define ICC             (0)     /* v9 */
  375: #define XCC             (1 << 12) /* v9 */
  376: #define FCC(x)          (((x) & 0x3) << 11) /* v9 */
  377: #define FBFCC(x)        (((x) & 0x3) << 20)     /* v9 */
  378: 
  379: /* The order of the opcodes in the table is significant:
  380: 
  381:         * The assembler requires that all instances of the same mnemonic must
  382:         be consecutive. If they aren't, the assembler will bomb at runtime.
  383: 
  384:         * The disassembler should not care about the order of the opcodes.  */
  385: 
  386: /* Entries for commutative arithmetic operations.  */
  387: /* ??? More entries can make use of this.  */
  388: #define COMMUTEOP(opcode, op3, arch_mask) \
  389: { opcode,       F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),        "1,2,d", 0, arch_mask }, \
  390: { opcode,       F3(2, op3, 1), F3(~2, ~op3, ~1),                "1,i,d", 0, arch_mask }, \
  391: { opcode,       F3(2, op3, 1), F3(~2, ~op3, ~1),                "i,1,d", 0, arch_mask }
  392: 
  393: static const struct sparc_opcode sparc_opcodes[] = {
  394: 
  395: { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", 0, v6 },
  396: { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
  397: { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", 0, v6 },
  398: { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", 0, v6 },
  399: { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", 0, v6 },
  400: { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ld [rs1+0],d */
  401: { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0),              "[1+2],g", 0, v6 },
  402: { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0,       "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
  403: { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[1+i],g", 0, v6 },
  404: { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[i+1],g", 0, v6 },
  405: { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,       "[i],g", 0, v6 },
  406: { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),   "[1],g", 0, v6 }, /* ld [rs1+0],d */
  407: 
  408: { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0),       "[1+2],F", 0, v6 },
  409: { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
  410: { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[1+i],F", 0, v6 },
  411: { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[i+1],F", 0, v6 },
  412: { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
  413: { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
  414: 
  415: { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0),              "[1+2],D", 0, v6notv9 },
  416: { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,       "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */
  417: { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i],D", 0, v6notv9 },
  418: { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1],D", 0, v6notv9 },
  419: { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i],D", 0, v6notv9 },
  420: { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),   "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */
  421: { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0),              "[1+2],C", 0, v6notv9 },
  422: { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0,       "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */
  423: { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[1+i],C", 0, v6notv9 },
  424: { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[i+1],C", 0, v6notv9 },
  425: { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0,       "[i],C", 0, v6notv9 },
  426: { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0),   "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */
  427: 
  428: /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
  429:    'ld' pseudo-op in v9.  */
  430: { "lduw",       F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", F_ALIAS, v9 },
  431: { "lduw",       F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */
  432: { "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", F_ALIAS, v9 },
  433: { "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", F_ALIAS, v9 },
  434: { "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", F_ALIAS, v9 },
  435: { "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */
  436: 
  437: { "ldd",        F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
  438: { "ldd",        F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
  439: { "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", 0, v6 },
  440: { "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", 0, v6 },
  441: { "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", 0, v6 },
  442: { "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldd [rs1+0],d */
  443: { "ldd",        F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),      "[1+2],H", 0, v6 },
  444: { "ldd",        F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),  "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */
  445: { "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[1+i],H", 0, v6 },
  446: { "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[i+1],H", 0, v6 },
  447: { "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,       "[i],H", 0, v6 },
  448: { "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),   "[1],H", 0, v6 }, /* ldd [rs1+0],d */
  449: 
  450: { "ldd",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),      "[1+2],D", 0, v6notv9 },
  451: { "ldd",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),  "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */
  452: { "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i],D", 0, v6notv9 },
  453: { "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1],D", 0, v6notv9 },
  454: { "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i],D", 0, v6notv9 },
  455: { "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),   "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */
  456: 
  457: { "ldq",        F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0),      "[1+2],J", 0, v9 },
  458: { "ldq",        F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0),  "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */
  459: { "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[1+i],J", 0, v9 },
  460: { "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[i+1],J", 0, v9 },
  461: { "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0,       "[i],J", 0, v9 },
  462: { "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0),   "[1],J", 0, v9 }, /* ldd [rs1+0],d */
  463: 
  464: { "ldsb",       F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
  465: { "ldsb",       F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
  466: { "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[1+i],d", 0, v6 },
  467: { "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[i+1],d", 0, v6 },
  468: { "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0,       "[i],d", 0, v6 },
  469: { "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldsb [rs1+0],d */
  470: 
  471: { "ldsh",       F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
  472: { "ldsh",       F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
  473: { "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[1+i],d", 0, v6 },
  474: { "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[i+1],d", 0, v6 },
  475: { "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0,       "[i],d", 0, v6 },
  476: { "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldsh [rs1+0],d */
  477: 
  478: { "ldstub",     F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
  479: { "ldstub",     F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
  480: { "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[1+i],d", 0, v6 },
  481: { "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[i+1],d", 0, v6 },
  482: { "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0,       "[i],d", 0, v6 },
  483: { "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldstub [rs1+0],d */
  484: 
  485: { "ldsw",       F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0),      "[1+2],d", 0, v9 },
  486: { "ldsw",       F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0),  "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */
  487: { "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[1+i],d", 0, v9 },
  488: { "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[i+1],d", 0, v9 },
  489: { "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0,       "[i],d", 0, v9 },
  490: { "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0),   "[1],d", 0, v9 }, /* ldsw [rs1+0],d */
  491: 
  492: { "ldub",       F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
  493: { "ldub",       F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
  494: { "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[1+i],d", 0, v6 },
  495: { "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[i+1],d", 0, v6 },
  496: { "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0,       "[i],d", 0, v6 },
  497: { "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldub [rs1+0],d */
  498: 
  499: { "lduh",       F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
  500: { "lduh",       F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
  501: { "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[1+i],d", 0, v6 },
  502: { "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[i+1],d", 0, v6 },
  503: { "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,       "[i],d", 0, v6 },
  504: { "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* lduh [rs1+0],d */
  505: 
  506: { "ldx",        F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0),      "[1+2],d", 0, v9 },
  507: { "ldx",        F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0),  "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */
  508: { "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[1+i],d", 0, v9 },
  509: { "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[i+1],d", 0, v9 },
  510: { "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0,       "[i],d", 0, v9 },
  511: { "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0),   "[1],d", 0, v9 }, /* ldx [rs1+0],d */
  512: 
  513: { "ldx",        F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 },
  514: { "ldx",        F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1),  "[1],F", 0, v9 }, /* ld [rs1+%g0],d */
  515: { "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 },
  516: { "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 },
  517: { "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1),  "[i],F", 0, v9 },
  518: { "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
  519: 
  520: { "lda",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0),              "[1+2]A,d", 0, v6 },
  521: { "lda",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
  522: { "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[1+i]o,d", 0, v9 },
  523: { "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[i+1]o,d", 0, v9 },
  524: { "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  525: { "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  526: { "lda",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0),              "[1+2]A,g", 0, v9 },
  527: { "lda",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,       "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */
  528: { "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i]o,g", 0, v9 },
  529: { "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1]o,g", 0, v9 },
  530: { "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i]o,g", 0, v9 },
  531: { "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),   "[1]o,g", 0, v9 }, /* ld [rs1+0],d */
  532: 
  533: { "ldda",       F3(3, 0x13, 0), F3(~3, ~0x13, ~0),              "[1+2]A,d", 0, v6 },
  534: { "ldda",       F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
  535: { "ldda",       F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[1+i]o,d", 0, v9 },
  536: { "ldda",       F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[i+1]o,d", 0, v9 },
  537: { "ldda",       F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  538: { "ldda",       F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  539: 
  540: { "ldda",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0),              "[1+2]A,H", 0, v9 },
  541: { "ldda",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0,       "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */
  542: { "ldda",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i]o,H", 0, v9 },
  543: { "ldda",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1]o,H", 0, v9 },
  544: { "ldda",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i]o,H", 0, v9 },
  545: { "ldda",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),   "[1]o,H", 0, v9 }, /* ld [rs1+0],d */
  546: 
  547: { "ldqa",       F3(3, 0x32, 0), F3(~3, ~0x32, ~0),              "[1+2]A,J", 0, v9 },
  548: { "ldqa",       F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0,       "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */
  549: { "ldqa",       F3(3, 0x32, 1), F3(~3, ~0x32, ~1),              "[1+i]o,J", 0, v9 },
  550: { "ldqa",       F3(3, 0x32, 1), F3(~3, ~0x32, ~1),              "[i+1]o,J", 0, v9 },
  551: { "ldqa",       F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0,       "[i]o,J", 0, v9 },
  552: { "ldqa",       F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0),   "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */
  553: 
  554: { "ldsba",      F3(3, 0x19, 0), F3(~3, ~0x19, ~0),              "[1+2]A,d", 0, v6 },
  555: { "ldsba",      F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
  556: { "ldsba",      F3(3, 0x19, 1), F3(~3, ~0x19, ~1),              "[1+i]o,d", 0, v9 },
  557: { "ldsba",      F3(3, 0x19, 1), F3(~3, ~0x19, ~1),              "[i+1]o,d", 0, v9 },
  558: { "ldsba",      F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  559: { "ldsba",      F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  560: 
  561: { "ldsha",      F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0),              "[1+2]A,d", 0, v6 },
  562: { "ldsha",      F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
  563: { "ldsha",      F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),              "[1+i]o,d", 0, v9 },
  564: { "ldsha",      F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),              "[i+1]o,d", 0, v9 },
  565: { "ldsha",      F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  566: { "ldsha",      F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  567: 
  568: { "ldstuba",    F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0),              "[1+2]A,d", 0, v6 },
  569: { "ldstuba",    F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
  570: { "ldstuba",    F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),              "[1+i]o,d", 0, v9 },
  571: { "ldstuba",    F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),              "[i+1]o,d", 0, v9 },
  572: { "ldstuba",    F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  573: { "ldstuba",    F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  574: 
  575: { "ldswa",      F3(3, 0x18, 0), F3(~3, ~0x18, ~0),              "[1+2]A,d", 0, v9 },
  576: { "ldswa",      F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0,       "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
  577: { "ldswa",      F3(3, 0x18, 1), F3(~3, ~0x18, ~1),              "[1+i]o,d", 0, v9 },
  578: { "ldswa",      F3(3, 0x18, 1), F3(~3, ~0x18, ~1),              "[i+1]o,d", 0, v9 },
  579: { "ldswa",      F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  580: { "ldswa",      F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  581: 
  582: { "lduba",      F3(3, 0x11, 0), F3(~3, ~0x11, ~0),              "[1+2]A,d", 0, v6 },
  583: { "lduba",      F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
  584: { "lduba",      F3(3, 0x11, 1), F3(~3, ~0x11, ~1),              "[1+i]o,d", 0, v9 },
  585: { "lduba",      F3(3, 0x11, 1), F3(~3, ~0x11, ~1),              "[i+1]o,d", 0, v9 },
  586: { "lduba",      F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  587: { "lduba",      F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  588: 
  589: { "lduha",      F3(3, 0x12, 0), F3(~3, ~0x12, ~0),              "[1+2]A,d", 0, v6 },
  590: { "lduha",      F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
  591: { "lduha",      F3(3, 0x12, 1), F3(~3, ~0x12, ~1),              "[1+i]o,d", 0, v9 },
  592: { "lduha",      F3(3, 0x12, 1), F3(~3, ~0x12, ~1),              "[i+1]o,d", 0, v9 },
  593: { "lduha",      F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  594: { "lduha",      F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  595: 
  596: { "lduwa",      F3(3, 0x10, 0), F3(~3, ~0x10, ~0),              "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */
  597: { "lduwa",      F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,       "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */
  598: { "lduwa",      F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[1+i]o,d", F_ALIAS, v9 },
  599: { "lduwa",      F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[i+1]o,d", F_ALIAS, v9 },
  600: { "lduwa",      F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,       "[i]o,d", F_ALIAS, v9 },
  601: { "lduwa",      F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),   "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */
  602: 
  603: { "ldxa",       F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0),              "[1+2]A,d", 0, v9 },
  604: { "ldxa",       F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0,       "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
  605: { "ldxa",       F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),              "[1+i]o,d", 0, v9 },
  606: { "ldxa",       F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),              "[i+1]o,d", 0, v9 },
  607: { "ldxa",       F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  608: { "ldxa",       F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
  609: 
  610: { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),              "d,[1+2]", 0, v6 },
  611: { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),          "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
  612: { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[1+i]", 0, v6 },
  613: { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[i+1]", 0, v6 },
  614: { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,               "d,[i]", 0, v6 },
  615: { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),           "d,[1]", 0, v6 }, /* st d,[rs1+0] */
  616: { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),              "g,[1+2]", 0, v6 },
  617: { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),          "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
  618: { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[1+i]", 0, v6 },
  619: { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[i+1]", 0, v6 },
  620: { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,               "g,[i]", 0, v6 },
  621: { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),           "g,[1]", 0, v6 }, /* st d,[rs1+0] */
  622: 
  623: { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),              "D,[1+2]", 0, v6notv9 },
  624: { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),          "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
  625: { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[1+i]", 0, v6notv9 },
  626: { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[i+1]", 0, v6notv9 },
  627: { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,               "D,[i]", 0, v6notv9 },
  628: { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),           "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
  629: { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),              "C,[1+2]", 0, v6notv9 },
  630: { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),          "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
  631: { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[1+i]", 0, v6notv9 },
  632: { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[i+1]", 0, v6notv9 },
  633: { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,               "C,[i]", 0, v6notv9 },
  634: { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),           "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
  635: 
  636: { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),        "F,[1+2]", 0, v6 },
  637: { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),    "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
  638: { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[1+i]", 0, v6 },
  639: { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[i+1]", 0, v6 },
  640: { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,         "F,[i]", 0, v6 },
  641: { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0),     "F,[1]", 0, v6 }, /* st d,[rs1+0] */
  642: 
  643: { "stw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, v9 },
  644: { "stw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
  645: { "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, v9 },
  646: { "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, v9 },
  647: { "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v9 },
  648: { "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
  649: { "stsw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, v9 },
  650: { "stsw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
  651: { "stsw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, v9 },
  652: { "stsw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, v9 },
  653: { "stsw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v9 },
  654: { "stsw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
  655: { "stuw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, v9 },
  656: { "stuw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
  657: { "stuw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, v9 },
  658: { "stuw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, v9 },
  659: { "stuw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v9 },
  660: { "stuw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
  661: 
  662: { "spill",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, v6 },
  663: { "spill",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */
  664: { "spill",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, v6 },
  665: { "spill",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, v6 },
  666: { "spill",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
  667: { "spill",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */
  668: 
  669: { "sta",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", 0, v6 },
  670: { "sta",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
  671: { "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", 0, v9 },
  672: { "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", 0, v9 },
  673: { "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
  674: { "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", 0, v9 }, /* st d,[rs1+0] */
  675: 
  676: { "sta",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0),              "g,[1+2]A", 0, v9 },
  677: { "sta",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0),      "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */
  678: { "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),              "g,[1+i]o", 0, v9 },
  679: { "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),              "g,[i+1]o", 0, v9 },
  680: { "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,       "g,[i]o", 0, v9 },
  681: { "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),   "g,[1]o", 0, v9 }, /* st d,[rs1+0] */
  682: 
  683: { "stwa",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", F_ALIAS, v9 },
  684: { "stwa",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
  685: { "stwa",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, v9 },
  686: { "stwa",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, v9 },
  687: { "stwa",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
  688: { "stwa",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
  689: { "stswa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", F_ALIAS, v9 },
  690: { "stswa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
  691: { "stswa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, v9 },
  692: { "stswa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, v9 },
  693: { "stswa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
  694: { "stswa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
  695: { "stuwa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", F_ALIAS, v9 },
  696: { "stuwa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
  697: { "stuwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, v9 },
  698: { "stuwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, v9 },
  699: { "stuwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
  700: { "stuwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
  701: 
  702: { "stb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", 0, v6 },
  703: { "stb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
  704: { "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", 0, v6 },
  705: { "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", 0, v6 },
  706: { "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", 0, v6 },
  707: { "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", 0, v6 }, /* stb d,[rs1+0] */
  708: 
  709: { "stsb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, v6 },
  710: { "stsb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
  711: { "stsb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", F_ALIAS, v6 },
  712: { "stsb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", F_ALIAS, v6 },
  713: { "stsb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
  714: { "stsb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
  715: { "stub",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, v6 },
  716: { "stub",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
  717: { "stub",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", F_ALIAS, v6 },
  718: { "stub",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", F_ALIAS, v6 },
  719: { "stub",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
  720: { "stub",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
  721: 
  722: { "stba",       F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", 0, v6 },
  723: { "stba",       F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
  724: { "stba",       F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", 0, v9 },
  725: { "stba",       F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", 0, v9 },
  726: { "stba",       F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
  727: { "stba",       F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */
  728: 
  729: { "stsba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", F_ALIAS, v6 },
  730: { "stsba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
  731: { "stsba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", F_ALIAS, v9 },
  732: { "stsba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", F_ALIAS, v9 },
  733: { "stsba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
  734: { "stsba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
  735: { "stuba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", F_ALIAS, v6 },
  736: { "stuba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
  737: { "stuba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", F_ALIAS, v9 },
  738: { "stuba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", F_ALIAS, v9 },
  739: { "stuba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
  740: { "stuba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
  741: 
  742: { "std",        F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", 0, v6 },
  743: { "std",        F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
  744: { "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", 0, v6 },
  745: { "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", 0, v6 },
  746: { "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", 0, v6 },
  747: { "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", 0, v6 }, /* std d,[rs1+0] */
  748: 
  749: { "std",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),      "q,[1+2]", 0, v6notv9 },
  750: { "std",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
  751: { "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[1+i]", 0, v6notv9 },
  752: { "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[i+1]", 0, v6notv9 },
  753: { "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "q,[i]", 0, v6notv9 },
  754: { "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),   "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
  755: { "std",        F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0),      "H,[1+2]", 0, v6 },
  756: { "std",        F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0),  "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */
  757: { "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[1+i]", 0, v6 },
  758: { "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[i+1]", 0, v6 },
  759: { "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0,       "H,[i]", 0, v6 },
  760: { "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0),   "H,[1]", 0, v6 }, /* std d,[rs1+0] */
  761: 
  762: { "std",        F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),      "Q,[1+2]", 0, v6notv9 },
  763: { "std",        F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
  764: { "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[1+i]", 0, v6notv9 },
  765: { "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[i+1]", 0, v6notv9 },
  766: { "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "Q,[i]", 0, v6notv9 },
  767: { "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),   "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
  768: { "std",        F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0),      "D,[1+2]", 0, v6notv9 },
  769: { "std",        F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0),  "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
  770: { "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[1+i]", 0, v6notv9 },
  771: { "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[i+1]", 0, v6notv9 },
  772: { "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,       "D,[i]", 0, v6notv9 },
  773: { "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),   "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
  774: 
  775: { "spilld",     F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, v6 },
  776: { "spilld",     F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
  777: { "spilld",     F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", F_ALIAS, v6 },
  778: { "spilld",     F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", F_ALIAS, v6 },
  779: { "spilld",     F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
  780: { "spilld",     F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
  781: 
  782: { "stda",       F3(3, 0x17, 0), F3(~3, ~0x17, ~0),              "d,[1+2]A", 0, v6 },
  783: { "stda",       F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
  784: { "stda",       F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[1+i]o", 0, v9 },
  785: { "stda",       F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[i+1]o", 0, v9 },
  786: { "stda",       F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
  787: { "stda",       F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),   "d,[1]o", 0, v9 }, /* std d,[rs1+0] */
  788: { "stda",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0),              "H,[1+2]A", 0, v9 },
  789: { "stda",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0),      "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */
  790: { "stda",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "H,[1+i]o", 0, v9 },
  791: { "stda",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "H,[i+1]o", 0, v9 },
  792: { "stda",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,       "H,[i]o", 0, v9 },
  793: { "stda",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),   "H,[1]o", 0, v9 }, /* std d,[rs1+0] */
  794: 
  795: { "sth",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", 0, v6 },
  796: { "sth",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
  797: { "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", 0, v6 },
  798: { "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", 0, v6 },
  799: { "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", 0, v6 },
  800: { "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", 0, v6 }, /* sth d,[rs1+0] */
  801: 
  802: { "stsh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, v6 },
  803: { "stsh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
  804: { "stsh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", F_ALIAS, v6 },
  805: { "stsh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", F_ALIAS, v6 },
  806: { "stsh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
  807: { "stsh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
  808: { "stuh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, v6 },
  809: { "stuh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
  810: { "stuh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", F_ALIAS, v6 },
  811: { "stuh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", F_ALIAS, v6 },
  812: { "stuh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
  813: { "stuh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
  814: 
  815: { "stha",       F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", 0, v6 },
  816: { "stha",       F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */
  817: { "stha",       F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", 0, v9 },
  818: { "stha",       F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", 0, v9 },
  819: { "stha",       F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
  820: { "stha",       F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */
  821: 
  822: { "stsha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", F_ALIAS, v6 },
  823: { "stsha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
  824: { "stsha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", F_ALIAS, v9 },
  825: { "stsha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", F_ALIAS, v9 },
  826: { "stsha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
  827: { "stsha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
  828: { "stuha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", F_ALIAS, v6 },
  829: { "stuha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
  830: { "stuha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", F_ALIAS, v9 },
  831: { "stuha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", F_ALIAS, v9 },
  832: { "stuha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
  833: { "stuha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
  834: 
  835: { "stx",        F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0),      "d,[1+2]", 0, v9 },
  836: { "stx",        F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0),  "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
  837: { "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),              "d,[1+i]", 0, v9 },
  838: { "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),              "d,[i+1]", 0, v9 },
  839: { "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0,       "d,[i]", 0, v9 },
  840: { "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0),   "d,[1]", 0, v9 }, /* stx d,[rs1+0] */
  841: 
  842: { "stx",        F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 },
  843: { "stx",        F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
  844: { "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[1+i]", 0, v9 },
  845: { "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[i+1]", 0, v9 },
  846: { "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1),  "F,[i]", 0, v9 },
  847: { "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
  848: 
  849: { "stxa",       F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0),              "d,[1+2]A", 0, v9 },
  850: { "stxa",       F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0),      "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */
  851: { "stxa",       F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[1+i]o", 0, v9 },
  852: { "stxa",       F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[i+1]o", 0, v9 },
  853: { "stxa",       F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
  854: { "stxa",       F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0),   "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */
  855: 
  856: { "stq",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),      "J,[1+2]", 0, v9 },
  857: { "stq",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "J,[1]", 0, v9 }, /* stq [rs1+%g0] */
  858: { "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[1+i]", 0, v9 },
  859: { "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[i+1]", 0, v9 },
  860: { "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "J,[i]", 0, v9 },
  861: { "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),   "J,[1]", 0, v9 }, /* stq [rs1+0] */
  862: 
  863: { "stqa",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),      "J,[1+2]A", 0, v9 },
  864: { "stqa",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */
  865: { "stqa",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[1+i]o", 0, v9 },
  866: { "stqa",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[i+1]o", 0, v9 },
  867: { "stqa",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "J,[i]o", 0, v9 },
  868: { "stqa",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),   "J,[1]o", 0, v9 }, /* stqa [rs1+0] */
  869: 
  870: { "swap",       F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0),      "[1+2],d", 0, v7 },
  871: { "swap",       F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),  "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
  872: { "swap",       F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[1+i],d", 0, v7 },
  873: { "swap",       F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[i+1],d", 0, v7 },
  874: { "swap",       F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0,       "[i],d", 0, v7 },
  875: { "swap",       F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0),   "[1],d", 0, v7 }, /* swap [rs1+0],d */
  876: 
  877: { "swapa",      F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0),              "[1+2]A,d", 0, v7 },
  878: { "swapa",      F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0),      "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
  879: { "swapa",      F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),              "[1+i]o,d", 0, v9 },
  880: { "swapa",      F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),              "[i+1]o,d", 0, v9 },
  881: { "swapa",      F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
  882: { "swapa",      F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0),   "[1]o,d", 0, v9 }, /* swap [rs1+0],d */
  883: 
  884: { "restore",    F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),                      "1,2,d", 0, v6 },
  885: { "restore",    F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "", 0, v6 }, /* restore %g0,%g0,%g0 */
  886: { "restore",    F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),                              "1,i,d", 0, v6 },
  887: { "restore",    F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),      "", 0, v6 }, /* restore %g0,0,%g0 */
  888: 
  889: { "rett",       F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
  890: { "rett",       F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, v6 },    /* rett rs1,%g0 */
  891: { "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
  892: { "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
  893: { "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
  894: { "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, v6 },    /* rett X */
  895: { "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, v6 },    /* rett rs1+0 */
  896: 
  897: { "save",       F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),      "1,2,d", 0, v6 },
  898: { "save",       F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),              "1,i,d", 0, v6 },
  899: { "save",       0x81e00000,     ~0x81e00000,                    "", F_ALIAS, v6 },
  900: 
  901: { "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),            "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
  902: { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
  903: 
  904: { "jmpl",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0),      "1+2,d", F_JSR|F_DELAYED, v6 },
  905: { "jmpl",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0),  "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
  906: { "jmpl",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0),   "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
  907: { "jmpl",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0,       "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
  908: { "jmpl",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "1+i,d", F_JSR|F_DELAYED, v6 },
  909: { "jmpl",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "i+1,d", F_JSR|F_DELAYED, v6 },
  910: 
  911: { "done",       F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0),       "", 0, v9 },
  912: { "retry",      F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0),       "", 0, v9 },
  913: { "saved",      F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0),       "", 0, v9 },
  914: { "restored",   F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0),       "", 0, v9 },
  915: { "allclean",   F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0),       "", 0, v9 },
  916: { "otherw",     F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0),       "", 0, v9 },
  917: { "normalw",    F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0),       "", 0, v9 },
  918: { "invalw",     F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0),       "", 0, v9 },
  919: { "sir",        F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0,              "i", 0, v9 },
  920: 
  921: { "flush",      F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", 0, v8 },
  922: { "flush",      F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", 0, v8 }, /* flush rs1+%g0 */
  923: { "flush",      F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", 0, v8 }, /* flush rs1+0 */
  924: { "flush",      F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", 0, v8 }, /* flush %g0+i */
  925: { "flush",      F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", 0, v8 },
  926: { "flush",      F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", 0, v8 },
  927: 
  928: /* IFLUSH was renamed to FLUSH in v8.  */
  929: { "iflush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", F_ALIAS, v6 },
  930: { "iflush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", F_ALIAS, v6 }, /* flush rs1+%g0 */
  931: { "iflush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", F_ALIAS, v6 }, /* flush rs1+0 */
  932: { "iflush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", F_ALIAS, v6 },
  933: { "iflush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", F_ALIAS, v6 },
  934: { "iflush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", F_ALIAS, v6 },
  935: 
  936: { "return",     F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0),      "1+2", 0, v9 },
  937: { "return",     F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0),  "1", 0, v9 }, /* return rs1+%g0 */
  938: { "return",     F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0),   "1", 0, v9 }, /* return rs1+0 */
  939: { "return",     F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0,       "i", 0, v9 }, /* return %g0+i */
  940: { "return",     F3(2, 0x39, 1), F3(~2, ~0x39, ~1),              "1+i", 0, v9 },
  941: { "return",     F3(2, 0x39, 1), F3(~2, ~0x39, ~1),              "i+1", 0, v9 },
  942: 
  943: { "flushw",     F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "", 0, v9 },
  944: 
  945: { "membar",     F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
  946: { "stbar",      F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
  947: 
  948: { "prefetch",   F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0),              "[1+2],*", 0, v9 },
  949: { "prefetch",   F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0,       "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
  950: { "prefetch",   F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),              "[1+i],*", 0, v9 },
  951: { "prefetch",   F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),              "[i+1],*", 0, v9 },
  952: { "prefetch",   F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0,       "[i],*", 0, v9 },
  953: { "prefetch",   F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0),   "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
  954: { "prefetcha",  F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0),              "[1+2]A,*", 0, v9 },
  955: { "prefetcha",  F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0,       "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
  956: { "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),              "[1+i]o,*", 0, v9 },
  957: { "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),              "[i+1]o,*", 0, v9 },
  958: { "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0,       "[i]o,*", 0, v9 },
  959: { "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0),   "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */
  960: 
  961: { "sll",        F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5),    "1,2,d", 0, v6 },
  962: { "sll",        F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, v6 },
  963: { "sra",        F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5),    "1,2,d", 0, v6 },
  964: { "sra",        F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, v6 },
  965: { "srl",        F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5),    "1,2,d", 0, v6 },
  966: { "srl",        F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, v6 },
  967: 
  968: { "sllx",       F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5),    "1,2,d", 0, v9 },
  969: { "sllx",       F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6),    "1,Y,d", 0, v9 },
  970: { "srax",       F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5),    "1,2,d", 0, v9 },
  971: { "srax",       F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6),    "1,Y,d", 0, v9 },
  972: { "srlx",       F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5),    "1,2,d", 0, v9 },
  973: { "srlx",       F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6),    "1,Y,d", 0, v9 },
  974: 
  975: { "mulscc",     F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0),      "1,2,d", 0, v6 },
  976: { "mulscc",     F3(2, 0x24, 1), F3(~2, ~0x24, ~1),              "1,i,d", 0, v6 },
  977: 
  978: { "divscc",     F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0),      "1,2,d", 0, sparclite },
  979: { "divscc",     F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1),              "1,i,d", 0, sparclite },
  980: 
  981: { "scan",       F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0),      "1,2,d", 0, sparclet|sparclite },
  982: { "scan",       F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1),              "1,i,d", 0, sparclet|sparclite },
  983: 
  984: { "popc",       F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
  985: { "popc",       F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0,       "i,d", 0, v9 },
  986: 
  987: { "clr",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
  988: { "clr",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),            "d", F_ALIAS, v6 }, /* or %g0,0,d       */
  989: { "clr",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),                "[1+2]", F_ALIAS, v6 },
  990: { "clr",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),            "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
  991: { "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[1+i]", F_ALIAS, v6 },
  992: { "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[i+1]", F_ALIAS, v6 },
  993: { "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,                 "[i]", F_ALIAS, v6 },
  994: { "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),             "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
  995: 
  996: { "clrb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v6 },
  997: { "clrb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
  998: { "clrb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
  999: { "clrb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
 1000: { "clrb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v6 },
 1001: { "clrb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
 1002: 
 1003: { "clrh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v6 },
 1004: { "clrh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
 1005: { "clrh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
 1006: { "clrh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
 1007: { "clrh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v6 },
 1008: { "clrh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
 1009: 
 1010: { "clrx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v9 },
 1011: { "clrx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
 1012: { "clrx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[1+i]", F_ALIAS, v9 },
 1013: { "clrx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[i+1]", F_ALIAS, v9 },
 1014: { "clrx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v9 },
 1015: { "clrx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
 1016: 
 1017: { "orcc",       F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1018: { "orcc",       F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "1,i,d", 0, v6 },
 1019: { "orcc",       F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "i,1,d", 0, v6 },
 1020: 
 1021: /* This is not a commutative instruction.  */
 1022: { "orncc",      F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1023: { "orncc",      F3(2, 0x16, 1), F3(~2, ~0x16, ~1),              "1,i,d", 0, v6 },
 1024: 
 1025: /* This is not a commutative instruction.  */
 1026: { "orn",        F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1027: { "orn",        F3(2, 0x06, 1), F3(~2, ~0x06, ~1),              "1,i,d", 0, v6 },
 1028: 
 1029: { "tst",        F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0),    "1", 0, v6 }, /* orcc rs1, %g0, %g0 */
 1030: { "tst",        F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */
 1031: { "tst",        F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0),     "1", 0, v6 }, /* orcc rs1, 0, %g0 */
 1032: 
 1033: { "wr", F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI(~0),              "1,2,m", 0, v8 }, /* wr r,r,%asrX */
 1034: { "wr", F3(2, 0x30, 1),         F3(~2, ~0x30, ~1),                      "1,i,m", 0, v8 }, /* wr r,i,%asrX */
 1035: { "wr", F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI_RS2(~0),          "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
 1036: { "wr", F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", 0, v6 }, /* wr r,r,%y */
 1037: { "wr", F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", 0, v6 }, /* wr r,i,%y */
 1038: { "wr", F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),    "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
 1039: { "wr", F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
 1040: { "wr", F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
 1041: { "wr", F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),    "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
 1042: { "wr", F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
 1043: { "wr", F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
 1044: { "wr", F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),    "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
 1045: { "wr", F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
 1046: { "wr", F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
 1047: { "wr", F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),    "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
 1048: 
 1049: { "wr", F3(2, 0x30, 0)|RD(2),   F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0),       "1,2,E", 0, v9 }, /* wr r,r,%ccr */
 1050: { "wr", F3(2, 0x30, 1)|RD(2),   F3(~2, ~0x30, ~1)|RD(~2),               "1,i,E", 0, v9 }, /* wr r,i,%ccr */
 1051: { "wr", F3(2, 0x30, 0)|RD(3),   F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0),       "1,2,o", 0, v9 }, /* wr r,r,%asi */
 1052: { "wr", F3(2, 0x30, 1)|RD(3),   F3(~2, ~0x30, ~1)|RD(~3),               "1,i,o", 0, v9 }, /* wr r,i,%asi */
 1053: { "wr", F3(2, 0x30, 0)|RD(6),   F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0),       "1,2,s", 0, v9 }, /* wr r,r,%fprs */
 1054: { "wr", F3(2, 0x30, 1)|RD(6),   F3(~2, ~0x30, ~1)|RD(~6),               "1,i,s", 0, v9 }, /* wr r,i,%fprs */
 1055: 
 1056: { "wr", F3(2, 0x30, 0)|RD(16),  F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0),      "1,2,_", 0, v9a }, /* wr r,r,%pcr */
 1057: { "wr", F3(2, 0x30, 1)|RD(16),  F3(~2, ~0x30, ~1)|RD(~16),              "1,i,_", 0, v9a }, /* wr r,i,%pcr */
 1058: { "wr", F3(2, 0x30, 0)|RD(17),  F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0),      "1,2,_", 0, v9a }, /* wr r,r,%pic */
 1059: { "wr", F3(2, 0x30, 1)|RD(17),  F3(~2, ~0x30, ~1)|RD(~17),              "1,i,_", 0, v9a }, /* wr r,i,%pic */
 1060: { "wr", F3(2, 0x30, 0)|RD(18),  F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0),      "1,2,_", 0, v9a }, /* wr r,r,%dcr */
 1061: { "wr", F3(2, 0x30, 1)|RD(18),  F3(~2, ~0x30, ~1)|RD(~18),              "1,i,_", 0, v9a }, /* wr r,i,%dcr */
 1062: { "wr", F3(2, 0x30, 0)|RD(19),  F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0),      "1,2,_", 0, v9a }, /* wr r,r,%gsr */
 1063: { "wr", F3(2, 0x30, 1)|RD(19),  F3(~2, ~0x30, ~1)|RD(~19),              "1,i,_", 0, v9a }, /* wr r,i,%gsr */
 1064: { "wr", F3(2, 0x30, 0)|RD(20),  F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0),      "1,2,_", 0, v9a }, /* wr r,r,%set_softint */
 1065: { "wr", F3(2, 0x30, 1)|RD(20),  F3(~2, ~0x30, ~1)|RD(~20),              "1,i,_", 0, v9a }, /* wr r,i,%set_softint */
 1066: { "wr", F3(2, 0x30, 0)|RD(21),  F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0),      "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */
 1067: { "wr", F3(2, 0x30, 1)|RD(21),  F3(~2, ~0x30, ~1)|RD(~21),              "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */
 1068: { "wr", F3(2, 0x30, 0)|RD(22),  F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0),      "1,2,_", 0, v9a }, /* wr r,r,%softint */
 1069: { "wr", F3(2, 0x30, 1)|RD(22),  F3(~2, ~0x30, ~1)|RD(~22),              "1,i,_", 0, v9a }, /* wr r,i,%softint */
 1070: { "wr", F3(2, 0x30, 0)|RD(23),  F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0),      "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
 1071: { "wr", F3(2, 0x30, 1)|RD(23),  F3(~2, ~0x30, ~1)|RD(~23),              "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
 1072: { "wr", F3(2, 0x30, 0)|RD(24),  F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0),      "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
 1073: { "wr", F3(2, 0x30, 1)|RD(24),  F3(~2, ~0x30, ~1)|RD(~24),              "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
 1074: { "wr", F3(2, 0x30, 0)|RD(25),  F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0),      "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
 1075: { "wr", F3(2, 0x30, 1)|RD(25),  F3(~2, ~0x30, ~1)|RD(~25),              "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
 1076: 
 1077: { "rd", F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|SIMM13(~0),           "M,d", 0, v8 }, /* rd %asrX,r */
 1078: { "rd", F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),    "y,d", 0, v6 }, /* rd %y,r */
 1079: { "rd", F3(2, 0x29, 0),                 F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),    "p,d", 0, v6notv9 }, /* rd %psr,r */
 1080: { "rd", F3(2, 0x2a, 0),                 F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),    "w,d", 0, v6notv9 }, /* rd %wim,r */
 1081: { "rd", F3(2, 0x2b, 0),                 F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),    "t,d", 0, v6notv9 }, /* rd %tbr,r */
 1082: 
 1083: { "rd", F3(2, 0x28, 0)|RS1(2),          F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0),   "E,d", 0, v9 }, /* rd %ccr,r */
 1084: { "rd", F3(2, 0x28, 0)|RS1(3),          F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0),   "o,d", 0, v9 }, /* rd %asi,r */
 1085: { "rd", F3(2, 0x28, 0)|RS1(4),          F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0),   "W,d", 0, v9 }, /* rd %tick,r */
 1086: { "rd", F3(2, 0x28, 0)|RS1(5),          F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0),   "P,d", 0, v9 }, /* rd %pc,r */
 1087: { "rd", F3(2, 0x28, 0)|RS1(6),          F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0),   "s,d", 0, v9 }, /* rd %fprs,r */
 1088: 
 1089: { "rd", F3(2, 0x28, 0)|RS1(16),         F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0),  "/,d", 0, v9a }, /* rd %pcr,r */
 1090: { "rd", F3(2, 0x28, 0)|RS1(17),         F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0),  "/,d", 0, v9a }, /* rd %pic,r */
 1091: { "rd", F3(2, 0x28, 0)|RS1(18),         F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0),  "/,d", 0, v9a }, /* rd %dcr,r */
 1092: { "rd", F3(2, 0x28, 0)|RS1(19),         F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0),  "/,d", 0, v9a }, /* rd %gsr,r */
 1093: { "rd", F3(2, 0x28, 0)|RS1(22),         F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0),  "/,d", 0, v9a }, /* rd %softint,r */
 1094: { "rd", F3(2, 0x28, 0)|RS1(23),         F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0),  "/,d", 0, v9a }, /* rd %tick_cmpr,r */
 1095: { "rd", F3(2, 0x28, 0)|RS1(24),         F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),  "/,d", 0, v9b }, /* rd %sys_tick,r */
 1096: { "rd", F3(2, 0x28, 0)|RS1(25),         F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),  "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
 1097: 
 1098: { "rdpr",       F3(2, 0x2a, 0),         F3(~2, ~0x2a, ~0)|SIMM13(~0),   "?,d", 0, v9 },   /* rdpr %priv,r */
 1099: { "wrpr",       F3(2, 0x32, 0),         F3(~2, ~0x32, ~0),              "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
 1100: { "wrpr",       F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|SIMM13(~0),   "1,!", 0, v9 },   /* wrpr r1,%priv */
 1101: { "wrpr",       F3(2, 0x32, 1),         F3(~2, ~0x32, ~1),              "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */
 1102: { "wrpr",       F3(2, 0x32, 1),         F3(~2, ~0x32, ~1),              "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
 1103: { "wrpr",       F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RS1(~0),      "i,!", 0, v9 },   /* wrpr i,%priv */
 1104: 
 1105: { "rdhpr",      F3(2, 0x29, 0),         F3(~2, ~0x29, ~0)|SIMM13(~0),   "$,d", 0, v9 },   /* rdhpr %hpriv,r */
 1106: { "wrhpr",      F3(2, 0x33, 0),         F3(~2, ~0x33, ~0),              "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */
 1107: { "wrhpr",      F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|SIMM13(~0),   "1,%", 0, v9 },   /* wrhpr r1,%hpriv */
 1108: { "wrhpr",      F3(2, 0x33, 1),         F3(~2, ~0x33, ~1),              "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */
 1109: { "wrhpr",      F3(2, 0x33, 1),         F3(~2, ~0x33, ~1),              "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */
 1110: { "wrhpr",      F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RS1(~0),      "i,%", 0, v9 },   /* wrhpr i,%hpriv */
 1111: 
 1112: /* ??? This group seems wrong.  A three operand move?  */
 1113: { "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0),              "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
 1114: { "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1),                      "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
 1115: { "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
 1116: { "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
 1117: { "mov",        F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
 1118: { "mov",        F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
 1119: { "mov",        F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
 1120: { "mov",        F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
 1121: { "mov",        F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
 1122: { "mov",        F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
 1123: 
 1124: { "mov",        F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0),           "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
 1125: { "mov",        F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),    "y,d", F_ALIAS, v6 }, /* rd %y,r */
 1126: { "mov",        F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),    "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
 1127: { "mov",        F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),    "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
 1128: { "mov",        F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),    "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
 1129: 
 1130: { "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0),          "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
 1131: { "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1),                      "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
 1132: { "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0),           "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */
 1133: { "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),    "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
 1134: { "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,                "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
 1135: { "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0),     "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
 1136: { "mov",        F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),    "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
 1137: { "mov",        F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,                "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
 1138: { "mov",        F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0),     "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */
 1139: { "mov",        F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),    "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
 1140: { "mov",        F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,                "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
 1141: { "mov",        F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0),     "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */
 1142: { "mov",        F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),    "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
 1143: { "mov",        F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,                "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
 1144: { "mov",        F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0),     "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */
 1145: 
 1146: { "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),       "2,d", 0, v6 }, /* or %g0,rs2,d */
 1147: { "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,               "i,d", 0, v6 }, /* or %g0,i,d   */
 1148: { "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0),          "1,d", 0, v6 }, /* or rs1,%g0,d   */
 1149: { "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0),           "1,d", 0, v6 }, /* or rs1,0,d */
 1150: 
 1151: { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1152: { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "1,i,d", 0, v6 },
 1153: { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,1,d", 0, v6 },
 1154: 
 1155: { "bset",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),      "2,r", F_ALIAS, v6 },   /* or rd,rs2,rd */
 1156: { "bset",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,r", F_ALIAS, v6 },   /* or rd,i,rd */
 1157: 
 1158: /* This is not a commutative instruction.  */
 1159: { "andn",       F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1160: { "andn",       F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "1,i,d", 0, v6 },
 1161: 
 1162: /* This is not a commutative instruction.  */
 1163: { "andncc",     F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1164: { "andncc",     F3(2, 0x15, 1), F3(~2, ~0x15, ~1),              "1,i,d", 0, v6 },
 1165: 
 1166: { "bclr",       F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),      "2,r", F_ALIAS, v6 },   /* andn rd,rs2,rd */
 1167: { "bclr",       F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "i,r", F_ALIAS, v6 },   /* andn rd,i,rd */
 1168: 
 1169: { "cmp",        F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0),        "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */
 1170: { "cmp",        F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0,                "1,i", 0, v6 }, /* subcc rs1,i,%g0 */
 1171: 
 1172: { "sub",        F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1173: { "sub",        F3(2, 0x04, 1), F3(~2, ~0x04, ~1),              "1,i,d", 0, v6 },
 1174: 
 1175: { "subcc",      F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1176: { "subcc",      F3(2, 0x14, 1), F3(~2, ~0x14, ~1),              "1,i,d", 0, v6 },
 1177: 
 1178: { "subx",       F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),      "1,2,d", 0, v6notv9 },
 1179: { "subx",       F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),              "1,i,d", 0, v6notv9 },
 1180: { "subc",       F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),      "1,2,d", 0, v9 },
 1181: { "subc",       F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),              "1,i,d", 0, v9 },
 1182: 
 1183: { "subxcc",     F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),      "1,2,d", 0, v6notv9 },
 1184: { "subxcc",     F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),              "1,i,d", 0, v6notv9 },
 1185: { "subccc",     F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),      "1,2,d", 0, v9 },
 1186: { "subccc",     F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),              "1,i,d", 0, v9 },
 1187: 
 1188: { "and",        F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1189: { "and",        F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "1,i,d", 0, v6 },
 1190: { "and",        F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "i,1,d", 0, v6 },
 1191: 
 1192: { "andcc",      F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1193: { "andcc",      F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "1,i,d", 0, v6 },
 1194: { "andcc",      F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "i,1,d", 0, v6 },
 1195: 
 1196: { "dec",        F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* sub rd,1,rd */
 1197: { "dec",        F3(2, 0x04, 1),             F3(~2, ~0x04, ~1),                 "i,r", F_ALIAS, v8 },    /* sub rd,imm,rd */
 1198: { "deccc",      F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* subcc rd,1,rd */
 1199: { "deccc",      F3(2, 0x14, 1),             F3(~2, ~0x14, ~1),                 "i,r", F_ALIAS, v8 },    /* subcc rd,imm,rd */
 1200: { "inc",        F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* add rd,1,rd */
 1201: { "inc",        F3(2, 0x00, 1),             F3(~2, ~0x00, ~1),                 "i,r", F_ALIAS, v8 },    /* add rd,imm,rd */
 1202: { "inccc",      F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* addcc rd,1,rd */
 1203: { "inccc",      F3(2, 0x10, 1),             F3(~2, ~0x10, ~1),                 "i,r", F_ALIAS, v8 },    /* addcc rd,imm,rd */
 1204: 
 1205: { "btst",       F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 },  /* andcc rs1,rs2,%g0 */
 1206: { "btst",       F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 },  /* andcc rs1,i,%g0 */
 1207: 
 1208: { "neg",        F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
 1209: { "neg",        F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */
 1210: 
 1211: { "add",        F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1212: { "add",        F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "1,i,d", 0, v6 },
 1213: { "add",        F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "i,1,d", 0, v6 },
 1214: { "addcc",      F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1215: { "addcc",      F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "1,i,d", 0, v6 },
 1216: { "addcc",      F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "i,1,d", 0, v6 },
 1217: 
 1218: { "addx",       F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),      "1,2,d", 0, v6notv9 },
 1219: { "addx",       F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "1,i,d", 0, v6notv9 },
 1220: { "addx",       F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "i,1,d", 0, v6notv9 },
 1221: { "addc",       F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),      "1,2,d", 0, v9 },
 1222: { "addc",       F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "1,i,d", 0, v9 },
 1223: { "addc",       F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "i,1,d", 0, v9 },
 1224: 
 1225: { "addxcc",     F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),      "1,2,d", 0, v6notv9 },
 1226: { "addxcc",     F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "1,i,d", 0, v6notv9 },
 1227: { "addxcc",     F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "i,1,d", 0, v6notv9 },
 1228: { "addccc",     F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),      "1,2,d", 0, v9 },
 1229: { "addccc",     F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "1,i,d", 0, v9 },
 1230: { "addccc",     F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "i,1,d", 0, v9 },
 1231: 
 1232: { "smul",       F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0),      "1,2,d", 0, v8 },
 1233: { "smul",       F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "1,i,d", 0, v8 },
 1234: { "smul",       F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "i,1,d", 0, v8 },
 1235: { "smulcc",     F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0),      "1,2,d", 0, v8 },
 1236: { "smulcc",     F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "1,i,d", 0, v8 },
 1237: { "smulcc",     F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "i,1,d", 0, v8 },
 1238: { "umul",       F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0),      "1,2,d", 0, v8 },
 1239: { "umul",       F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "1,i,d", 0, v8 },
 1240: { "umul",       F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "i,1,d", 0, v8 },
 1241: { "umulcc",     F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0),      "1,2,d", 0, v8 },
 1242: { "umulcc",     F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "1,i,d", 0, v8 },
 1243: { "umulcc",     F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "i,1,d", 0, v8 },
 1244: { "sdiv",       F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0),      "1,2,d", 0, v8 },
 1245: { "sdiv",       F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "1,i,d", 0, v8 },
 1246: { "sdiv",       F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "i,1,d", 0, v8 },
 1247: { "sdivcc",     F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0),      "1,2,d", 0, v8 },
 1248: { "sdivcc",     F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "1,i,d", 0, v8 },
 1249: { "sdivcc",     F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "i,1,d", 0, v8 },
 1250: { "udiv",       F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0),      "1,2,d", 0, v8 },
 1251: { "udiv",       F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "1,i,d", 0, v8 },
 1252: { "udiv",       F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "i,1,d", 0, v8 },
 1253: { "udivcc",     F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0),      "1,2,d", 0, v8 },
 1254: { "udivcc",     F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "1,i,d", 0, v8 },
 1255: { "udivcc",     F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "i,1,d", 0, v8 },
 1256: 
 1257: { "mulx",       F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0),      "1,2,d", 0, v9 },
 1258: { "mulx",       F3(2, 0x09, 1), F3(~2, ~0x09, ~1),              "1,i,d", 0, v9 },
 1259: { "sdivx",      F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),      "1,2,d", 0, v9 },
 1260: { "sdivx",      F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),              "1,i,d", 0, v9 },
 1261: { "udivx",      F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0),      "1,2,d", 0, v9 },
 1262: { "udivx",      F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1),              "1,i,d", 0, v9 },
 1263: 
 1264: { "call",       F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
 1265: { "call",       F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
 1266: 
 1267: { "call",       F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),     "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
 1268: { "call",       F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),     "1+2,#", F_JSR|F_DELAYED, v6 },
 1269: { "call",       F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
 1270: { "call",       F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 },
 1271: { "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
 1272: { "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i,#", F_JSR|F_DELAYED, v6 },
 1273: { "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
 1274: { "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1,#", F_JSR|F_DELAYED, v6 },
 1275: { "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
 1276: { "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i,#", F_JSR|F_DELAYED, v6 },
 1277: { "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),  "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
 1278: { "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),  "1,#", F_JSR|F_DELAYED, v6 },
 1279: 
 1280: 
 1281: /* Conditional instructions.
 1282: 
 1283:    Because this part of the table was such a mess earlier, I have
 1284:    macrofied it so that all the branches and traps are generated from
 1285:    a single-line description of each condition value.  John Gilmore. */
 1286: 
 1287: /* Define branches -- one annulled, one without, etc. */
 1288: #define br(opcode, mask, lose, flags) \
 1289:  { opcode, (mask)|ANNUL, (lose),       ",a l",   (flags), v6 }, \
 1290:  { opcode, (mask)      , (lose)|ANNUL, "l",     (flags), v6 }
 1291: 
 1292: #define brx(opcode, mask, lose, flags) /* v9 */ \
 1293:  { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G",      (flags), v9 }, \
 1294:  { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G",   (flags), v9 }, \
 1295:  { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G",   (flags), v9 }, \
 1296:  { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
 1297:  { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G",   (flags), v9 }, \
 1298:  { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
 1299:  { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G",      (flags), v9 }, \
 1300:  { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G",   (flags), v9 }, \
 1301:  { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G",   (flags), v9 }, \
 1302:  { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
 1303:  { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G",   (flags), v9 }, \
 1304:  { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
 1305: 
 1306: /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
 1307: #define tr(opcode, mask, lose, flags) \
 1308:  { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i",   (flags), v9 }, /* %g0 + imm */ \
 1309:  { opcode, (mask)|(2<<11)|IMMED, (lose),        "Z,1+i", (flags), v9 }, /* rs1 + imm */ \
 1310:  { opcode, (mask)|(2<<11), IMMED|(lose),        "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \
 1311:  { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1",   (flags), v9 }, /* rs1 + %g0 */ \
 1312:  { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i",   (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \
 1313:  { opcode, (mask)|IMMED, (lose),        "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \
 1314:  { opcode, (mask), IMMED|(lose),        "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \
 1315:  { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1",   (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
 1316:  { opcode, (mask)|IMMED, (lose)|RS1_G0,         "i",     (flags), v6 }, /* %g0 + imm */ \
 1317:  { opcode, (mask)|IMMED, (lose),                "1+i",   (flags), v6 }, /* rs1 + imm */ \
 1318:  { opcode, (mask), IMMED|(lose),                "1+2",   (flags), v6 }, /* rs1 + rs2 */ \
 1319:  { opcode, (mask), IMMED|(lose)|RS2_G0,         "1",     (flags), v6 } /* rs1 + %g0 */
 1320: 
 1321: /* v9: We must put `brx' before `br', to ensure that we never match something
 1322:    v9: against an expression unless it is an expression.  Otherwise, we end
 1323:    v9: up with undefined symbol tables entries, because they get added, but
 1324:    v9: are not deleted if the pattern fails to match.  */
 1325: 
 1326: /* Define both branches and traps based on condition mask */
 1327: #define cond(bop, top, mask, flags) \
 1328:   brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
 1329:   br(bop,  F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
 1330:   tr(top,  F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
 1331: 
 1332: /* Define all the conditions, all the branches, all the traps.  */
 1333: 
 1334: /* Standard branch, trap mnemonics */
 1335: cond ("b",      "ta",   CONDA, F_UNBR),
 1336: /* Alternative form (just for assembly, not for disassembly) */
 1337: cond ("ba",     "t",    CONDA, F_UNBR|F_ALIAS),
 1338: 
 1339: cond ("bcc",    "tcc",  CONDCC, F_CONDBR),
 1340: cond ("bcs",    "tcs",  CONDCS, F_CONDBR),
 1341: cond ("be",     "te",   CONDE, F_CONDBR),
 1342: cond ("beq",    "teq",  CONDE, F_CONDBR|F_ALIAS),
 1343: cond ("bg",     "tg",   CONDG, F_CONDBR),
 1344: cond ("bgt",    "tgt",  CONDG, F_CONDBR|F_ALIAS),
 1345: cond ("bge",    "tge",  CONDGE, F_CONDBR),
 1346: cond ("bgeu",   "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
 1347: cond ("bgu",    "tgu",  CONDGU, F_CONDBR),
 1348: cond ("bl",     "tl",   CONDL, F_CONDBR),
 1349: cond ("blt",    "tlt",  CONDL, F_CONDBR|F_ALIAS),
 1350: cond ("ble",    "tle",  CONDLE, F_CONDBR),
 1351: cond ("bleu",   "tleu", CONDLEU, F_CONDBR),
 1352: cond ("blu",    "tlu",  CONDLU, F_CONDBR|F_ALIAS), /* for cs */
 1353: cond ("bn",     "tn",   CONDN, F_CONDBR),
 1354: cond ("bne",    "tne",  CONDNE, F_CONDBR),
 1355: cond ("bneg",   "tneg", CONDNEG, F_CONDBR),
 1356: cond ("bnz",    "tnz",  CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
 1357: cond ("bpos",   "tpos", CONDPOS, F_CONDBR),
 1358: cond ("bvc",    "tvc",  CONDVC, F_CONDBR),
 1359: cond ("bvs",    "tvs",  CONDVS, F_CONDBR),
 1360: cond ("bz",     "tz",   CONDZ, F_CONDBR|F_ALIAS), /* for e */
 1361: 
 1362: #undef cond
 1363: #undef br
 1364: #undef brr /* v9 */
 1365: #undef tr
 1366: 
 1367: #define brr(opcode, mask, lose, flags) /* v9 */ \
 1368:  { opcode, (mask)|BPRED, ANNUL|(lose), "1,k",      F_DELAYED|(flags), v9 }, \
 1369:  { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k",   F_DELAYED|(flags), v9 }, \
 1370:  { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k",   F_DELAYED|(flags), v9 }, \
 1371:  { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
 1372:  { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k",   F_DELAYED|(flags), v9 }, \
 1373:  { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
 1374: 
 1375: #define condr(bop, mask, flags) /* v9 */ \
 1376:   brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
 1377: 
 1378: /* v9 */ condr("brnz", 0x5, F_CONDBR),
 1379: /* v9 */ condr("brz", 0x1, F_CONDBR),
 1380: /* v9 */ condr("brgez", 0x7, F_CONDBR),
 1381: /* v9 */ condr("brlz", 0x3, F_CONDBR),
 1382: /* v9 */ condr("brlez", 0x2, F_CONDBR),
 1383: /* v9 */ condr("brgz", 0x6, F_CONDBR),
 1384: 
 1385: #undef condr /* v9 */
 1386: #undef brr /* v9 */
 1387: 
 1388: #define movr(opcode, mask, flags) /* v9 */ \
 1389:  { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \
 1390:  { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 }
 1391: 
 1392: #define fmrrs(opcode, mask, lose, flags) /* v9 */ \
 1393:  { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
 1394: #define fmrrd(opcode, mask, lose, flags) /* v9 */ \
 1395:  { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
 1396: #define fmrrq(opcode, mask, lose, flags) /* v9 */ \
 1397:  { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
 1398: 
 1399: #define fmovrs(mop, mask, flags) /* v9 */ \
 1400:   fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
 1401: #define fmovrd(mop, mask, flags) /* v9 */ \
 1402:   fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
 1403: #define fmovrq(mop, mask, flags) /* v9 */ \
 1404:   fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
 1405: 
 1406: /* v9 */ movr("movrne", 0x5, 0),
 1407: /* v9 */ movr("movre", 0x1, 0),
 1408: /* v9 */ movr("movrgez", 0x7, 0),
 1409: /* v9 */ movr("movrlz", 0x3, 0),
 1410: /* v9 */ movr("movrlez", 0x2, 0),
 1411: /* v9 */ movr("movrgz", 0x6, 0),
 1412: /* v9 */ movr("movrnz", 0x5, F_ALIAS),
 1413: /* v9 */ movr("movrz", 0x1, F_ALIAS),
 1414: 
 1415: /* v9 */ fmovrs("fmovrsne", 0x5, 0),
 1416: /* v9 */ fmovrs("fmovrse", 0x1, 0),
 1417: /* v9 */ fmovrs("fmovrsgez", 0x7, 0),
 1418: /* v9 */ fmovrs("fmovrslz", 0x3, 0),
 1419: /* v9 */ fmovrs("fmovrslez", 0x2, 0),
 1420: /* v9 */ fmovrs("fmovrsgz", 0x6, 0),
 1421: /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
 1422: /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
 1423: 
 1424: /* v9 */ fmovrd("fmovrdne", 0x5, 0),
 1425: /* v9 */ fmovrd("fmovrde", 0x1, 0),
 1426: /* v9 */ fmovrd("fmovrdgez", 0x7, 0),
 1427: /* v9 */ fmovrd("fmovrdlz", 0x3, 0),
 1428: /* v9 */ fmovrd("fmovrdlez", 0x2, 0),
 1429: /* v9 */ fmovrd("fmovrdgz", 0x6, 0),
 1430: /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
 1431: /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
 1432: 
 1433: /* v9 */ fmovrq("fmovrqne", 0x5, 0),
 1434: /* v9 */ fmovrq("fmovrqe", 0x1, 0),
 1435: /* v9 */ fmovrq("fmovrqgez", 0x7, 0),
 1436: /* v9 */ fmovrq("fmovrqlz", 0x3, 0),
 1437: /* v9 */ fmovrq("fmovrqlez", 0x2, 0),
 1438: /* v9 */ fmovrq("fmovrqgz", 0x6, 0),
 1439: /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
 1440: /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
 1441: 
 1442: #undef movr /* v9 */
 1443: #undef fmovr /* v9 */
 1444: #undef fmrr /* v9 */
 1445: 
 1446: #define movicc(opcode, cond, flags) /* v9 */ \
 1447:   { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
 1448:   { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
 1449:   { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11),     "Z,2,d", flags, v9 }, \
 1450:   { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11),     "Z,I,d", flags, v9 }
 1451: 
 1452: #define movfcc(opcode, fcond, flags) /* v9 */ \
 1453:   { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
 1454:   { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
 1455:   { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
 1456:   { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
 1457:   { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
 1458:   { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
 1459:   { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
 1460:   { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
 1461: 
 1462: #define movcc(opcode, cond, fcond, flags) /* v9 */ \
 1463:   movfcc (opcode, fcond, flags), /* v9 */ \
 1464:   movicc (opcode, cond, flags) /* v9 */
 1465: 
 1466: /* v9 */ movcc  ("mova",        CONDA, FCONDA, 0),
 1467: /* v9 */ movicc ("movcc",       CONDCC, 0),
 1468: /* v9 */ movicc ("movgeu",      CONDGEU, F_ALIAS),
 1469: /* v9 */ movicc ("movcs",       CONDCS, 0),
 1470: /* v9 */ movicc ("movlu",       CONDLU, F_ALIAS),
 1471: /* v9 */ movcc  ("move",        CONDE, FCONDE, 0),
 1472: /* v9 */ movcc  ("movg",        CONDG, FCONDG, 0),
 1473: /* v9 */ movcc  ("movge",       CONDGE, FCONDGE, 0),
 1474: /* v9 */ movicc ("movgu",       CONDGU, 0),
 1475: /* v9 */ movcc  ("movl",        CONDL, FCONDL, 0),
 1476: /* v9 */ movcc  ("movle",       CONDLE, FCONDLE, 0),
 1477: /* v9 */ movicc ("movleu",      CONDLEU, 0),
 1478: /* v9 */ movfcc ("movlg",       FCONDLG, 0),
 1479: /* v9 */ movcc  ("movn",        CONDN, FCONDN, 0),
 1480: /* v9 */ movcc  ("movne",       CONDNE, FCONDNE, 0),
 1481: /* v9 */ movicc ("movneg",      CONDNEG, 0),
 1482: /* v9 */ movcc  ("movnz",       CONDNZ, FCONDNZ, F_ALIAS),
 1483: /* v9 */ movfcc ("movo",        FCONDO, 0),
 1484: /* v9 */ movicc ("movpos",      CONDPOS, 0),
 1485: /* v9 */ movfcc ("movu",        FCONDU, 0),
 1486: /* v9 */ movfcc ("movue",       FCONDUE, 0),
 1487: /* v9 */ movfcc ("movug",       FCONDUG, 0),
 1488: /* v9 */ movfcc ("movuge",      FCONDUGE, 0),
 1489: /* v9 */ movfcc ("movul",       FCONDUL, 0),
 1490: /* v9 */ movfcc ("movule",      FCONDULE, 0),
 1491: /* v9 */ movicc ("movvc",       CONDVC, 0),
 1492: /* v9 */ movicc ("movvs",       CONDVS, 0),
 1493: /* v9 */ movcc  ("movz",        CONDZ, FCONDZ, F_ALIAS),
 1494: 
 1495: #undef movicc /* v9 */
 1496: #undef movfcc /* v9 */
 1497: #undef movcc /* v9 */
 1498: 
 1499: #define FM_SF 1         /* v9 - values for fpsize */
 1500: #define FM_DF 2         /* v9 */
 1501: #define FM_QF 3         /* v9 */
 1502: 
 1503: #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
 1504: { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags, v9 }, \
 1505: { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags, v9 }
 1506: 
 1507: #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
 1508: { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \
 1509: { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \
 1510: { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \
 1511: { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 }
 1512: 
 1513: /* FIXME: use fmovicc/fmovfcc? */ /* v9 */
 1514: #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
 1515: { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags | F_FLOAT, v9 }, \
 1516: { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \
 1517: { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags | F_FLOAT, v9 }, \
 1518: { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \
 1519: { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \
 1520: { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 }
 1521: 
 1522: #define fmovicc(suffix, cond, flags) /* v9 */ \
 1523: fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags),            \
 1524: fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags),            \
 1525: fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
 1526: 
 1527: #define fmovfcc(suffix, fcond, flags) /* v9 */ \
 1528: fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags),           \
 1529: fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags),           \
 1530: fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
 1531: 
 1532: #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
 1533: fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags),      \
 1534: fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags),      \
 1535: fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
 1536: 
 1537: /* v9 */ fmovcc  ("a", CONDA, FCONDA, 0),
 1538: /* v9 */ fmovicc ("cc", CONDCC, 0),
 1539: /* v9 */ fmovicc ("cs", CONDCS, 0),
 1540: /* v9 */ fmovcc  ("e", CONDE, FCONDE, 0),
 1541: /* v9 */ fmovcc  ("g", CONDG, FCONDG, 0),
 1542: /* v9 */ fmovcc  ("ge", CONDGE, FCONDGE, 0),
 1543: /* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
 1544: /* v9 */ fmovicc ("gu", CONDGU, 0),
 1545: /* v9 */ fmovcc  ("l", CONDL, FCONDL, 0),
 1546: /* v9 */ fmovcc  ("le", CONDLE, FCONDLE, 0),
 1547: /* v9 */ fmovicc ("leu", CONDLEU, 0),
 1548: /* v9 */ fmovfcc ("lg", FCONDLG, 0),
 1549: /* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
 1550: /* v9 */ fmovcc  ("n", CONDN, FCONDN, 0),
 1551: /* v9 */ fmovcc  ("ne", CONDNE, FCONDNE, 0),
 1552: /* v9 */ fmovicc ("neg", CONDNEG, 0),
 1553: /* v9 */ fmovcc  ("nz", CONDNZ, FCONDNZ, F_ALIAS),
 1554: /* v9 */ fmovfcc ("o", FCONDO, 0),
 1555: /* v9 */ fmovicc ("pos", CONDPOS, 0),
 1556: /* v9 */ fmovfcc ("u", FCONDU, 0),
 1557: /* v9 */ fmovfcc ("ue", FCONDUE, 0),
 1558: /* v9 */ fmovfcc ("ug", FCONDUG, 0),
 1559: /* v9 */ fmovfcc ("uge", FCONDUGE, 0),
 1560: /* v9 */ fmovfcc ("ul", FCONDUL, 0),
 1561: /* v9 */ fmovfcc ("ule", FCONDULE, 0),
 1562: /* v9 */ fmovicc ("vc", CONDVC, 0),
 1563: /* v9 */ fmovicc ("vs", CONDVS, 0),
 1564: /* v9 */ fmovcc  ("z", CONDZ, FCONDZ, F_ALIAS),
 1565: 
 1566: #undef fmoviccx /* v9 */
 1567: #undef fmovfccx /* v9 */
 1568: #undef fmovccx /* v9 */
 1569: #undef fmovicc /* v9 */
 1570: #undef fmovfcc /* v9 */
 1571: #undef fmovcc /* v9 */
 1572: #undef FM_DF /* v9 */
 1573: #undef FM_QF /* v9 */
 1574: #undef FM_SF /* v9 */
 1575: 
 1576: /* Coprocessor branches.  */
 1577: #define CBR(opcode, mask, lose, flags, arch) \
 1578:  { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED, arch }, \
 1579:  { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch }
 1580: 
 1581: /* Floating point branches.  */
 1582: #define FBR(opcode, mask, lose, flags) \
 1583:  { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED | F_FBR, v6 }, \
 1584:  { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 }
 1585: 
 1586: /* V9 extended floating point branches.  */
 1587: #define FBRX(opcode, mask, lose, flags) /* v9 */ \
 1588:  { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G",      flags|F_DELAYED|F_FBR, v9 }, \
 1589:  { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1590:  { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1591:  { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
 1592:  { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1593:  { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
 1594:  { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G",      flags|F_DELAYED|F_FBR, v9 }, \
 1595:  { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1596:  { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1597:  { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
 1598:  { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1599:  { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
 1600:  { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G",      flags|F_DELAYED|F_FBR, v9 }, \
 1601:  { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1602:  { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1603:  { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
 1604:  { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1605:  { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
 1606:  { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G",      flags|F_DELAYED|F_FBR, v9 }, \
 1607:  { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1608:  { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1609:  { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
 1610:  { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G",   flags|F_DELAYED|F_FBR, v9 }, \
 1611:  { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 }
 1612: 
 1613: /* v9: We must put `FBRX' before `FBR', to ensure that we never match
 1614:    v9: something against an expression unless it is an expression.  Otherwise,
 1615:    v9: we end up with undefined symbol tables entries, because they get added,
 1616:    v9: but are not deleted if the pattern fails to match.  */
 1617: 
 1618: #define CONDFC(fop, cop, mask, flags) \
 1619:   FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
 1620:   FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
 1621:   CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
 1622: 
 1623: #define CONDFCL(fop, cop, mask, flags) \
 1624:   FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
 1625:   FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
 1626:   CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
 1627: 
 1628: #define CONDF(fop, mask, flags) \
 1629:   FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
 1630:   FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
 1631: 
 1632: CONDFC  ("fb",    "cb",    0x8, F_UNBR),
 1633: CONDFCL ("fba",   "cba",   0x8, F_UNBR|F_ALIAS),
 1634: CONDFC  ("fbe",   "cb0",   0x9, F_CONDBR),
 1635: CONDF   ("fbz",            0x9, F_CONDBR|F_ALIAS),
 1636: CONDFC  ("fbg",   "cb2",   0x6, F_CONDBR),
 1637: CONDFC  ("fbge",  "cb02",  0xb, F_CONDBR),
 1638: CONDFC  ("fbl",   "cb1",   0x4, F_CONDBR),
 1639: CONDFC  ("fble",  "cb01",  0xd, F_CONDBR),
 1640: CONDFC  ("fblg",  "cb12",  0x2, F_CONDBR),
 1641: CONDFCL ("fbn",   "cbn",   0x0, F_UNBR),
 1642: CONDFC  ("fbne",  "cb123", 0x1, F_CONDBR),
 1643: CONDF   ("fbnz",           0x1, F_CONDBR|F_ALIAS),
 1644: CONDFC  ("fbo",   "cb012", 0xf, F_CONDBR),
 1645: CONDFC  ("fbu",   "cb3",   0x7, F_CONDBR),
 1646: CONDFC  ("fbue",  "cb03",  0xa, F_CONDBR),
 1647: CONDFC  ("fbug",  "cb23",  0x5, F_CONDBR),
 1648: CONDFC  ("fbuge", "cb023", 0xc, F_CONDBR),
 1649: CONDFC  ("fbul",  "cb13",  0x3, F_CONDBR),
 1650: CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
 1651: 
 1652: #undef CONDFC
 1653: #undef CONDFCL
 1654: #undef CONDF
 1655: #undef CBR
 1656: #undef FBR
 1657: #undef FBRX     /* v9 */
 1658: 
 1659: { "jmp",        F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
 1660: { "jmp",        F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
 1661: { "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
 1662: { "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
 1663: { "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
 1664: { "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
 1665: 
 1666: { "nop",        F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
 1667: 
 1668: { "set",        F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 },
 1669: { "setuw",      F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
 1670: { "setsw",      F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
 1671: { "setx",       F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 },
 1672: 
 1673: { "sethi",      F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
 1674: 
 1675: { "taddcc",     F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1676: { "taddcc",     F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "1,i,d", 0, v6 },
 1677: { "taddcc",     F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "i,1,d", 0, v6 },
 1678: { "taddcctv",   F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1679: { "taddcctv",   F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "1,i,d", 0, v6 },
 1680: { "taddcctv",   F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "i,1,d", 0, v6 },
 1681: 
 1682: { "tsubcc",     F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1683: { "tsubcc",     F3(2, 0x21, 1), F3(~2, ~0x21, ~1),              "1,i,d", 0, v6 },
 1684: { "tsubcctv",   F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1685: { "tsubcctv",   F3(2, 0x23, 1), F3(~2, ~0x23, ~1),              "1,i,d", 0, v6 },
 1686: 
 1687: { "unimp",      F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 },
 1688: { "illtrap",    F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 },
 1689: 
 1690: /* This *is* a commutative instruction.  */
 1691: { "xnor",       F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1692: { "xnor",       F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "1,i,d", 0, v6 },
 1693: { "xnor",       F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "i,1,d", 0, v6 },
 1694: /* This *is* a commutative instruction.  */
 1695: { "xnorcc",     F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1696: { "xnorcc",     F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "1,i,d", 0, v6 },
 1697: { "xnorcc",     F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "i,1,d", 0, v6 },
 1698: { "xor",        F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1699: { "xor",        F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "1,i,d", 0, v6 },
 1700: { "xor",        F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,1,d", 0, v6 },
 1701: { "xorcc",      F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 1702: { "xorcc",      F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "1,i,d", 0, v6 },
 1703: { "xorcc",      F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "i,1,d", 0, v6 },
 1704: 
 1705: { "not",        F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
 1706: { "not",        F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
 1707: 
 1708: { "btog",       F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),      "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
 1709: { "btog",       F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
 1710: 
 1711: /* FPop1 and FPop2 are not instructions.  Don't accept them.  */
 1712: 
 1713: { "fdtoi",      F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 },
 1714: { "fstoi",      F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
 1715: { "fqtoi",      F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
 1716: 
 1717: { "fdtox",      F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 },
 1718: { "fstox",      F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 },
 1719: { "fqtox",      F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 },
 1720: 
 1721: { "fitod",      F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
 1722: { "fitos",      F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
 1723: { "fitoq",      F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
 1724: 
 1725: { "fxtod",      F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 },
 1726: { "fxtos",      F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 },
 1727: { "fxtoq",      F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 },
 1728: 
 1729: { "fdtoq",      F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
 1730: { "fdtos",      F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
 1731: { "fqtod",      F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 },
 1732: { "fqtos",      F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 },
 1733: { "fstod",      F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 },
 1734: { "fstoq",      F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 },
 1735: 
 1736: { "fdivd",      F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 },
 1737: { "fdivq",      F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 },
 1738: { "fdivx",      F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 },
 1739: { "fdivs",      F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 },
 1740: { "fmuld",      F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 },
 1741: { "fmulq",      F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 },
 1742: { "fmulx",      F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 },
 1743: { "fmuls",      F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 },
 1744: 
 1745: { "fdmulq",     F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 },
 1746: { "fdmulx",     F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 },
 1747: { "fsmuld",     F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 },
 1748: 
 1749: { "fsqrtd",     F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 },
 1750: { "fsqrtq",     F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 },
 1751: { "fsqrtx",     F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 },
 1752: { "fsqrts",     F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 },
 1753: 
 1754: { "fabsd",      F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 },
 1755: { "fabsq",      F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 },
 1756: { "fabsx",      F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
 1757: { "fabss",      F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 },
 1758: { "fmovd",      F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 },
 1759: { "fmovq",      F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 },
 1760: { "fmovx",      F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
 1761: { "fmovs",      F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 },
 1762: { "fnegd",      F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 },
 1763: { "fnegq",      F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 },
 1764: { "fnegx",      F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
 1765: { "fnegs",      F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 },
 1766: 
 1767: { "faddd",      F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 },
 1768: { "faddq",      F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 },
 1769: { "faddx",      F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 },
 1770: { "fadds",      F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 },
 1771: { "fsubd",      F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 },
 1772: { "fsubq",      F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 },
 1773: { "fsubx",      F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 },
 1774: { "fsubs",      F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 },
 1775: 
 1776: #define CMPFCC(x)       (((x)&0x3)<<25)
 1777: 
 1778: { "fcmpd",                F3F(2, 0x35, 0x052),            F3F(~2, ~0x35, ~0x052)|RD_G0,  "v,B",   F_FLOAT, v6 },
 1779: { "fcmpd",      CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052),        "6,v,B", F_FLOAT, v9 },
 1780: { "fcmpd",      CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052),        "7,v,B", F_FLOAT, v9 },
 1781: { "fcmpd",      CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052),        "8,v,B", F_FLOAT, v9 },
 1782: { "fcmpd",      CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052),        "9,v,B", F_FLOAT, v9 },
 1783: { "fcmped",               F3F(2, 0x35, 0x056),            F3F(~2, ~0x35, ~0x056)|RD_G0,  "v,B",   F_FLOAT, v6 },
 1784: { "fcmped",     CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056),        "6,v,B", F_FLOAT, v9 },
 1785: { "fcmped",     CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056),        "7,v,B", F_FLOAT, v9 },
 1786: { "fcmped",     CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056),        "8,v,B", F_FLOAT, v9 },
 1787: { "fcmped",     CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056),        "9,v,B", F_FLOAT, v9 },
 1788: { "fcmpq",                F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,  "V,R", F_FLOAT, v8 },
 1789: { "fcmpq",      CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),        "6,V,R", F_FLOAT, v9 },
 1790: { "fcmpq",      CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),        "7,V,R", F_FLOAT, v9 },
 1791: { "fcmpq",      CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),        "8,V,R", F_FLOAT, v9 },
 1792: { "fcmpq",      CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),        "9,V,R", F_FLOAT, v9 },
 1793: { "fcmpeq",               F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,  "V,R", F_FLOAT, v8 },
 1794: { "fcmpeq",     CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),        "6,V,R", F_FLOAT, v9 },
 1795: { "fcmpeq",     CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),        "7,V,R", F_FLOAT, v9 },
 1796: { "fcmpeq",     CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),        "8,V,R", F_FLOAT, v9 },
 1797: { "fcmpeq",     CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),        "9,V,R", F_FLOAT, v9 },
 1798: { "fcmpx",                F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,  "V,R", F_FLOAT|F_ALIAS, v8 },
 1799: { "fcmpx",      CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),        "6,V,R", F_FLOAT|F_ALIAS, v9 },
 1800: { "fcmpx",      CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),        "7,V,R", F_FLOAT|F_ALIAS, v9 },
 1801: { "fcmpx",      CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),        "8,V,R", F_FLOAT|F_ALIAS, v9 },
 1802: { "fcmpx",      CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),        "9,V,R", F_FLOAT|F_ALIAS, v9 },
 1803: { "fcmpex",               F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,  "V,R", F_FLOAT|F_ALIAS, v8 },
 1804: { "fcmpex",     CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),        "6,V,R", F_FLOAT|F_ALIAS, v9 },
 1805: { "fcmpex",     CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),        "7,V,R", F_FLOAT|F_ALIAS, v9 },
 1806: { "fcmpex",     CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),        "8,V,R", F_FLOAT|F_ALIAS, v9 },
 1807: { "fcmpex",     CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),        "9,V,R", F_FLOAT|F_ALIAS, v9 },
 1808: { "fcmps",                F3F(2, 0x35, 0x051),            F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f",   F_FLOAT, v6 },
 1809: { "fcmps",      CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051),        "6,e,f", F_FLOAT, v9 },
 1810: { "fcmps",      CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051),        "7,e,f", F_FLOAT, v9 },
 1811: { "fcmps",      CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051),        "8,e,f", F_FLOAT, v9 },
 1812: { "fcmps",      CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051),        "9,e,f", F_FLOAT, v9 },
 1813: { "fcmpes",               F3F(2, 0x35, 0x055),            F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f",   F_FLOAT, v6 },
 1814: { "fcmpes",     CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055),        "6,e,f", F_FLOAT, v9 },
 1815: { "fcmpes",     CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055),        "7,e,f", F_FLOAT, v9 },
 1816: { "fcmpes",     CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055),        "8,e,f", F_FLOAT, v9 },
 1817: { "fcmpes",     CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055),        "9,e,f", F_FLOAT, v9 },
 1818: 
 1819: /* These Extended FPop (FIFO) instructions are new in the Fujitsu
 1820:    MB86934, replacing the CPop instructions from v6 and later
 1821:    processors.  */
 1822: 
 1823: #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite }
 1824: #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op),        args, 0, sparclite }
 1825: #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0,  args, 0, sparclite }
 1826: 
 1827: EFPOP1_2 ("efitod",     0x0c8, "f,H"),
 1828: EFPOP1_2 ("efitos",     0x0c4, "f,g"),
 1829: EFPOP1_2 ("efdtoi",     0x0d2, "B,g"),
 1830: EFPOP1_2 ("efstoi",     0x0d1, "f,g"),
 1831: EFPOP1_2 ("efstod",     0x0c9, "f,H"),
 1832: EFPOP1_2 ("efdtos",     0x0c6, "B,g"),
 1833: EFPOP1_2 ("efmovs",     0x001, "f,g"),
 1834: EFPOP1_2 ("efnegs",     0x005, "f,g"),
 1835: EFPOP1_2 ("efabss",     0x009, "f,g"),
 1836: EFPOP1_2 ("efsqrtd",    0x02a, "B,H"),
 1837: EFPOP1_2 ("efsqrts",    0x029, "f,g"),
 1838: EFPOP1_3 ("efaddd",     0x042, "v,B,H"),
 1839: EFPOP1_3 ("efadds",     0x041, "e,f,g"),
 1840: EFPOP1_3 ("efsubd",     0x046, "v,B,H"),
 1841: EFPOP1_3 ("efsubs",     0x045, "e,f,g"),
 1842: EFPOP1_3 ("efdivd",     0x04e, "v,B,H"),
 1843: EFPOP1_3 ("efdivs",     0x04d, "e,f,g"),
 1844: EFPOP1_3 ("efmuld",     0x04a, "v,B,H"),
 1845: EFPOP1_3 ("efmuls",     0x049, "e,f,g"),
 1846: EFPOP1_3 ("efsmuld",    0x069, "e,f,H"),
 1847: EFPOP2_2 ("efcmpd",     0x052, "v,B"),
 1848: EFPOP2_2 ("efcmped",    0x056, "v,B"),
 1849: EFPOP2_2 ("efcmps",     0x051, "e,f"),
 1850: EFPOP2_2 ("efcmpes",    0x055, "e,f"),
 1851: 
 1852: #undef EFPOP1_2
 1853: #undef EFPOP1_3
 1854: #undef EFPOP2_2
 1855: 
 1856: /* These are marked F_ALIAS, so that they won't conflict with sparclite insns
 1857:    present.  Otherwise, the F_ALIAS flag is ignored.  */
 1858: { "cpop1",      F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 },
 1859: { "cpop2",      F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
 1860: 
 1861: /* sparclet specific insns */
 1862: 
 1863: COMMUTEOP ("umac", 0x3e, sparclet),
 1864: COMMUTEOP ("smac", 0x3f, sparclet),
 1865: COMMUTEOP ("umacd", 0x2e, sparclet),
 1866: COMMUTEOP ("smacd", 0x2f, sparclet),
 1867: COMMUTEOP ("umuld", 0x09, sparclet),
 1868: COMMUTEOP ("smuld", 0x0d, sparclet),
 1869: 
 1870: { "shuffle",    F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),      "1,2,d", 0, sparclet },
 1871: { "shuffle",    F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),              "1,i,d", 0, sparclet },
 1872: 
 1873: /* The manual isn't completely accurate on these insns.  The `rs2' field is
 1874:    treated as being 6 bits to account for 6 bit immediates to cpush.  It is
 1875:    assumed that it is intended that bit 5 is 0 when rs2 contains a reg.  */
 1876: #define BIT5 (1<<5)
 1877: { "crdcxt",     F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0),    "U,d", 0, sparclet },
 1878: { "cwrcxt",     F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0),    "1,u", 0, sparclet },
 1879: { "cpush",      F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0),     "1,2", 0, sparclet },
 1880: { "cpush",      F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0),          "1,Y", 0, sparclet },
 1881: { "cpusha",     F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0),     "1,2", 0, sparclet },
 1882: { "cpusha",     F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0),          "1,Y", 0, sparclet },
 1883: { "cpull",      F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
 1884: #undef BIT5
 1885: 
 1886: /* sparclet coprocessor branch insns */
 1887: #define SLCBCC2(opcode, mask, lose) \
 1888:  { opcode, (mask), ANNUL|(lose), "l",    F_DELAYED|F_CONDBR, sparclet }, \
 1889:  { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
 1890: #define SLCBCC(opcode, mask) \
 1891:   SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
 1892: 
 1893: /* cbn,cba can't be defined here because they're defined elsewhere and GAS
 1894:    requires all mnemonics of the same name to be consecutive.  */
 1895: /*SLCBCC("cbn", 0), - already defined */
 1896: SLCBCC("cbe", 1),
 1897: SLCBCC("cbf", 2),
 1898: SLCBCC("cbef", 3),
 1899: SLCBCC("cbr", 4),
 1900: SLCBCC("cber", 5),
 1901: SLCBCC("cbfr", 6),
 1902: SLCBCC("cbefr", 7),
 1903: /*SLCBCC("cba", 8), - already defined */
 1904: SLCBCC("cbne", 9),
 1905: SLCBCC("cbnf", 10),
 1906: SLCBCC("cbnef", 11),
 1907: SLCBCC("cbnr", 12),
 1908: SLCBCC("cbner", 13),
 1909: SLCBCC("cbnfr", 14),
 1910: SLCBCC("cbnefr", 15),
 1911: 
 1912: #undef SLCBCC2
 1913: #undef SLCBCC
 1914: 
 1915: { "casa",       F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
 1916: { "casa",       F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
 1917: { "casxa",      F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
 1918: { "casxa",      F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
 1919: 
 1920: /* v9 synthetic insns */
 1921: { "iprefetch",  F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
 1922: { "signx",      F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
 1923: { "signx",      F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
 1924: { "clruw",      F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
 1925: { "clruw",      F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
 1926: { "cas",        F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
 1927: { "casl",       F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
 1928: { "casx",       F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
 1929: { "casxl",      F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
 1930: 
 1931: /* Ultrasparc extensions */
 1932: { "shutdown",   F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
 1933: 
 1934: /* FIXME: Do we want to mark these as F_FLOAT, or something similar?  */
 1935: { "fpadd16",    F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a },
 1936: { "fpadd16s",   F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a },
 1937: { "fpadd32",    F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a },
 1938: { "fpadd32s",   F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a },
 1939: { "fpsub16",    F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a },
 1940: { "fpsub16s",   F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a },
 1941: { "fpsub32",    F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a },
 1942: { "fpsub32s",   F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a },
 1943: 
 1944: { "fpack32",    F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a },
 1945: { "fpack16",    F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a },
 1946: { "fpackfix",   F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a },
 1947: { "fexpand",    F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a },
 1948: { "fpmerge",    F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a },
 1949: 
 1950: /* Note that the mixing of 32/64 bit regs is intentional.  */
 1951: { "fmul8x16",           F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a },
 1952: { "fmul8x16au",         F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a },
 1953: { "fmul8x16al",         F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a },
 1954: { "fmul8sux16",         F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a },
 1955: { "fmul8ulx16",         F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a },
 1956: { "fmuld8sux16",        F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a },
 1957: { "fmuld8ulx16",        F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a },
 1958: 
 1959: { "alignaddr",  F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a },
 1960: { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a },
 1961: { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a },
 1962: 
 1963: { "fzero",      F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a },
 1964: { "fzeros",     F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a },
 1965: { "fone",       F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a },
 1966: { "fones",      F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a },
 1967: { "fsrc1",      F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a },
 1968: { "fsrc1s",     F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a },
 1969: { "fsrc2",      F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a },
 1970: { "fsrc2s",     F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a },
 1971: { "fnot1",      F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a },
 1972: { "fnot1s",     F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a },
 1973: { "fnot2",      F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a },
 1974: { "fnot2s",     F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a },
 1975: { "for",        F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a },
 1976: { "fors",       F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a },
 1977: { "fnor",       F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a },
 1978: { "fnors",      F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a },
 1979: { "fand",       F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a },
 1980: { "fands",      F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a },
 1981: { "fnand",      F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a },
 1982: { "fnands",     F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a },
 1983: { "fxor",       F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a },
 1984: { "fxors",      F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a },
 1985: { "fxnor",      F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a },
 1986: { "fxnors",     F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a },
 1987: { "fornot1",    F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a },
 1988: { "fornot1s",   F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a },
 1989: { "fornot2",    F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a },
 1990: { "fornot2s",   F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a },
 1991: { "fandnot1",   F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a },
 1992: { "fandnot1s",  F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a },
 1993: { "fandnot2",   F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a },
 1994: { "fandnot2s",  F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a },
 1995: 
 1996: { "fcmpgt16",   F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a },
 1997: { "fcmpgt32",   F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a },
 1998: { "fcmple16",   F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a },
 1999: { "fcmple32",   F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a },
 2000: { "fcmpne16",   F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a },
 2001: { "fcmpne32",   F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a },
 2002: { "fcmpeq16",   F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a },
 2003: { "fcmpeq32",   F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a },
 2004: 
 2005: { "edge8",      F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a },
 2006: { "edge8l",     F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a },
 2007: { "edge16",     F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a },
 2008: { "edge16l",    F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a },
 2009: { "edge32",     F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a },
 2010: { "edge32l",    F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a },
 2011: 
 2012: { "pdist",      F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a },
 2013: 
 2014: { "array8",     F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a },
 2015: { "array16",    F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
 2016: { "array32",    F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
 2017: 
 2018: /* Cheetah instructions */
 2019: { "edge8n",    F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
 2020: { "edge8ln",   F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
 2021: { "edge16n",   F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
 2022: { "edge16ln",  F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
 2023: { "edge32n",   F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
 2024: { "edge32ln",  F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
 2025: 
 2026: { "bmask",     F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
 2027: { "bshuffle",  F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
 2028: 
 2029: { "siam",      F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
 2030: 
 2031: /* More v9 specific insns, these need to come last so they do not clash
 2032:    with v9a instructions such as "edge8" which looks like impdep1. */
 2033: 
 2034: #define IMPDEP(name, code) \
 2035: { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
 2036: { name, F3(2, code, 1), F3(~2, ~code, ~1),         "1,i,d", 0, v9notv9a }, \
 2037: { name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,1,2,d", 0, v9notv9a }, \
 2038: { name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,e,f,g", 0, v9notv9a }
 2039: 
 2040: IMPDEP ("impdep1", 0x36),
 2041: IMPDEP ("impdep2", 0x37),
 2042: 
 2043: #undef IMPDEP
 2044: 
 2045: };
 2046: 
 2047: static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
 2048: 
 2049: /* Utilities for argument parsing.  */
 2050: 
 2051: typedef struct
 2052: {
 2053:   int value;
 2054:   const char *name;
 2055: } arg;
 2056: 
 2057: /* Look up VALUE in TABLE.  */
 2058: 
 2059: static const char *
 2060: lookup_value (const arg *table, int value)
 2061: {
 2062:   const arg *p;
 2063: 
 2064:   for (p = table; p->name; ++p)
 2065:     if (value == p->value)
 2066:       return p->name;
 2067: 
 2068:   return NULL;
 2069: }
 2070: 
 2071: /* Handle ASI's.  */
 2072: 
 2073: static const arg asi_table_v8[] =
 2074: {
 2075:   { 0x00, "#ASI_M_RES00" },
 2076:   { 0x01, "#ASI_M_UNA01" },
 2077:   { 0x02, "#ASI_M_MXCC" },
 2078:   { 0x03, "#ASI_M_FLUSH_PROBE" },
 2079:   { 0x04, "#ASI_M_MMUREGS" },
 2080:   { 0x05, "#ASI_M_TLBDIAG" },
 2081:   { 0x06, "#ASI_M_DIAGS" },
 2082:   { 0x07, "#ASI_M_IODIAG" },
 2083:   { 0x08, "#ASI_M_USERTXT" },
 2084:   { 0x09, "#ASI_M_KERNELTXT" },
 2085:   { 0x0A, "#ASI_M_USERDATA" },
 2086:   { 0x0B, "#ASI_M_KERNELDATA" },
 2087:   { 0x0C, "#ASI_M_TXTC_TAG" },
 2088:   { 0x0D, "#ASI_M_TXTC_DATA" },
 2089:   { 0x0E, "#ASI_M_DATAC_TAG" },
 2090:   { 0x0F, "#ASI_M_DATAC_DATA" },
 2091:   { 0x10, "#ASI_M_FLUSH_PAGE" },
 2092:   { 0x11, "#ASI_M_FLUSH_SEG" },
 2093:   { 0x12, "#ASI_M_FLUSH_REGION" },
 2094:   { 0x13, "#ASI_M_FLUSH_CTX" },
 2095:   { 0x14, "#ASI_M_FLUSH_USER" },
 2096:   { 0x17, "#ASI_M_BCOPY" },
 2097:   { 0x18, "#ASI_M_IFLUSH_PAGE" },
 2098:   { 0x19, "#ASI_M_IFLUSH_SEG" },
 2099:   { 0x1A, "#ASI_M_IFLUSH_REGION" },
 2100:   { 0x1B, "#ASI_M_IFLUSH_CTX" },
 2101:   { 0x1C, "#ASI_M_IFLUSH_USER" },
 2102:   { 0x1F, "#ASI_M_BFILL" },
 2103:   { 0x20, "#ASI_M_BYPASS" },
 2104:   { 0x29, "#ASI_M_FBMEM" },
 2105:   { 0x2A, "#ASI_M_VMEUS" },
 2106:   { 0x2B, "#ASI_M_VMEPS" },
 2107:   { 0x2C, "#ASI_M_VMEUT" },
 2108:   { 0x2D, "#ASI_M_VMEPT" },
 2109:   { 0x2E, "#ASI_M_SBUS" },
 2110:   { 0x2F, "#ASI_M_CTL" },
 2111:   { 0x31, "#ASI_M_FLUSH_IWHOLE" },
 2112:   { 0x36, "#ASI_M_IC_FLCLEAR" },
 2113:   { 0x37, "#ASI_M_DC_FLCLEAR" },
 2114:   { 0x39, "#ASI_M_DCDR" },
 2115:   { 0x40, "#ASI_M_VIKING_TMP1" },
 2116:   { 0x41, "#ASI_M_VIKING_TMP2" },
 2117:   { 0x4c, "#ASI_M_ACTION" },
 2118:   { 0, NULL }
 2119: };
 2120: 
 2121: static const arg asi_table_v9[] =
 2122: {
 2123:   /* These are in the v9 architecture manual.  */
 2124:   /* The shorter versions appear first, they're here because Sun's as has them.
 2125:      Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
 2126:      UltraSPARC architecture manual).  */
 2127:   { 0x04, "#ASI_N" },
 2128:   { 0x0c, "#ASI_N_L" },
 2129:   { 0x10, "#ASI_AIUP" },
 2130:   { 0x11, "#ASI_AIUS" },
 2131:   { 0x18, "#ASI_AIUP_L" },
 2132:   { 0x19, "#ASI_AIUS_L" },
 2133:   { 0x80, "#ASI_P" },
 2134:   { 0x81, "#ASI_S" },
 2135:   { 0x82, "#ASI_PNF" },
 2136:   { 0x83, "#ASI_SNF" },
 2137:   { 0x88, "#ASI_P_L" },
 2138:   { 0x89, "#ASI_S_L" },
 2139:   { 0x8a, "#ASI_PNF_L" },
 2140:   { 0x8b, "#ASI_SNF_L" },
 2141:   { 0x04, "#ASI_NUCLEUS" },
 2142:   { 0x0c, "#ASI_NUCLEUS_LITTLE" },
 2143:   { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
 2144:   { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
 2145:   { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
 2146:   { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
 2147:   { 0x80, "#ASI_PRIMARY" },
 2148:   { 0x81, "#ASI_SECONDARY" },
 2149:   { 0x82, "#ASI_PRIMARY_NOFAULT" },
 2150:   { 0x83, "#ASI_SECONDARY_NOFAULT" },
 2151:   { 0x88, "#ASI_PRIMARY_LITTLE" },
 2152:   { 0x89, "#ASI_SECONDARY_LITTLE" },
 2153:   { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
 2154:   { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
 2155:   /* These are UltraSPARC extensions.  */
 2156:   { 0x14, "#ASI_PHYS_USE_EC"},
 2157:   { 0x15, "#ASI_PHYS_BYPASS_EC_WITH_EBIT"},
 2158:   { 0x45, "#ASI_LSU_CONTROL_REG"},
 2159:   { 0x47, "#ASI_DCACHE_TAG"},
 2160:   { 0x4a, "#ASI_UPA_CONFIG_REG"},
 2161:   { 0x50, "#ASI_IMMU" },
 2162:   { 0x51, "#ASI_IMMU_TSB_8KB_PTR_REG" },
 2163:   { 0x52, "#ASI_IMMU_TSB_64KB_PTR_REG" },
 2164:   /*{ 0x53, "#reserved?" },*/
 2165:   { 0x54, "#ASI_ITLB_DATA_IN_REG" },
 2166:   { 0x55, "#ASI_ITLB_DATA_ACCESS_REG" },
 2167:   { 0x56, "#ASI_ITLB_TAG_READ_REG" },
 2168:   { 0x57, "#ASI_IMMU_DEMAP" },
 2169:   { 0x58, "#ASI_DMMU" },
 2170:   { 0x59, "#ASI_DMMU_TSB_8KB_PTR_REG" },
 2171:   { 0x5a, "#ASI_DMMU_TSB_64KB_PTR_REG" },
 2172:   { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR_REG" },
 2173:   { 0x5c, "#ASI_DTLB_DATA_IN_REG" },
 2174:   { 0x5d, "#ASI_DTLB_DATA_ACCESS_REG" },
 2175:   { 0x5e, "#ASI_DTLB_TAG_READ_REG" },
 2176:   { 0x5f, "#ASI_DMMU_DEMAP" },
 2177:   { 0x67, "#ASI_IC_TAG"},
 2178:   /* FIXME: There are dozens of them.  Not sure we want them all.
 2179:      Most are for kernel building but some are for vis type stuff.  */
 2180:   { 0, NULL }
 2181: };
 2182: 
 2183: /* Return the name for ASI value VALUE or NULL if not found.  */
 2184: 
 2185: static const char *
 2186: sparc_decode_asi_v9 (int value)
 2187: {
 2188:   return lookup_value (asi_table_v9, value);
 2189: }
 2190: 
 2191: static const char *
 2192: sparc_decode_asi_v8 (int value)
 2193: {
 2194:   return lookup_value (asi_table_v8, value);
 2195: }
 2196: 
 2197: /* Handle membar masks.  */
 2198: 
 2199: static const arg membar_table[] =
 2200: {
 2201:   { 0x40, "#Sync" },
 2202:   { 0x20, "#MemIssue" },
 2203:   { 0x10, "#Lookaside" },
 2204:   { 0x08, "#StoreStore" },
 2205:   { 0x04, "#LoadStore" },
 2206:   { 0x02, "#StoreLoad" },
 2207:   { 0x01, "#LoadLoad" },
 2208:   { 0, NULL }
 2209: };
 2210: 
 2211: /* Return the name for membar value VALUE or NULL if not found.  */
 2212: 
 2213: static const char *
 2214: sparc_decode_membar (int value)
 2215: {
 2216:   return lookup_value (membar_table, value);
 2217: }
 2218: 
 2219: /* Handle prefetch args.  */
 2220: 
 2221: static const arg prefetch_table[] =
 2222: {
 2223:   { 0, "#n_reads" },
 2224:   { 1, "#one_read" },
 2225:   { 2, "#n_writes" },
 2226:   { 3, "#one_write" },
 2227:   { 4, "#page" },
 2228:   { 16, "#invalidate" },
 2229:   { 0, NULL }
 2230: };
 2231: 
 2232: /* Return the name for prefetch value VALUE or NULL if not found.  */
 2233: 
 2234: static const char *
 2235: sparc_decode_prefetch (int value)
 2236: {
 2237:   return lookup_value (prefetch_table, value);
 2238: }
 2239: 
 2240: /* Handle sparclet coprocessor registers.  */
 2241: 
 2242: static const arg sparclet_cpreg_table[] =
 2243: {
 2244:   { 0, "%ccsr" },
 2245:   { 1, "%ccfr" },
 2246:   { 2, "%cccrcr" },
 2247:   { 3, "%ccpr" },
 2248:   { 4, "%ccsr2" },
 2249:   { 5, "%cccrr" },
 2250:   { 6, "%ccrstr" },
 2251:   { 0, NULL }
 2252: };
 2253: 
 2254: /* Return the name for sparclet cpreg value VALUE or NULL if not found.  */
 2255: 
 2256: static const char *
 2257: sparc_decode_sparclet_cpreg (int value)
 2258: {
 2259:   return lookup_value (sparclet_cpreg_table, value);
 2260: }
 2261: 
 2262: #undef MASK_V9
 2263: 
 2264: /* opcodes/sparc-dis.c */
 2265: 
 2266: /* Print SPARC instructions.
 2267:    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
 2268:    2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 2269: 
 2270:    This program is free software; you can redistribute it and/or modify
 2271:    it under the terms of the GNU General Public License as published by
 2272:    the Free Software Foundation; either version 2 of the License, or
 2273:    (at your option) any later version.
 2274: 
 2275:    This program is distributed in the hope that it will be useful,
 2276:    but WITHOUT ANY WARRANTY; without even the implied warranty of
 2277:    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 2278:    GNU General Public License for more details.
 2279: 
 2280:    You should have received a copy of the GNU General Public License
 2281:    along with this program; if not, see <http://www.gnu.org/licenses/>.  */
 2282: 
 2283: /* Bitmask of v9 architectures.  */
 2284: #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
 2285:                  | (1 << SPARC_OPCODE_ARCH_V9A) \
 2286:                  | (1 << SPARC_OPCODE_ARCH_V9B))
 2287: /* 1 if INSN is for v9 only.  */
 2288: #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
 2289: /* 1 if INSN is for v9.  */
 2290: #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
 2291: 
 2292: /* The sorted opcode table.  */
 2293: static const sparc_opcode **sorted_opcodes;
 2294: 
 2295: /* For faster lookup, after insns are sorted they are hashed.  */
 2296: /* ??? I think there is room for even more improvement.  */
 2297: 
 2298: #define HASH_SIZE 256
 2299: /* It is important that we only look at insn code bits as that is how the
 2300:    opcode table is hashed.  OPCODE_BITS is a table of valid bits for each
 2301:    of the main types (0,1,2,3).  */
 2302: static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
 2303: #define HASH_INSN(INSN) \
 2304:   ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
 2305: typedef struct sparc_opcode_hash
 2306: {
 2307:   struct sparc_opcode_hash *next;
 2308:   const sparc_opcode *opcode;
 2309: } sparc_opcode_hash;
 2310: 
 2311: static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
 2312: 
 2313: /* Sign-extend a value which is N bits long.  */
 2314: #define SEX(value, bits) \
 2315:         ((((int)(value)) << ((8 * sizeof (int)) - bits))        \
 2316:                          >> ((8 * sizeof (int)) - bits) )
 2317: 
 2318: static const char * const reg_names[] =
 2319: { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
 2320:   "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
 2321:   "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
 2322:   "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
 2323:   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
 2324:   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
 2325:   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
 2326:   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
 2327:   "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
 2328:   "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
 2329:   "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
 2330:   "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
 2331: /* psr, wim, tbr, fpsr, cpsr are v8 only.  */
 2332:   "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
 2333: };
 2334: 
 2335: #define freg_names      (&reg_names[4 * 8])
 2336: 
 2337: /* These are ordered according to there register number in
 2338:    rdpr and wrpr insns.  */
 2339: static const char * const v9_priv_reg_names[] =
 2340: {
 2341:   "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
 2342:   "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
 2343:   "wstate", "fq", "gl"
 2344:   /* "ver" - special cased */
 2345: };
 2346: 
 2347: /* These are ordered according to there register number in
 2348:    rdhpr and wrhpr insns.  */
 2349: static const char * const v9_hpriv_reg_names[] =
 2350: {
 2351:   "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
 2352:   "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
 2353:   "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
 2354:   "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
 2355:   "resv28", "resv29", "resv30", "hstick_cmpr"
 2356: };
 2357: 
 2358: /* These are ordered according to there register number in
 2359:    rd and wr insns (-16).  */
 2360: static const char * const v9a_asr_reg_names[] =
 2361: {
 2362:   "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
 2363:   "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
 2364: };
 2365: 
 2366: /* Macros used to extract instruction fields.  Not all fields have
 2367:    macros defined here, only those which are actually used.  */
 2368: 
 2369: #define X_RD(i)      (((i) >> 25) & 0x1f)
 2370: #define X_RS1(i)     (((i) >> 14) & 0x1f)
 2371: #define X_LDST_I(i)  (((i) >> 13) & 1)
 2372: #define X_ASI(i)     (((i) >> 5) & 0xff)
 2373: #define X_RS2(i)     (((i) >> 0) & 0x1f)
 2374: #define X_IMM(i,n)   (((i) >> 0) & ((1 << (n)) - 1))
 2375: #define X_SIMM(i,n)  SEX (X_IMM ((i), (n)), (n))
 2376: #define X_DISP22(i)  (((i) >> 0) & 0x3fffff)
 2377: #define X_IMM22(i)   X_DISP22 (i)
 2378: #define X_DISP30(i)  (((i) >> 0) & 0x3fffffff)
 2379: 
 2380: /* These are for v9.  */
 2381: #define X_DISP16(i)  (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
 2382: #define X_DISP19(i)  (((i) >> 0) & 0x7ffff)
 2383: #define X_MEMBAR(i)  ((i) & 0x7f)
 2384: 
 2385: /* Here is the union which was used to extract instruction fields
 2386:    before the shift and mask macros were written.
 2387: 
 2388:    union sparc_insn
 2389:      {
 2390:        unsigned long int code;
 2391:        struct
 2392:          {
 2393:            unsigned int anop:2;
 2394:            #define      op      ldst.anop
 2395:            unsigned int anrd:5;
 2396:            #define      rd      ldst.anrd
 2397:            unsigned int op3:6;
 2398:            unsigned int anrs1:5;
 2399:            #define      rs1     ldst.anrs1
 2400:            unsigned int i:1;
 2401:            unsigned int anasi:8;
 2402:            #define      asi     ldst.anasi
 2403:            unsigned int anrs2:5;
 2404:            #define      rs2     ldst.anrs2
 2405:            #define      shcnt   rs2
 2406:          } ldst;
 2407:        struct
 2408:          {
 2409:            unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
 2410:            unsigned int IMM13:13;
 2411:            #define      imm13   IMM13.IMM13
 2412:          } IMM13;
 2413:        struct
 2414:          {
 2415:            unsigned int anop:2;
 2416:            unsigned int a:1;
 2417:            unsigned int cond:4;
 2418:            unsigned int op2:3;
 2419:            unsigned int DISP22:22;
 2420:            #define      disp22  branch.DISP22
 2421:            #define      imm22   disp22
 2422:          } branch;
 2423:        struct
 2424:          {
 2425:            unsigned int anop:2;
 2426:            unsigned int a:1;
 2427:            unsigned int z:1;
 2428:            unsigned int rcond:3;
 2429:            unsigned int op2:3;
 2430:            unsigned int DISP16HI:2;
 2431:            unsigned int p:1;
 2432:            unsigned int _rs1:5;
 2433:            unsigned int DISP16LO:14;
 2434:          } branch16;
 2435:        struct
 2436:          {
 2437:            unsigned int anop:2;
 2438:            unsigned int adisp30:30;
 2439:            #define      disp30  call.adisp30
 2440:          } call;
 2441:      };  */
 2442: 
 2443: /* Nonzero if INSN is the opcode for a delayed branch.  */
 2444: 
 2445: static int
 2446: is_delayed_branch (unsigned long insn)
 2447: {
 2448:   sparc_opcode_hash *op;
 2449: 
 2450:   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
 2451:     {
 2452:       const sparc_opcode *opcode = op->opcode;
 2453: 
 2454:       if ((opcode->match & insn) == opcode->match
 2455:           && (opcode->lose & insn) == 0)
 2456:         return opcode->flags & F_DELAYED;
 2457:     }
 2458:   return 0;
 2459: }
 2460: 
 2461: /* extern void qsort (); */
 2462: 
 2463: /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
 2464:    to compare_opcodes.  */
 2465: static unsigned int current_arch_mask;
 2466: 
 2467: /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values.  */
 2468: 
 2469: static int
 2470: compute_arch_mask (unsigned long mach)
 2471: {
 2472:   switch (mach)
 2473:     {
 2474:     case 0 :
 2475:     case bfd_mach_sparc :
 2476:       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
 2477:     case bfd_mach_sparc_sparclet :
 2478:       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
 2479:     case bfd_mach_sparc_sparclite :
 2480:     case bfd_mach_sparc_sparclite_le :
 2481:       /* sparclites insns are recognized by default (because that's how
 2482:          they've always been treated, for better or worse).  Kludge this by
 2483:          indicating generic v8 is also selected.  */
 2484:       return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
 2485:               | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
 2486:     case bfd_mach_sparc_v8plus :
 2487:     case bfd_mach_sparc_v9 :
 2488:       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
 2489:     case bfd_mach_sparc_v8plusa :
 2490:     case bfd_mach_sparc_v9a :
 2491:       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
 2492:     case bfd_mach_sparc_v8plusb :
 2493:     case bfd_mach_sparc_v9b :
 2494:       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
 2495:     }
 2496:   abort ();
 2497: }
 2498: 
 2499: /* Compare opcodes A and B.  */
 2500: 
 2501: static int
 2502: compare_opcodes (const void * a, const void * b)
 2503: {
 2504:   sparc_opcode *op0 = * (sparc_opcode **) a;
 2505:   sparc_opcode *op1 = * (sparc_opcode **) b;
 2506:   unsigned long int match0 = op0->match, match1 = op1->match;
 2507:   unsigned long int lose0 = op0->lose, lose1 = op1->lose;
 2508:   register unsigned int i;
 2509: 
 2510:   /* If one (and only one) insn isn't supported by the current architecture,
 2511:      prefer the one that is.  If neither are supported, but they're both for
 2512:      the same architecture, continue processing.  Otherwise (both unsupported
 2513:      and for different architectures), prefer lower numbered arch's (fudged
 2514:      by comparing the bitmasks).  */
 2515:   if (op0->architecture & current_arch_mask)
 2516:     {
 2517:       if (! (op1->architecture & current_arch_mask))
 2518:         return -1;
 2519:     }
 2520:   else
 2521:     {
 2522:       if (op1->architecture & current_arch_mask)
 2523:         return 1;
 2524:       else if (op0->architecture != op1->architecture)
 2525:         return op0->architecture - op1->architecture;
 2526:     }
 2527: 
 2528:   /* If a bit is set in both match and lose, there is something
 2529:      wrong with the opcode table.  */
 2530:   if (match0 & lose0)
 2531:     {
 2532:       fprintf
 2533:         (stderr,
 2534:          /* xgettext:c-format */
 2535:          _("Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
 2536:          op0->name, match0, lose0);
 2537:       op0->lose &= ~op0->match;
 2538:       lose0 = op0->lose;
 2539:     }
 2540: 
 2541:   if (match1 & lose1)
 2542:     {
 2543:       fprintf
 2544:         (stderr,
 2545:          /* xgettext:c-format */
 2546:          _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
 2547:          op1->name, match1, lose1);
 2548:       op1->lose &= ~op1->match;
 2549:       lose1 = op1->lose;
 2550:     }
 2551: 
 2552:   /* Because the bits that are variable in one opcode are constant in
 2553:      another, it is important to order the opcodes in the right order.  */
 2554:   for (i = 0; i < 32; ++i)
 2555:     {
 2556:       unsigned long int x = 1 << i;
 2557:       int x0 = (match0 & x) != 0;
 2558:       int x1 = (match1 & x) != 0;
 2559: 
 2560:       if (x0 != x1)
 2561:         return x1 - x0;
 2562:     }
 2563: 
 2564:   for (i = 0; i < 32; ++i)
 2565:     {
 2566:       unsigned long int x = 1 << i;
 2567:       int x0 = (lose0 & x) != 0;
 2568:       int x1 = (lose1 & x) != 0;
 2569: 
 2570:       if (x0 != x1)
 2571:         return x1 - x0;
 2572:     }
 2573: 
 2574:   /* They are functionally equal.  So as long as the opcode table is
 2575:      valid, we can put whichever one first we want, on aesthetic grounds.  */
 2576: 
 2577:   /* Our first aesthetic ground is that aliases defer to real insns.  */
 2578:   {
 2579:     int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
 2580: 
 2581:     if (alias_diff != 0)
 2582:       /* Put the one that isn't an alias first.  */
 2583:       return alias_diff;
 2584:   }
 2585: 
 2586:   /* Except for aliases, two "identical" instructions had
 2587:      better have the same opcode.  This is a sanity check on the table.  */
 2588:   i = strcmp (op0->name, op1->name);
 2589:   if (i)
 2590:     {
 2591:       if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary.  */
 2592:         return i;
 2593:       else
 2594:         fprintf (stderr,
 2595:                  /* xgettext:c-format */
 2596:                  _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
 2597:                  op0->name, op1->name);
 2598:     }
 2599: 
 2600:   /* Fewer arguments are preferred.  */
 2601:   {
 2602:     int length_diff = strlen (op0->args) - strlen (op1->args);
 2603: 
 2604:     if (length_diff != 0)
 2605:       /* Put the one with fewer arguments first.  */
 2606:       return length_diff;
 2607:   }
 2608: 
 2609:   /* Put 1+i before i+1.  */
 2610:   {
 2611:     char *p0 = (char *) strchr (op0->args, '+');
 2612:     char *p1 = (char *) strchr (op1->args, '+');
 2613: 
 2614:     if (p0 && p1)
 2615:       {
 2616:         /* There is a plus in both operands.  Note that a plus
 2617:            sign cannot be the first character in args,
 2618:            so the following [-1]'s are valid.  */
 2619:         if (p0[-1] == 'i' && p1[1] == 'i')
 2620:           /* op0 is i+1 and op1 is 1+i, so op1 goes first.  */
 2621:           return 1;
 2622:         if (p0[1] == 'i' && p1[-1] == 'i')
 2623:           /* op0 is 1+i and op1 is i+1, so op0 goes first.  */
 2624:           return -1;
 2625:       }
 2626:   }
 2627: 
 2628:   /* Put 1,i before i,1.  */
 2629:   {
 2630:     int i0 = strncmp (op0->args, "i,1", 3) == 0;
 2631:     int i1 = strncmp (op1->args, "i,1", 3) == 0;
 2632: 
 2633:     if (i0 ^ i1)
 2634:       return i0 - i1;
 2635:   }
 2636: 
 2637:   /* They are, as far as we can tell, identical.
 2638:      Since qsort may have rearranged the table partially, there is
 2639:      no way to tell which one was first in the opcode table as
 2640:      written, so just say there are equal.  */
 2641:   /* ??? This is no longer true now that we sort a vector of pointers,
 2642:      not the table itself.  */
 2643:   return 0;
 2644: }
 2645: 
 2646: /* Build a hash table from the opcode table.
 2647:    OPCODE_TABLE is a sorted list of pointers into the opcode table.  */
 2648: 
 2649: static void
 2650: build_hash_table (const sparc_opcode **opcode_table,
 2651:                   sparc_opcode_hash **hash_table,
 2652:                   int num_opcodes)
 2653: {
 2654:   int i;
 2655:   int hash_count[HASH_SIZE];
 2656:   static sparc_opcode_hash *hash_buf = NULL;
 2657: 
 2658:   /* Start at the end of the table and work backwards so that each
 2659:      chain is sorted.  */
 2660: 
 2661:   memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
 2662:   memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
 2663:   if (hash_buf != NULL)
 2664:     free (hash_buf);
 2665:   hash_buf = malloc (sizeof (* hash_buf) * num_opcodes);
 2666:   for (i = num_opcodes - 1; i >= 0; --i)
 2667:     {
 2668:       int hash = HASH_INSN (opcode_table[i]->match);
 2669:       sparc_opcode_hash *h = &hash_buf[i];
 2670: 
 2671:       h->next = hash_table[hash];
 2672:       h->opcode = opcode_table[i];
 2673:       hash_table[hash] = h;
 2674:       ++hash_count[hash];
 2675:     }
 2676: 
 2677: #if 0 /* for debugging */
 2678:   {
 2679:     int min_count = num_opcodes, max_count = 0;
 2680:     int total;
 2681: 
 2682:     for (i = 0; i < HASH_SIZE; ++i)
 2683:       {
 2684:         if (hash_count[i] < min_count)
 2685:           min_count = hash_count[i];
 2686:         if (hash_count[i] > max_count)
 2687:           max_count = hash_count[i];
 2688:         total += hash_count[i];
 2689:       }
 2690: 
 2691:     printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
 2692:             min_count, max_count, (double) total / HASH_SIZE);
 2693:   }
 2694: #endif
 2695: }
 2696: 
 2697: /* Print one instruction from MEMADDR on INFO->STREAM.
 2698: 
 2699:    We suffix the instruction with a comment that gives the absolute
 2700:    address involved, as well as its symbolic form, if the instruction
 2701:    is preceded by a findable `sethi' and it either adds an immediate
 2702:    displacement to that register, or it is an `add' or `or' instruction
 2703:    on that register.  */
 2704: 
 2705: int
 2706: print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
 2707: {
 2708:   FILE *stream = info->stream;
 2709:   bfd_byte buffer[4];
 2710:   unsigned long insn;
 2711:   sparc_opcode_hash *op;
 2712:   /* Nonzero of opcode table has been initialized.  */
 2713:   static int opcodes_initialized = 0;
 2714:   /* bfd mach number of last call.  */
 2715:   static unsigned long current_mach = 0;
 2716:   bfd_vma (*getword) (const unsigned char *);
 2717: 
 2718:   if (!opcodes_initialized
 2719:       || info->mach != current_mach)
 2720:     {
 2721:       int i;
 2722: 
 2723:       current_arch_mask = compute_arch_mask (info->mach);
 2724: 
 2725:       if (!opcodes_initialized)
 2726:         sorted_opcodes =
 2727:           malloc (sparc_num_opcodes * sizeof (sparc_opcode *));
 2728:       /* Reset the sorted table so we can resort it.  */
 2729:       for (i = 0; i < sparc_num_opcodes; ++i)
 2730:         sorted_opcodes[i] = &sparc_opcodes[i];
 2731:       qsort ((char *) sorted_opcodes, sparc_num_opcodes,
 2732:              sizeof (sorted_opcodes[0]), compare_opcodes);
 2733: 
 2734:       build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
 2735:       current_mach = info->mach;
 2736:       opcodes_initialized = 1;
 2737:     }
 2738: 
 2739:   {
 2740:     int status =
 2741:       (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
 2742: 
 2743:     if (status != 0)
 2744:       {
 2745:         (*info->memory_error_func) (status, memaddr, info);
 2746:         return -1;
 2747:       }
 2748:   }
 2749: 
 2750:   /* On SPARClite variants such as DANlite (sparc86x), instructions
 2751:      are always big-endian even when the machine is in little-endian mode.  */
 2752:   if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
 2753:     getword = bfd_getb32;
 2754:   else
 2755:     getword = bfd_getl32;
 2756: 
 2757:   insn = getword (buffer);
 2758: 
 2759:   info->insn_info_valid = 1;                    /* We do return this info.  */
 2760:   info->insn_type = dis_nonbranch;              /* Assume non branch insn.  */
 2761:   info->branch_delay_insns = 0;                 /* Assume no delay.  */
 2762:   info->target = 0;                             /* Assume no target known.  */
 2763: 
 2764:   for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
 2765:     {
 2766:       const sparc_opcode *opcode = op->opcode;
 2767: 
 2768:       /* If the insn isn't supported by the current architecture, skip it.  */
 2769:       if (! (opcode->architecture & current_arch_mask))
 2770:         continue;
 2771: 
 2772:       if ((opcode->match & insn) == opcode->match
 2773:           && (opcode->lose & insn) == 0)
 2774:         {
 2775:           /* Nonzero means that we have found an instruction which has
 2776:              the effect of adding or or'ing the imm13 field to rs1.  */
 2777:           int imm_added_to_rs1 = 0;
 2778:           int imm_ored_to_rs1 = 0;
 2779: 
 2780:           /* Nonzero means that we have found a plus sign in the args
 2781:              field of the opcode table.  */
 2782:           int found_plus = 0;
 2783: 
 2784:           /* Nonzero means we have an annulled branch.  */
 2785:           /* int is_annulled = 0; */ /* see FIXME below */
 2786: 
 2787:           /* Do we have an `add' or `or' instruction combining an
 2788:              immediate with rs1?  */
 2789:           if (opcode->match == 0x80102000) /* or */
 2790:             imm_ored_to_rs1 = 1;
 2791:           if (opcode->match == 0x80002000) /* add */
 2792:             imm_added_to_rs1 = 1;
 2793: 
 2794:           if (X_RS1 (insn) != X_RD (insn)
 2795:               && strchr (opcode->args, 'r') != NULL)
 2796:               /* Can't do simple format if source and dest are different.  */
 2797:               continue;
 2798:           if (X_RS2 (insn) != X_RD (insn)
 2799:               && strchr (opcode->args, 'O') != NULL)
 2800:               /* Can't do simple format if source and dest are different.  */
 2801:               continue;
 2802: 
 2803:           (*info->fprintf_func) (stream, "%s", opcode->name);
 2804: 
 2805:           {
 2806:             const char *s;
 2807: 
 2808:             if (opcode->args[0] != ',')
 2809:               (*info->fprintf_func) (stream, " ");
 2810: 
 2811:             for (s = opcode->args; *s != '\0'; ++s)
 2812:               {
 2813:                 while (*s == ',')
 2814:                   {
 2815:                     (*info->fprintf_func) (stream, ",");
 2816:                     ++s;
 2817:                     switch (*s)
 2818:                       {
 2819:                       case 'a':
 2820:                         (*info->fprintf_func) (stream, "a");
 2821:                         /* is_annulled = 1; */ /* see FIXME below */
 2822:                         ++s;
 2823:                         continue;
 2824:                       case 'N':
 2825:                         (*info->fprintf_func) (stream, "pn");
 2826:                         ++s;
 2827:                         continue;
 2828: 
 2829:                       case 'T':
 2830:                         (*info->fprintf_func) (stream, "pt");
 2831:                         ++s;
 2832:                         continue;
 2833: 
 2834:                       default:
 2835:                         break;
 2836:                       }
 2837:                   }
 2838: 
 2839:                 (*info->fprintf_func) (stream, " ");
 2840: 
 2841:                 switch (*s)
 2842:                   {
 2843:                   case '+':
 2844:                     found_plus = 1;
 2845:                     /* Fall through.  */
 2846: 
 2847:                   default:
 2848:                     (*info->fprintf_func) (stream, "%c", *s);
 2849:                     break;
 2850: 
 2851:                   case '#':
 2852:                     (*info->fprintf_func) (stream, "0");
 2853:                     break;
 2854: 
 2855: #define reg(n)  (*info->fprintf_func) (stream, "%%%s", reg_names[n])
 2856:                   case '1':
 2857:                   case 'r':
 2858:                     reg (X_RS1 (insn));
 2859:                     break;
 2860: 
 2861:                   case '2':
 2862:                   case 'O':
 2863:                     reg (X_RS2 (insn));
 2864:                     break;
 2865: 
 2866:                   case 'd':
 2867:                     reg (X_RD (insn));
 2868:                     break;
 2869: #undef  reg
 2870: 
 2871: #define freg(n)         (*info->fprintf_func) (stream, "%%%s", freg_names[n])
 2872: #define fregx(n)        (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
 2873:                   case 'e':
 2874:                     freg (X_RS1 (insn));
 2875:                     break;
 2876:                   case 'v':     /* Double/even.  */
 2877:                   case 'V':     /* Quad/multiple of 4.  */
 2878:                     fregx (X_RS1 (insn));
 2879:                     break;
 2880: 
 2881:                   case 'f':
 2882:                     freg (X_RS2 (insn));
 2883:                     break;
 2884:                   case 'B':     /* Double/even.  */
 2885:                   case 'R':     /* Quad/multiple of 4.  */
 2886:                     fregx (X_RS2 (insn));
 2887:                     break;
 2888: 
 2889:                   case 'g':
 2890:                     freg (X_RD (insn));
 2891:                     break;
 2892:                   case 'H':     /* Double/even.  */
 2893:                   case 'J':     /* Quad/multiple of 4.  */
 2894:                     fregx (X_RD (insn));
 2895:                     break;
 2896: #undef  freg
 2897: #undef  fregx
 2898: 
 2899: #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
 2900:                   case 'b':
 2901:                     creg (X_RS1 (insn));
 2902:                     break;
 2903: 
 2904:                   case 'c':
 2905:                     creg (X_RS2 (insn));
 2906:                     break;
 2907: 
 2908:                   case 'D':
 2909:                     creg (X_RD (insn));
 2910:                     break;
 2911: #undef  creg
 2912: 
 2913:                   case 'h':
 2914:                     (*info->fprintf_func) (stream, "%%hi(%#x)",
 2915:                                            ((unsigned) 0xFFFFFFFF
 2916:                                             & ((int) X_IMM22 (insn) << 10)));
 2917:                     break;
 2918: 
 2919:                   case 'i':     /* 13 bit immediate.  */
 2920:                   case 'I':     /* 11 bit immediate.  */
 2921:                   case 'j':     /* 10 bit immediate.  */
 2922:                     {
 2923:                       int imm;
 2924: 
 2925:                       if (*s == 'i')
 2926:                         imm = X_SIMM (insn, 13);
 2927:                       else if (*s == 'I')
 2928:                         imm = X_SIMM (insn, 11);
 2929:                       else
 2930:                         imm = X_SIMM (insn, 10);
 2931: 
 2932:                       /* Check to see whether we have a 1+i, and take
 2933:                          note of that fact.
 2934: 
 2935:                          Note: because of the way we sort the table,
 2936:                          we will be matching 1+i rather than i+1,
 2937:                          so it is OK to assume that i is after +,
 2938:                          not before it.  */
 2939:                       if (found_plus)
 2940:                         imm_added_to_rs1 = 1;
 2941: 
 2942:                       if (imm <= 9)
 2943:                         (*info->fprintf_func) (stream, "%d", imm);
 2944:                       else
 2945:                         (*info->fprintf_func) (stream, "%#x", imm);
 2946:                     }
 2947:                     break;
 2948: 
 2949:                   case 'X':     /* 5 bit unsigned immediate.  */
 2950:                   case 'Y':     /* 6 bit unsigned immediate.  */
 2951:                     {
 2952:                       int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
 2953: 
 2954:                       if (imm <= 9)
 2955:                         (info->fprintf_func) (stream, "%d", imm);
 2956:                       else
 2957:                         (info->fprintf_func) (stream, "%#x", (unsigned) imm);
 2958:                     }
 2959:                     break;
 2960: 
 2961:                   case '3':
 2962:                     (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
 2963:                     break;
 2964: 
 2965:                   case 'K':
 2966:                     {
 2967:                       int mask = X_MEMBAR (insn);
 2968:                       int bit = 0x40, printed_one = 0;
 2969:                       const char *name;
 2970: 
 2971:                       if (mask == 0)
 2972:                         (info->fprintf_func) (stream, "0");
 2973:                       else
 2974:                         while (bit)
 2975:                           {
 2976:                             if (mask & bit)
 2977:                               {
 2978:                                 if (printed_one)
 2979:                                   (info->fprintf_func) (stream, "|");
 2980:                                 name = sparc_decode_membar (bit);
 2981:                                 (info->fprintf_func) (stream, "%s", name);
 2982:                                 printed_one = 1;
 2983:                               }
 2984:                             bit >>= 1;
 2985:                           }
 2986:                       break;
 2987:                     }
 2988: 
 2989:                   case 'k':
 2990:                     info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
 2991:                     (*info->print_address_func) (info->target, info);
 2992:                     break;
 2993: 
 2994:                   case 'G':
 2995:                     info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
 2996:                     (*info->print_address_func) (info->target, info);
 2997:                     break;
 2998: 
 2999:                   case '6':
 3000:                   case '7':
 3001:                   case '8':
 3002:                   case '9':
 3003:                     (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
 3004:                     break;
 3005: 
 3006:                   case 'z':
 3007:                     (*info->fprintf_func) (stream, "%%icc");
 3008:                     break;
 3009: 
 3010:                   case 'Z':
 3011:                     (*info->fprintf_func) (stream, "%%xcc");
 3012:                     break;
 3013: 
 3014:                   case 'E':
 3015:                     (*info->fprintf_func) (stream, "%%ccr");
 3016:                     break;
 3017: 
 3018:                   case 's':
 3019:                     (*info->fprintf_func) (stream, "%%fprs");
 3020:                     break;
 3021: 
 3022:                   case 'o':
 3023:                     (*info->fprintf_func) (stream, "%%asi");
 3024:                     break;
 3025: 
 3026:                   case 'W':
 3027:                     (*info->fprintf_func) (stream, "%%tick");
 3028:                     break;
 3029: 
 3030:                   case 'P':
 3031:                     (*info->fprintf_func) (stream, "%%pc");
 3032:                     break;
 3033: 
 3034:                   case '?':
 3035:                     if (X_RS1 (insn) == 31)
 3036:                       (*info->fprintf_func) (stream, "%%ver");
 3037:                     else if ((unsigned) X_RS1 (insn) < 17)
 3038:                       (*info->fprintf_func) (stream, "%%%s",
 3039:                                              v9_priv_reg_names[X_RS1 (insn)]);
 3040:                     else
 3041:                       (*info->fprintf_func) (stream, "%%reserved");
 3042:                     break;
 3043: 
 3044:                   case '!':
 3045:                     if ((unsigned) X_RD (insn) < 17)
 3046:                       (*info->fprintf_func) (stream, "%%%s",
 3047:                                              v9_priv_reg_names[X_RD (insn)]);
 3048:                     else
 3049:                       (*info->fprintf_func) (stream, "%%reserved");
 3050:                     break;
 3051: 
 3052:                   case '$':
 3053:                     if ((unsigned) X_RS1 (insn) < 32)
 3054:                       (*info->fprintf_func) (stream, "%%%s",
 3055:                                              v9_hpriv_reg_names[X_RS1 (insn)]);
 3056:                     else
 3057:                       (*info->fprintf_func) (stream, "%%reserved");
 3058:                     break;
 3059: 
 3060:                   case '%':
 3061:                     if ((unsigned) X_RD (insn) < 32)
 3062:                       (*info->fprintf_func) (stream, "%%%s",
 3063:                                              v9_hpriv_reg_names[X_RD (insn)]);
 3064:                     else
 3065:                       (*info->fprintf_func) (stream, "%%reserved");
 3066:                     break;
 3067: 
 3068:                   case '/':
 3069:                     if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
 3070:                       (*info->fprintf_func) (stream, "%%reserved");
 3071:                     else
 3072:                       (*info->fprintf_func) (stream, "%%%s",
 3073:                                              v9a_asr_reg_names[X_RS1 (insn)-16]);
 3074:                     break;
 3075: 
 3076:                   case '_':
 3077:                     if (X_RD (insn) < 16 || X_RD (insn) > 25)
 3078:                       (*info->fprintf_func) (stream, "%%reserved");
 3079:                     else
 3080:                       (*info->fprintf_func) (stream, "%%%s",
 3081:                                              v9a_asr_reg_names[X_RD (insn)-16]);
 3082:                     break;
 3083: 
 3084:                   case '*':
 3085:                     {
 3086:                       const char *name = sparc_decode_prefetch (X_RD (insn));
 3087: 
 3088:                       if (name)
 3089:                         (*info->fprintf_func) (stream, "%s", name);
 3090:                       else
 3091:                         (*info->fprintf_func) (stream, "%ld", X_RD (insn));
 3092:                       break;
 3093:                     }
 3094: 
 3095:                   case 'M':
 3096:                     (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
 3097:                     break;
 3098: 
 3099:                   case 'm':
 3100:                     (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
 3101:                     break;
 3102: 
 3103:                   case 'L':
 3104:                     info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
 3105:                     (*info->print_address_func) (info->target, info);
 3106:                     break;
 3107: 
 3108:                   case 'n':
 3109:                     (*info->fprintf_func)
 3110:                       (stream, "%#x", SEX (X_DISP22 (insn), 22));
 3111:                     break;
 3112: 
 3113:                   case 'l':
 3114:                     info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
 3115:                     (*info->print_address_func) (info->target, info);
 3116:                     break;
 3117: 
 3118:                   case 'A':
 3119:                     {
 3120:                       const char *name;
 3121: 
 3122:                       if ((info->mach == bfd_mach_sparc_v8plusa) ||
 3123:                           ((info->mach >= bfd_mach_sparc_v9) &&
 3124:                            (info->mach <= bfd_mach_sparc_v9b)))
 3125:                         name = sparc_decode_asi_v9 (X_ASI (insn));
 3126:                       else
 3127:                         name = sparc_decode_asi_v8 (X_ASI (insn));
 3128: 
 3129:                       if (name)
 3130:                         (*info->fprintf_func) (stream, "%s", name);
 3131:                       else
 3132:                         (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
 3133:                       break;
 3134:                     }
 3135: 
 3136:                   case 'C':
 3137:                     (*info->fprintf_func) (stream, "%%csr");
 3138:                     break;
 3139: 
 3140:                   case 'F':
 3141:                     (*info->fprintf_func) (stream, "%%fsr");
 3142:                     break;
 3143: 
 3144:                   case 'p':
 3145:                     (*info->fprintf_func) (stream, "%%psr");
 3146:                     break;
 3147: 
 3148:                   case 'q':
 3149:                     (*info->fprintf_func) (stream, "%%fq");
 3150:                     break;
 3151: 
 3152:                   case 'Q':
 3153:                     (*info->fprintf_func) (stream, "%%cq");
 3154:                     break;
 3155: 
 3156:                   case 't':
 3157:                     (*info->fprintf_func) (stream, "%%tbr");
 3158:                     break;
 3159: 
 3160:                   case 'w':
 3161:                     (*info->fprintf_func) (stream, "%%wim");
 3162:                     break;
 3163: 
 3164:                   case 'x':
 3165:                     (*info->fprintf_func) (stream, "%ld",
 3166:                                            ((X_LDST_I (insn) << 8)
 3167:                                             + X_ASI (insn)));
 3168:                     break;
 3169: 
 3170:                   case 'y':
 3171:                     (*info->fprintf_func) (stream, "%%y");
 3172:                     break;
 3173: 
 3174:                   case 'u':
 3175:                   case 'U':
 3176:                     {
 3177:                       int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
 3178:                       const char *name = sparc_decode_sparclet_cpreg (val);
 3179: 
 3180:                       if (name)
 3181:                         (*info->fprintf_func) (stream, "%s", name);
 3182:                       else
 3183:                         (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
 3184:                       break;
 3185:                     }
 3186:                   }
 3187:               }
 3188:           }
 3189: 
 3190:           /* If we are adding or or'ing something to rs1, then
 3191:              check to see whether the previous instruction was
 3192:              a sethi to the same register as in the sethi.
 3193:              If so, attempt to print the result of the add or
 3194:              or (in this context add and or do the same thing)
 3195:              and its symbolic value.  */
 3196:           if (imm_ored_to_rs1 || imm_added_to_rs1)
 3197:             {
 3198:               unsigned long prev_insn;
 3199:               int errcode;
 3200: 
 3201:               if (memaddr >= 4)
 3202:                 errcode =
 3203:                   (*info->read_memory_func)
 3204:                   (memaddr - 4, buffer, sizeof (buffer), info);
 3205:               else
 3206:                 errcode = 1;
 3207: 
 3208:               prev_insn = getword (buffer);
 3209: 
 3210:               if (errcode == 0)
 3211:                 {
 3212:                   /* If it is a delayed branch, we need to look at the
 3213:                      instruction before the delayed branch.  This handles
 3214:                      sequences such as:
 3215: 
 3216:                      sethi %o1, %hi(_foo), %o1
 3217:                      call _printf
 3218:                      or %o1, %lo(_foo), %o1  */
 3219: 
 3220:                   if (is_delayed_branch (prev_insn))
 3221:                     {
 3222:                       if (memaddr >= 8)
 3223:                         errcode = (*info->read_memory_func)
 3224:                           (memaddr - 8, buffer, sizeof (buffer), info);
 3225:                       else
 3226:                         errcode = 1;
 3227: 
 3228:                       prev_insn = getword (buffer);
 3229:                     }
 3230:                 }
 3231: 
 3232:               /* If there was a problem reading memory, then assume
 3233:                  the previous instruction was not sethi.  */
 3234:               if (errcode == 0)
 3235:                 {
 3236:                   /* Is it sethi to the same register?  */
 3237:                   if ((prev_insn & 0xc1c00000) == 0x01000000
 3238:                       && X_RD (prev_insn) == X_RS1 (insn))
 3239:                     {
 3240:                       (*info->fprintf_func) (stream, "\t! ");
 3241:                       info->target =
 3242:                         ((unsigned) 0xFFFFFFFF
 3243:                          & ((int) X_IMM22 (prev_insn) << 10));
 3244:                       if (imm_added_to_rs1)
 3245:                         info->target += X_SIMM (insn, 13);
 3246:                       else
 3247:                         info->target |= X_SIMM (insn, 13);
 3248:                       (*info->print_address_func) (info->target, info);
 3249:                       info->insn_type = dis_dref;
 3250:                       info->data_size = 4;  /* FIXME!!! */
 3251:                     }
 3252:                 }
 3253:             }
 3254: 
 3255:           if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
 3256:             {
 3257:                 /* FIXME -- check is_annulled flag.  */
 3258:               if (opcode->flags & F_UNBR)
 3259:                 info->insn_type = dis_branch;
 3260:               if (opcode->flags & F_CONDBR)
 3261:                 info->insn_type = dis_condbranch;
 3262:               if (opcode->flags & F_JSR)
 3263:                 info->insn_type = dis_jsr;
 3264:               if (opcode->flags & F_DELAYED)
 3265:                 info->branch_delay_insns = 1;
 3266:             }
 3267: 
 3268:           return sizeof (buffer);
 3269:         }
 3270:     }
 3271: 
 3272:   info->insn_type = dis_noninsn;        /* Mark as non-valid instruction.  */
 3273:   (*info->fprintf_func) (stream, _("unknown"));
 3274:   return sizeof (buffer);
 3275: }

unix.superglobalmegacorp.com