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1.1 root 1: /*
2: * Alpha emulation cpu definitions for qemu.
3: *
4: * Copyright (c) 2007 Jocelyn Mayer
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.3 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19:
20: #if !defined (__CPU_ALPHA_H__)
21: #define __CPU_ALPHA_H__
22:
23: #include "config.h"
24:
25: #define TARGET_LONG_BITS 64
26:
1.1.1.3 root 27: #define CPUState struct CPUAlphaState
28:
1.1 root 29: #include "cpu-defs.h"
30:
31: #include <setjmp.h>
32:
33: #include "softfloat.h"
34:
35: #define TARGET_HAS_ICE 1
36:
37: #define ELF_MACHINE EM_ALPHA
38:
39: #define ICACHE_LINE_SIZE 32
40: #define DCACHE_LINE_SIZE 32
41:
1.1.1.3 root 42: #define TARGET_PAGE_BITS 13
1.1 root 43:
1.1.1.5 ! root 44: /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
! 45: #define TARGET_PHYS_ADDR_SPACE_BITS 44
! 46: #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
1.1 root 47:
48: /* Alpha major type */
49: enum {
50: ALPHA_EV3 = 1,
51: ALPHA_EV4 = 2,
52: ALPHA_SIM = 3,
53: ALPHA_LCA = 4,
54: ALPHA_EV5 = 5, /* 21164 */
55: ALPHA_EV45 = 6, /* 21064A */
56: ALPHA_EV56 = 7, /* 21164A */
57: };
58:
59: /* EV4 minor type */
60: enum {
61: ALPHA_EV4_2 = 0,
62: ALPHA_EV4_3 = 1,
63: };
64:
65: /* LCA minor type */
66: enum {
67: ALPHA_LCA_1 = 1, /* 21066 */
68: ALPHA_LCA_2 = 2, /* 20166 */
69: ALPHA_LCA_3 = 3, /* 21068 */
70: ALPHA_LCA_4 = 4, /* 21068 */
71: ALPHA_LCA_5 = 5, /* 21066A */
72: ALPHA_LCA_6 = 6, /* 21068A */
73: };
74:
75: /* EV5 minor type */
76: enum {
77: ALPHA_EV5_1 = 1, /* Rev BA, CA */
78: ALPHA_EV5_2 = 2, /* Rev DA, EA */
79: ALPHA_EV5_3 = 3, /* Pass 3 */
80: ALPHA_EV5_4 = 4, /* Pass 3.2 */
81: ALPHA_EV5_5 = 5, /* Pass 4 */
82: };
83:
84: /* EV45 minor type */
85: enum {
86: ALPHA_EV45_1 = 1, /* Pass 1 */
87: ALPHA_EV45_2 = 2, /* Pass 1.1 */
88: ALPHA_EV45_3 = 3, /* Pass 2 */
89: };
90:
91: /* EV56 minor type */
92: enum {
93: ALPHA_EV56_1 = 1, /* Pass 1 */
94: ALPHA_EV56_2 = 2, /* Pass 2 */
95: };
96:
97: enum {
98: IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
99: IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
100: IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
101: IMPLVER_21364 = 3, /* EV7 & EV79 */
102: };
103:
104: enum {
105: AMASK_BWX = 0x00000001,
106: AMASK_FIX = 0x00000002,
107: AMASK_CIX = 0x00000004,
108: AMASK_MVI = 0x00000100,
109: AMASK_TRAP = 0x00000200,
110: AMASK_PREFETCH = 0x00001000,
111: };
112:
113: enum {
114: VAX_ROUND_NORMAL = 0,
115: VAX_ROUND_CHOPPED,
116: };
117:
118: enum {
119: IEEE_ROUND_NORMAL = 0,
120: IEEE_ROUND_DYNAMIC,
121: IEEE_ROUND_PLUS,
122: IEEE_ROUND_MINUS,
123: IEEE_ROUND_CHOPPED,
124: };
125:
126: /* IEEE floating-point operations encoding */
127: /* Trap mode */
128: enum {
129: FP_TRAP_I = 0x0,
130: FP_TRAP_U = 0x1,
131: FP_TRAP_S = 0x4,
132: FP_TRAP_SU = 0x5,
133: FP_TRAP_SUI = 0x7,
134: };
135:
136: /* Rounding mode */
137: enum {
138: FP_ROUND_CHOPPED = 0x0,
139: FP_ROUND_MINUS = 0x1,
140: FP_ROUND_NORMAL = 0x2,
141: FP_ROUND_DYNAMIC = 0x3,
142: };
143:
1.1.1.5 ! root 144: /* FPCR bits */
! 145: #define FPCR_SUM (1ULL << 63)
! 146: #define FPCR_INED (1ULL << 62)
! 147: #define FPCR_UNFD (1ULL << 61)
! 148: #define FPCR_UNDZ (1ULL << 60)
! 149: #define FPCR_DYN_SHIFT 58
! 150: #define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT)
! 151: #define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT)
! 152: #define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT)
! 153: #define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT)
! 154: #define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT)
! 155: #define FPCR_IOV (1ULL << 57)
! 156: #define FPCR_INE (1ULL << 56)
! 157: #define FPCR_UNF (1ULL << 55)
! 158: #define FPCR_OVF (1ULL << 54)
! 159: #define FPCR_DZE (1ULL << 53)
! 160: #define FPCR_INV (1ULL << 52)
! 161: #define FPCR_OVFD (1ULL << 51)
! 162: #define FPCR_DZED (1ULL << 50)
! 163: #define FPCR_INVD (1ULL << 49)
! 164: #define FPCR_DNZ (1ULL << 48)
! 165: #define FPCR_DNOD (1ULL << 47)
! 166: #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
! 167: | FPCR_OVF | FPCR_DZE | FPCR_INV)
! 168:
! 169: /* The silly software trap enables implemented by the kernel emulation.
! 170: These are more or less architecturally required, since the real hardware
! 171: has read-as-zero bits in the FPCR when the features aren't implemented.
! 172: For the purposes of QEMU, we pretend the FPCR can hold everything. */
! 173: #define SWCR_TRAP_ENABLE_INV (1ULL << 1)
! 174: #define SWCR_TRAP_ENABLE_DZE (1ULL << 2)
! 175: #define SWCR_TRAP_ENABLE_OVF (1ULL << 3)
! 176: #define SWCR_TRAP_ENABLE_UNF (1ULL << 4)
! 177: #define SWCR_TRAP_ENABLE_INE (1ULL << 5)
! 178: #define SWCR_TRAP_ENABLE_DNO (1ULL << 6)
! 179: #define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1))
! 180:
! 181: #define SWCR_MAP_DMZ (1ULL << 12)
! 182: #define SWCR_MAP_UMZ (1ULL << 13)
! 183: #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
! 184:
! 185: #define SWCR_STATUS_INV (1ULL << 17)
! 186: #define SWCR_STATUS_DZE (1ULL << 18)
! 187: #define SWCR_STATUS_OVF (1ULL << 19)
! 188: #define SWCR_STATUS_UNF (1ULL << 20)
! 189: #define SWCR_STATUS_INE (1ULL << 21)
! 190: #define SWCR_STATUS_DNO (1ULL << 22)
! 191: #define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17))
! 192:
! 193: #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
! 194:
1.1 root 195: /* Internal processor registers */
196: /* XXX: TOFIX: most of those registers are implementation dependant */
197: enum {
1.1.1.5 ! root 198: #if defined(CONFIG_USER_ONLY)
! 199: IPR_EXC_ADDR,
! 200: IPR_EXC_SUM,
! 201: IPR_EXC_MASK,
! 202: #else
1.1 root 203: /* Ebox IPRs */
1.1.1.3 root 204: IPR_CC = 0xC0, /* 21264 */
205: IPR_CC_CTL = 0xC1, /* 21264 */
206: #define IPR_CC_CTL_ENA_SHIFT 32
207: #define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL
208: IPR_VA = 0xC2, /* 21264 */
209: IPR_VA_CTL = 0xC4, /* 21264 */
210: #define IPR_VA_CTL_VA_48_SHIFT 1
211: #define IPR_VA_CTL_VPTB_SHIFT 30
212: IPR_VA_FORM = 0xC3, /* 21264 */
1.1 root 213: /* Ibox IPRs */
1.1.1.3 root 214: IPR_ITB_TAG = 0x00, /* 21264 */
215: IPR_ITB_PTE = 0x01, /* 21264 */
216: IPR_ITB_IAP = 0x02,
217: IPR_ITB_IA = 0x03, /* 21264 */
218: IPR_ITB_IS = 0x04, /* 21264 */
1.1 root 219: IPR_PMPC = 0x05,
1.1.1.3 root 220: IPR_EXC_ADDR = 0x06, /* 21264 */
221: IPR_IVA_FORM = 0x07, /* 21264 */
222: IPR_CM = 0x09, /* 21264 */
223: #define IPR_CM_SHIFT 3
224: #define IPR_CM_MASK (3ULL << IPR_CM_SHIFT) /* 21264 */
225: IPR_IER = 0x0A, /* 21264 */
226: #define IPR_IER_MASK 0x0000007fffffe000ULL
227: IPR_IER_CM = 0x0B, /* 21264: = CM | IER */
228: IPR_SIRR = 0x0C, /* 21264 */
229: #define IPR_SIRR_SHIFT 14
230: #define IPR_SIRR_MASK 0x7fff
231: IPR_ISUM = 0x0D, /* 21264 */
232: IPR_HW_INT_CLR = 0x0E, /* 21264 */
1.1 root 233: IPR_EXC_SUM = 0x0F,
234: IPR_PAL_BASE = 0x10,
235: IPR_I_CTL = 0x11,
1.1.1.3 root 236: #define IPR_I_CTL_CHIP_ID_SHIFT 24 /* 21264 */
237: #define IPR_I_CTL_BIST_FAIL (1 << 23) /* 21264 */
238: #define IPR_I_CTL_IC_EN_SHIFT 2 /* 21264 */
239: #define IPR_I_CTL_SDE1_SHIFT 7 /* 21264 */
240: #define IPR_I_CTL_HWE_SHIFT 12 /* 21264 */
241: #define IPR_I_CTL_VA_48_SHIFT 15 /* 21264 */
242: #define IPR_I_CTL_SPE_SHIFT 3 /* 21264 */
243: #define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */
244: IPR_I_STAT = 0x16, /* 21264 */
245: IPR_IC_FLUSH = 0x13, /* 21264 */
246: IPR_IC_FLUSH_ASM = 0x12, /* 21264 */
1.1 root 247: IPR_CLR_MAP = 0x15,
248: IPR_SLEEP = 0x17,
249: IPR_PCTX = 0x40,
1.1.1.3 root 250: IPR_PCTX_ASN = 0x01, /* field */
251: #define IPR_PCTX_ASN_SHIFT 39
252: IPR_PCTX_ASTER = 0x02, /* field */
253: #define IPR_PCTX_ASTER_SHIFT 5
254: IPR_PCTX_ASTRR = 0x04, /* field */
255: #define IPR_PCTX_ASTRR_SHIFT 9
256: IPR_PCTX_PPCE = 0x08, /* field */
257: #define IPR_PCTX_PPCE_SHIFT 1
258: IPR_PCTX_FPE = 0x10, /* field */
259: #define IPR_PCTX_FPE_SHIFT 2
260: IPR_PCTX_ALL = 0x5f, /* all fields */
261: IPR_PCTR_CTL = 0x14, /* 21264 */
1.1 root 262: /* Mbox IPRs */
1.1.1.3 root 263: IPR_DTB_TAG0 = 0x20, /* 21264 */
264: IPR_DTB_TAG1 = 0xA0, /* 21264 */
265: IPR_DTB_PTE0 = 0x21, /* 21264 */
266: IPR_DTB_PTE1 = 0xA1, /* 21264 */
1.1 root 267: IPR_DTB_ALTMODE = 0xA6,
1.1.1.3 root 268: IPR_DTB_ALTMODE0 = 0x26, /* 21264 */
269: #define IPR_DTB_ALTMODE_MASK 3
1.1 root 270: IPR_DTB_IAP = 0xA2,
1.1.1.3 root 271: IPR_DTB_IA = 0xA3, /* 21264 */
1.1 root 272: IPR_DTB_IS0 = 0x24,
273: IPR_DTB_IS1 = 0xA4,
1.1.1.3 root 274: IPR_DTB_ASN0 = 0x25, /* 21264 */
275: IPR_DTB_ASN1 = 0xA5, /* 21264 */
276: #define IPR_DTB_ASN_SHIFT 56
277: IPR_MM_STAT = 0x27, /* 21264 */
278: IPR_M_CTL = 0x28, /* 21264 */
279: #define IPR_M_CTL_SPE_SHIFT 1
280: #define IPR_M_CTL_SPE_MASK 7
281: IPR_DC_CTL = 0x29, /* 21264 */
282: IPR_DC_STAT = 0x2A, /* 21264 */
1.1 root 283: /* Cbox IPRs */
284: IPR_C_DATA = 0x2B,
285: IPR_C_SHIFT = 0x2C,
286:
287: IPR_ASN,
288: IPR_ASTEN,
289: IPR_ASTSR,
290: IPR_DATFX,
291: IPR_ESP,
292: IPR_FEN,
293: IPR_IPIR,
294: IPR_IPL,
295: IPR_KSP,
296: IPR_MCES,
297: IPR_PERFMON,
298: IPR_PCBB,
299: IPR_PRBR,
300: IPR_PTBR,
301: IPR_SCBB,
302: IPR_SISR,
303: IPR_SSP,
304: IPR_SYSPTBR,
305: IPR_TBCHK,
306: IPR_TBIA,
307: IPR_TBIAP,
308: IPR_TBIS,
309: IPR_TBISD,
310: IPR_TBISI,
311: IPR_USP,
312: IPR_VIRBND,
313: IPR_VPTB,
314: IPR_WHAMI,
315: IPR_ALT_MODE,
1.1.1.5 ! root 316: #endif
1.1 root 317: IPR_LAST,
318: };
319:
320: typedef struct CPUAlphaState CPUAlphaState;
321:
322: typedef struct pal_handler_t pal_handler_t;
323: struct pal_handler_t {
324: /* Reset */
325: void (*reset)(CPUAlphaState *env);
326: /* Uncorrectable hardware error */
327: void (*machine_check)(CPUAlphaState *env);
328: /* Arithmetic exception */
329: void (*arithmetic)(CPUAlphaState *env);
330: /* Interrupt / correctable hardware error */
331: void (*interrupt)(CPUAlphaState *env);
332: /* Data fault */
333: void (*dfault)(CPUAlphaState *env);
334: /* DTB miss pal */
335: void (*dtb_miss_pal)(CPUAlphaState *env);
336: /* DTB miss native */
337: void (*dtb_miss_native)(CPUAlphaState *env);
338: /* Unaligned access */
339: void (*unalign)(CPUAlphaState *env);
340: /* ITB miss */
341: void (*itb_miss)(CPUAlphaState *env);
342: /* Instruction stream access violation */
343: void (*itb_acv)(CPUAlphaState *env);
344: /* Reserved or privileged opcode */
345: void (*opcdec)(CPUAlphaState *env);
346: /* Floating point exception */
347: void (*fen)(CPUAlphaState *env);
348: /* Call pal instruction */
349: void (*call_pal)(CPUAlphaState *env, uint32_t palcode);
350: };
351:
352: #define NB_MMU_MODES 4
353:
354: struct CPUAlphaState {
355: uint64_t ir[31];
1.1.1.5 ! root 356: float64 fir[31];
1.1 root 357: uint64_t pc;
358: uint64_t ipr[IPR_LAST];
359: uint64_t ps;
360: uint64_t unique;
1.1.1.5 ! root 361: uint64_t lock_addr;
! 362: uint64_t lock_st_addr;
! 363: uint64_t lock_value;
! 364: float_status fp_status;
! 365: /* The following fields make up the FPCR, but in FP_STATUS format. */
! 366: uint8_t fpcr_exc_status;
! 367: uint8_t fpcr_exc_mask;
! 368: uint8_t fpcr_dyn_round;
! 369: uint8_t fpcr_flush_to_zero;
! 370: uint8_t fpcr_dnz;
! 371: uint8_t fpcr_dnod;
! 372: uint8_t fpcr_undz;
! 373:
! 374: /* Used for HW_LD / HW_ST */
! 375: uint8_t saved_mode;
! 376: /* For RC and RS */
! 377: uint8_t intr_flag;
1.1 root 378:
379: #if TARGET_LONG_BITS > HOST_LONG_BITS
380: /* temporary fixed-point registers
381: * used to emulate 64 bits target on 32 bits hosts
382: */
1.1.1.2 root 383: target_ulong t0, t1;
1.1 root 384: #endif
385:
386: /* Those resources are used only in Qemu core */
387: CPU_COMMON
388:
389: uint32_t hflags;
390:
391: int error_code;
392:
393: uint32_t features;
394: uint32_t amask;
395: int implver;
396: pal_handler_t *pal_handler;
397: };
398:
399: #define cpu_init cpu_alpha_init
400: #define cpu_exec cpu_alpha_exec
401: #define cpu_gen_code cpu_alpha_gen_code
402: #define cpu_signal_handler cpu_alpha_signal_handler
403:
404: /* MMU modes definitions */
405: #define MMU_MODE0_SUFFIX _kernel
406: #define MMU_MODE1_SUFFIX _executive
407: #define MMU_MODE2_SUFFIX _supervisor
408: #define MMU_MODE3_SUFFIX _user
409: #define MMU_USER_IDX 3
410: static inline int cpu_mmu_index (CPUState *env)
411: {
412: return (env->ps >> 3) & 3;
413: }
414:
415: #include "cpu-all.h"
416:
417: enum {
418: FEATURE_ASN = 0x00000001,
419: FEATURE_SPS = 0x00000002,
420: FEATURE_VIRBND = 0x00000004,
421: FEATURE_TBCHK = 0x00000008,
422: };
423:
424: enum {
425: EXCP_RESET = 0x0000,
426: EXCP_MCHK = 0x0020,
427: EXCP_ARITH = 0x0060,
428: EXCP_HW_INTERRUPT = 0x00E0,
429: EXCP_DFAULT = 0x01E0,
430: EXCP_DTB_MISS_PAL = 0x09E0,
431: EXCP_ITB_MISS = 0x03E0,
432: EXCP_ITB_ACV = 0x07E0,
433: EXCP_DTB_MISS_NATIVE = 0x08E0,
434: EXCP_UNALIGN = 0x11E0,
435: EXCP_OPCDEC = 0x13E0,
436: EXCP_FEN = 0x17E0,
437: EXCP_CALL_PAL = 0x2000,
438: EXCP_CALL_PALP = 0x3000,
439: EXCP_CALL_PALE = 0x4000,
440: /* Pseudo exception for console */
441: EXCP_CONSOLE_DISPATCH = 0x4001,
442: EXCP_CONSOLE_FIXUP = 0x4002,
1.1.1.5 ! root 443: EXCP_STL_C = 0x4003,
! 444: EXCP_STQ_C = 0x4004,
1.1 root 445: };
446:
447: /* Arithmetic exception */
1.1.1.5 ! root 448: #define EXC_M_IOV (1<<16) /* Integer Overflow */
! 449: #define EXC_M_INE (1<<15) /* Inexact result */
! 450: #define EXC_M_UNF (1<<14) /* Underflow */
! 451: #define EXC_M_FOV (1<<13) /* Overflow */
! 452: #define EXC_M_DZE (1<<12) /* Division by zero */
! 453: #define EXC_M_INV (1<<11) /* Invalid operation */
! 454: #define EXC_M_SWC (1<<10) /* Software completion */
1.1 root 455:
456: enum {
457: IR_V0 = 0,
458: IR_T0 = 1,
459: IR_T1 = 2,
460: IR_T2 = 3,
461: IR_T3 = 4,
462: IR_T4 = 5,
463: IR_T5 = 6,
464: IR_T6 = 7,
465: IR_T7 = 8,
466: IR_S0 = 9,
467: IR_S1 = 10,
468: IR_S2 = 11,
469: IR_S3 = 12,
470: IR_S4 = 13,
471: IR_S5 = 14,
472: IR_S6 = 15,
1.1.1.5 ! root 473: IR_FP = IR_S6,
1.1 root 474: IR_A0 = 16,
475: IR_A1 = 17,
476: IR_A2 = 18,
477: IR_A3 = 19,
478: IR_A4 = 20,
479: IR_A5 = 21,
480: IR_T8 = 22,
481: IR_T9 = 23,
482: IR_T10 = 24,
483: IR_T11 = 25,
484: IR_RA = 26,
485: IR_T12 = 27,
1.1.1.5 ! root 486: IR_PV = IR_T12,
1.1 root 487: IR_AT = 28,
488: IR_GP = 29,
489: IR_SP = 30,
490: IR_ZERO = 31,
491: };
492:
493: CPUAlphaState * cpu_alpha_init (const char *cpu_model);
494: int cpu_alpha_exec(CPUAlphaState *s);
495: /* you can call this signal handler from your SIGBUS and SIGSEGV
496: signal handlers to inform the virtual CPU of exceptions. non zero
497: is returned if the signal was handled by the virtual CPU. */
498: int cpu_alpha_signal_handler(int host_signum, void *pinfo,
499: void *puc);
1.1.1.2 root 500: int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,
501: int mmu_idx, int is_softmmu);
1.1.1.4 root 502: #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
1.1.1.2 root 503: void do_interrupt (CPUState *env);
504:
1.1.1.5 ! root 505: uint64_t cpu_alpha_load_fpcr (CPUState *env);
! 506: void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
1.1 root 507: int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);
508: int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
1.1.1.2 root 509: #if !defined (CONFIG_USER_ONLY)
1.1.1.5 ! root 510: void pal_init (CPUState *env);
1.1.1.2 root 511: void call_pal (CPUState *env);
512: #endif
513:
514: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
515: target_ulong *cs_base, int *flags)
516: {
517: *pc = env->pc;
518: *cs_base = 0;
519: *flags = env->ps;
520: }
1.1 root 521:
1.1.1.5 ! root 522: #if defined(CONFIG_USER_ONLY)
! 523: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
! 524: {
! 525: if (newsp) {
! 526: env->ir[IR_SP] = newsp;
! 527: }
! 528: env->ir[IR_V0] = 0;
! 529: env->ir[IR_A3] = 0;
! 530: }
! 531:
! 532: static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
! 533: {
! 534: env->unique = newtls;
! 535: }
! 536: #endif
! 537:
1.1 root 538: #endif /* !defined (__CPU_ALPHA_H__) */
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