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Annotation of qemu/target-arm/cpu-qom.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * QEMU ARM CPU
        !             3:  *
        !             4:  * Copyright (c) 2012 SUSE LINUX Products GmbH
        !             5:  *
        !             6:  * This program is free software; you can redistribute it and/or
        !             7:  * modify it under the terms of the GNU General Public License
        !             8:  * as published by the Free Software Foundation; either version 2
        !             9:  * of the License, or (at your option) any later version.
        !            10:  *
        !            11:  * This program is distributed in the hope that it will be useful,
        !            12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
        !            13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
        !            14:  * GNU General Public License for more details.
        !            15:  *
        !            16:  * You should have received a copy of the GNU General Public License
        !            17:  * along with this program; if not, see
        !            18:  * <http://www.gnu.org/licenses/gpl-2.0.html>
        !            19:  */
        !            20: #ifndef QEMU_ARM_CPU_QOM_H
        !            21: #define QEMU_ARM_CPU_QOM_H
        !            22: 
        !            23: #include "qemu/cpu.h"
        !            24: 
        !            25: #define TYPE_ARM_CPU "arm-cpu"
        !            26: 
        !            27: #define ARM_CPU_CLASS(klass) \
        !            28:     OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
        !            29: #define ARM_CPU(obj) \
        !            30:     OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
        !            31: #define ARM_CPU_GET_CLASS(obj) \
        !            32:     OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
        !            33: 
        !            34: /**
        !            35:  * ARMCPUClass:
        !            36:  * @parent_reset: The parent class' reset handler.
        !            37:  *
        !            38:  * An ARM CPU model.
        !            39:  */
        !            40: typedef struct ARMCPUClass {
        !            41:     /*< private >*/
        !            42:     CPUClass parent_class;
        !            43:     /*< public >*/
        !            44: 
        !            45:     void (*parent_reset)(CPUState *cpu);
        !            46: } ARMCPUClass;
        !            47: 
        !            48: /**
        !            49:  * ARMCPU:
        !            50:  * @env: #CPUARMState
        !            51:  *
        !            52:  * An ARM CPU core.
        !            53:  */
        !            54: typedef struct ARMCPU {
        !            55:     /*< private >*/
        !            56:     CPUState parent_obj;
        !            57:     /*< public >*/
        !            58: 
        !            59:     CPUARMState env;
        !            60: 
        !            61:     /* The instance init functions for implementation-specific subclasses
        !            62:      * set these fields to specify the implementation-dependent values of
        !            63:      * various constant registers and reset values of non-constant
        !            64:      * registers.
        !            65:      * Some of these might become QOM properties eventually.
        !            66:      * Field names match the official register names as defined in the
        !            67:      * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
        !            68:      * is used for reset values of non-constant registers; no reset_
        !            69:      * prefix means a constant register.
        !            70:      */
        !            71:     uint32_t midr;
        !            72:     uint32_t reset_fpsid;
        !            73:     uint32_t mvfr0;
        !            74:     uint32_t mvfr1;
        !            75:     uint32_t ctr;
        !            76:     uint32_t reset_sctlr;
        !            77:     uint32_t id_pfr0;
        !            78:     uint32_t id_pfr1;
        !            79:     uint32_t id_dfr0;
        !            80:     uint32_t id_afr0;
        !            81:     uint32_t id_mmfr0;
        !            82:     uint32_t id_mmfr1;
        !            83:     uint32_t id_mmfr2;
        !            84:     uint32_t id_mmfr3;
        !            85:     uint32_t id_isar0;
        !            86:     uint32_t id_isar1;
        !            87:     uint32_t id_isar2;
        !            88:     uint32_t id_isar3;
        !            89:     uint32_t id_isar4;
        !            90:     uint32_t id_isar5;
        !            91:     uint32_t clidr;
        !            92:     /* The elements of this array are the CCSIDR values for each cache,
        !            93:      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
        !            94:      */
        !            95:     uint32_t ccsidr[16];
        !            96:     uint32_t reset_cbar;
        !            97: } ARMCPU;
        !            98: 
        !            99: static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
        !           100: {
        !           101:     return ARM_CPU(container_of(env, ARMCPU, env));
        !           102: }
        !           103: 
        !           104: #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
        !           105: 
        !           106: void arm_cpu_realize(ARMCPU *cpu);
        !           107: 
        !           108: #endif

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