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1.1 ! root 1: /* ! 2: * ARM virtual CPU header ! 3: * ! 4: * Copyright (c) 2003 Fabrice Bellard ! 5: * ! 6: * This library is free software; you can redistribute it and/or ! 7: * modify it under the terms of the GNU Lesser General Public ! 8: * License as published by the Free Software Foundation; either ! 9: * version 2 of the License, or (at your option) any later version. ! 10: * ! 11: * This library is distributed in the hope that it will be useful, ! 12: * but WITHOUT ANY WARRANTY; without even the implied warranty of ! 13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ! 14: * Lesser General Public License for more details. ! 15: * ! 16: * You should have received a copy of the GNU Lesser General Public ! 17: * License along with this library; if not, write to the Free Software ! 18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ! 19: */ ! 20: #ifndef CPU_ARM_H ! 21: #define CPU_ARM_H ! 22: ! 23: #define TARGET_LONG_BITS 32 ! 24: ! 25: #include "cpu-defs.h" ! 26: ! 27: #include "softfloat.h" ! 28: ! 29: #define TARGET_HAS_ICE 1 ! 30: ! 31: #define EXCP_UDEF 1 /* undefined instruction */ ! 32: #define EXCP_SWI 2 /* software interrupt */ ! 33: #define EXCP_PREFETCH_ABORT 3 ! 34: #define EXCP_DATA_ABORT 4 ! 35: ! 36: /* We currently assume float and double are IEEE single and double ! 37: precision respectively. ! 38: Doing runtime conversions is tricky because VFP registers may contain ! 39: integer values (eg. as the result of a FTOSI instruction). ! 40: s<2n> maps to the least significant half of d<n> ! 41: s<2n+1> maps to the most significant half of d<n> ! 42: */ ! 43: ! 44: typedef struct CPUARMState { ! 45: uint32_t regs[16]; ! 46: uint32_t cpsr; ! 47: ! 48: /* cpsr flag cache for faster execution */ ! 49: uint32_t CF; /* 0 or 1 */ ! 50: uint32_t VF; /* V is the bit 31. All other bits are undefined */ ! 51: uint32_t NZF; /* N is bit 31. Z is computed from NZF */ ! 52: uint32_t QF; /* 0 or 1 */ ! 53: ! 54: int thumb; /* 0 = arm mode, 1 = thumb mode */ ! 55: ! 56: /* coprocessor 15 (MMU) status */ ! 57: uint32_t cp15_6; ! 58: ! 59: /* exception/interrupt handling */ ! 60: jmp_buf jmp_env; ! 61: int exception_index; ! 62: int interrupt_request; ! 63: struct TranslationBlock *current_tb; ! 64: int user_mode_only; ! 65: uint32_t address; ! 66: ! 67: /* ICE debug support. */ ! 68: target_ulong breakpoints[MAX_BREAKPOINTS]; ! 69: int nb_breakpoints; ! 70: int singlestep_enabled; ! 71: ! 72: /* in order to avoid passing too many arguments to the memory ! 73: write helpers, we store some rarely used information in the CPU ! 74: context) */ ! 75: unsigned long mem_write_pc; /* host pc at which the memory was ! 76: written */ ! 77: unsigned long mem_write_vaddr; /* target virtual addr at which the ! 78: memory was written */ ! 79: /* VFP coprocessor state. */ ! 80: struct { ! 81: float64 regs[16]; ! 82: ! 83: /* We store these fpcsr fields separately for convenience. */ ! 84: int vec_len; ! 85: int vec_stride; ! 86: ! 87: uint32_t fpscr; ! 88: ! 89: /* Temporary variables if we don't have spare fp regs. */ ! 90: float32 tmp0s, tmp1s; ! 91: float64 tmp0d, tmp1d; ! 92: ! 93: float_status fp_status; ! 94: } vfp; ! 95: ! 96: /* user data */ ! 97: void *opaque; ! 98: } CPUARMState; ! 99: ! 100: CPUARMState *cpu_arm_init(void); ! 101: int cpu_arm_exec(CPUARMState *s); ! 102: void cpu_arm_close(CPUARMState *s); ! 103: /* you can call this signal handler from your SIGBUS and SIGSEGV ! 104: signal handlers to inform the virtual CPU of exceptions. non zero ! 105: is returned if the signal was handled by the virtual CPU. */ ! 106: struct siginfo; ! 107: int cpu_arm_signal_handler(int host_signum, struct siginfo *info, ! 108: void *puc); ! 109: ! 110: #define TARGET_PAGE_BITS 12 ! 111: #include "cpu-all.h" ! 112: ! 113: #endif
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