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1.1 root 1: /*
2: * ARM virtual CPU header
1.1.1.5 root 3: *
1.1 root 4: * Copyright (c) 2003 Fabrice Bellard
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.7 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #ifndef CPU_ARM_H
20: #define CPU_ARM_H
21:
22: #define TARGET_LONG_BITS 32
23:
1.1.1.4 root 24: #define ELF_MACHINE EM_ARM
25:
1.1.1.7 root 26: #define CPUState struct CPUARMState
27:
1.1.1.10! root 28: #include "config.h"
! 29: #include "qemu-common.h"
1.1 root 30: #include "cpu-defs.h"
31:
32: #include "softfloat.h"
33:
34: #define TARGET_HAS_ICE 1
35:
36: #define EXCP_UDEF 1 /* undefined instruction */
37: #define EXCP_SWI 2 /* software interrupt */
38: #define EXCP_PREFETCH_ABORT 3
39: #define EXCP_DATA_ABORT 4
1.1.1.2 root 40: #define EXCP_IRQ 5
41: #define EXCP_FIQ 6
1.1.1.3 root 42: #define EXCP_BKPT 7
1.1.1.5 root 43: #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
1.1.1.6 root 44: #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
1.1.1.8 root 45: #define EXCP_STREX 10
1.1.1.5 root 46:
47: #define ARMV7M_EXCP_RESET 1
48: #define ARMV7M_EXCP_NMI 2
49: #define ARMV7M_EXCP_HARD 3
50: #define ARMV7M_EXCP_MEM 4
51: #define ARMV7M_EXCP_BUS 5
52: #define ARMV7M_EXCP_USAGE 6
53: #define ARMV7M_EXCP_SVC 11
54: #define ARMV7M_EXCP_DEBUG 12
55: #define ARMV7M_EXCP_PENDSV 14
56: #define ARMV7M_EXCP_SYSTICK 15
57:
58: typedef void ARMWriteCPFunc(void *opaque, int cp_info,
59: int srcreg, int operand, uint32_t value);
60: typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
61: int dstreg, int operand);
62:
1.1.1.6 root 63: struct arm_boot_info;
64:
1.1.1.5 root 65: #define NB_MMU_MODES 2
1.1 root 66:
67: /* We currently assume float and double are IEEE single and double
68: precision respectively.
69: Doing runtime conversions is tricky because VFP registers may contain
70: integer values (eg. as the result of a FTOSI instruction).
71: s<2n> maps to the least significant half of d<n>
72: s<2n+1> maps to the most significant half of d<n>
73: */
74:
75: typedef struct CPUARMState {
1.1.1.2 root 76: /* Regs for current mode. */
1.1 root 77: uint32_t regs[16];
1.1.1.2 root 78: /* Frequently accessed CPSR bits are stored separately for efficiently.
1.1.1.4 root 79: This contains all the other bits. Use cpsr_{read,write} to access
1.1.1.2 root 80: the whole CPSR. */
81: uint32_t uncached_cpsr;
82: uint32_t spsr;
83:
84: /* Banked registers. */
85: uint32_t banked_spsr[6];
86: uint32_t banked_r13[6];
87: uint32_t banked_r14[6];
1.1.1.5 root 88:
1.1.1.2 root 89: /* These hold r8-r12. */
90: uint32_t usr_regs[5];
91: uint32_t fiq_regs[5];
1.1.1.5 root 92:
1.1 root 93: /* cpsr flag cache for faster execution */
94: uint32_t CF; /* 0 or 1 */
95: uint32_t VF; /* V is the bit 31. All other bits are undefined */
1.1.1.6 root 96: uint32_t NF; /* N is bit 31. All other bits are undefined. */
97: uint32_t ZF; /* Z set if zero. */
1.1 root 98: uint32_t QF; /* 0 or 1 */
1.1.1.5 root 99: uint32_t GE; /* cpsr[19:16] */
1.1.1.6 root 100: uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
1.1.1.5 root 101: uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
1.1 root 102:
1.1.1.2 root 103: /* System control coprocessor (cp15) */
104: struct {
1.1.1.3 root 105: uint32_t c0_cpuid;
1.1.1.5 root 106: uint32_t c0_cachetype;
1.1.1.6 root 107: uint32_t c0_ccsid[16]; /* Cache size. */
108: uint32_t c0_clid; /* Cache level. */
109: uint32_t c0_cssel; /* Cache size selection. */
1.1.1.5 root 110: uint32_t c0_c1[8]; /* Feature registers. */
111: uint32_t c0_c2[8]; /* Instruction set registers. */
1.1.1.2 root 112: uint32_t c1_sys; /* System control register. */
113: uint32_t c1_coproc; /* Coprocessor access register. */
1.1.1.5 root 114: uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
115: uint32_t c2_base0; /* MMU translation table base 0. */
116: uint32_t c2_base1; /* MMU translation table base 1. */
1.1.1.6 root 117: uint32_t c2_control; /* MMU translation table base control. */
118: uint32_t c2_mask; /* MMU translation table base selection mask. */
119: uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
1.1.1.5 root 120: uint32_t c2_data; /* MPU data cachable bits. */
121: uint32_t c2_insn; /* MPU instruction cachable bits. */
122: uint32_t c3; /* MMU domain access control register
123: MPU write buffer control. */
1.1.1.2 root 124: uint32_t c5_insn; /* Fault status registers. */
125: uint32_t c5_data;
1.1.1.5 root 126: uint32_t c6_region[8]; /* MPU base/size registers. */
1.1.1.2 root 127: uint32_t c6_insn; /* Fault address registers. */
128: uint32_t c6_data;
129: uint32_t c9_insn; /* Cache lockdown registers. */
130: uint32_t c9_data;
131: uint32_t c13_fcse; /* FCSE PID. */
132: uint32_t c13_context; /* Context ID. */
1.1.1.5 root 133: uint32_t c13_tls1; /* User RW Thread register. */
134: uint32_t c13_tls2; /* User RO Thread register. */
135: uint32_t c13_tls3; /* Privileged Thread register. */
136: uint32_t c15_cpar; /* XScale Coprocessor Access Register */
137: uint32_t c15_ticonfig; /* TI925T configuration byte. */
138: uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
139: uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
140: uint32_t c15_threadid; /* TI debugger thread-ID. */
1.1.1.2 root 141: } cp15;
1.1.1.3 root 142:
1.1.1.5 root 143: struct {
144: uint32_t other_sp;
145: uint32_t vecbase;
146: uint32_t basepri;
147: uint32_t control;
148: int current_sp;
149: int exception;
150: int pending_exception;
151: } v7m;
152:
1.1.1.6 root 153: /* Thumb-2 EE state. */
154: uint32_t teecr;
155: uint32_t teehbr;
156:
1.1.1.3 root 157: /* Internal CPU feature flags. */
158: uint32_t features;
159:
1.1.1.5 root 160: /* Callback for vectored interrupt controller. */
161: int (*get_irq_vector)(struct CPUARMState *);
162: void *irq_opaque;
163:
1.1 root 164: /* VFP coprocessor state. */
165: struct {
1.1.1.5 root 166: float64 regs[32];
1.1 root 167:
1.1.1.3 root 168: uint32_t xregs[16];
1.1 root 169: /* We store these fpcsr fields separately for convenience. */
170: int vec_len;
171: int vec_stride;
172:
1.1.1.5 root 173: /* scratch space when Tn are not sufficient. */
174: uint32_t scratch[8];
175:
1.1.1.10! root 176: /* fp_status is the "normal" fp status. standard_fp_status retains
! 177: * values corresponding to the ARM "Standard FPSCR Value", ie
! 178: * default-NaN, flush-to-zero, round-to-nearest and is used by
! 179: * any operations (generally Neon) which the architecture defines
! 180: * as controlled by the standard FPSCR value rather than the FPSCR.
! 181: *
! 182: * To avoid having to transfer exception bits around, we simply
! 183: * say that the FPSCR cumulative exception flags are the logical
! 184: * OR of the flags in the two fp statuses. This relies on the
! 185: * only thing which needs to read the exception flags being
! 186: * an explicit FPSCR read.
! 187: */
1.1 root 188: float_status fp_status;
1.1.1.10! root 189: float_status standard_fp_status;
1.1 root 190: } vfp;
1.1.1.8 root 191: uint32_t exclusive_addr;
192: uint32_t exclusive_val;
193: uint32_t exclusive_high;
1.1.1.5 root 194: #if defined(CONFIG_USER_ONLY)
1.1.1.8 root 195: uint32_t exclusive_test;
196: uint32_t exclusive_info;
1.1.1.5 root 197: #endif
198:
199: /* iwMMXt coprocessor state. */
200: struct {
201: uint64_t regs[16];
202: uint64_t val;
203:
204: uint32_t cregs[16];
205: } iwmmxt;
1.1 root 206:
1.1.1.3 root 207: #if defined(CONFIG_USER_ONLY)
208: /* For usermode syscall translation. */
209: int eabi;
210: #endif
211:
1.1.1.2 root 212: CPU_COMMON
213:
1.1.1.5 root 214: /* These fields after the common ones so they are preserved on reset. */
1.1.1.9 root 215:
216: /* Coprocessor IO used by peripherals */
217: struct {
218: ARMReadCPFunc *cp_read;
219: ARMWriteCPFunc *cp_write;
220: void *opaque;
221: } cp[15];
222: void *nvic;
1.1.1.6 root 223: struct arm_boot_info *boot_info;
1.1 root 224: } CPUARMState;
225:
1.1.1.5 root 226: CPUARMState *cpu_arm_init(const char *cpu_model);
1.1.1.6 root 227: void arm_translate_init(void);
1.1 root 228: int cpu_arm_exec(CPUARMState *s);
229: void cpu_arm_close(CPUARMState *s);
1.1.1.2 root 230: void do_interrupt(CPUARMState *);
231: void switch_mode(CPUARMState *, int);
1.1.1.5 root 232: uint32_t do_arm_semihosting(CPUARMState *env);
1.1.1.2 root 233:
1.1 root 234: /* you can call this signal handler from your SIGBUS and SIGSEGV
235: signal handlers to inform the virtual CPU of exceptions. non zero
236: is returned if the signal was handled by the virtual CPU. */
1.1.1.5 root 237: int cpu_arm_signal_handler(int host_signum, void *pinfo,
1.1 root 238: void *puc);
1.1.1.6 root 239: int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
240: int mmu_idx, int is_softmuu);
1.1.1.8 root 241: #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
1.1 root 242:
1.1.1.6 root 243: static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
244: {
245: env->cp15.c13_tls2 = newtls;
246: }
1.1.1.5 root 247:
1.1.1.2 root 248: #define CPSR_M (0x1f)
249: #define CPSR_T (1 << 5)
250: #define CPSR_F (1 << 6)
251: #define CPSR_I (1 << 7)
252: #define CPSR_A (1 << 8)
253: #define CPSR_E (1 << 9)
254: #define CPSR_IT_2_7 (0xfc00)
1.1.1.5 root 255: #define CPSR_GE (0xf << 16)
256: #define CPSR_RESERVED (0xf << 20)
1.1.1.2 root 257: #define CPSR_J (1 << 24)
258: #define CPSR_IT_0_1 (3 << 25)
259: #define CPSR_Q (1 << 27)
1.1.1.5 root 260: #define CPSR_V (1 << 28)
261: #define CPSR_C (1 << 29)
262: #define CPSR_Z (1 << 30)
263: #define CPSR_N (1 << 31)
264: #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
265:
266: #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
267: #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
268: /* Bits writable in user mode. */
269: #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
270: /* Execution state bits. MRS read as zero, MSR writes ignored. */
271: #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
1.1.1.2 root 272:
273: /* Return the current CPSR value. */
1.1.1.5 root 274: uint32_t cpsr_read(CPUARMState *env);
275: /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
276: void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
277:
278: /* Return the current xPSR value. */
279: static inline uint32_t xpsr_read(CPUARMState *env)
1.1.1.2 root 280: {
281: int ZF;
1.1.1.6 root 282: ZF = (env->ZF == 0);
283: return (env->NF & 0x80000000) | (ZF << 30)
1.1.1.5 root 284: | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
285: | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
286: | ((env->condexec_bits & 0xfc) << 8)
287: | env->v7m.exception;
1.1.1.2 root 288: }
289:
1.1.1.5 root 290: /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
291: static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1.1.1.2 root 292: {
293: if (mask & CPSR_NZCV) {
1.1.1.6 root 294: env->ZF = (~val) & CPSR_Z;
295: env->NF = val;
1.1.1.2 root 296: env->CF = (val >> 29) & 1;
297: env->VF = (val << 3) & 0x80000000;
298: }
299: if (mask & CPSR_Q)
300: env->QF = ((val & CPSR_Q) != 0);
1.1.1.5 root 301: if (mask & (1 << 24))
302: env->thumb = ((val & (1 << 24)) != 0);
303: if (mask & CPSR_IT_0_1) {
304: env->condexec_bits &= ~3;
305: env->condexec_bits |= (val >> 25) & 3;
306: }
307: if (mask & CPSR_IT_2_7) {
308: env->condexec_bits &= 3;
309: env->condexec_bits |= (val >> 8) & 0xfc;
310: }
311: if (mask & 0x1ff) {
312: env->v7m.exception = val & 0x1ff;
1.1.1.2 root 313: }
314: }
315:
1.1.1.10! root 316: /* Return the current FPSCR value. */
! 317: uint32_t vfp_get_fpscr(CPUARMState *env);
! 318: void vfp_set_fpscr(CPUARMState *env, uint32_t val);
! 319:
1.1.1.2 root 320: enum arm_cpu_mode {
321: ARM_CPU_MODE_USR = 0x10,
322: ARM_CPU_MODE_FIQ = 0x11,
323: ARM_CPU_MODE_IRQ = 0x12,
324: ARM_CPU_MODE_SVC = 0x13,
325: ARM_CPU_MODE_ABT = 0x17,
326: ARM_CPU_MODE_UND = 0x1b,
327: ARM_CPU_MODE_SYS = 0x1f
328: };
329:
1.1.1.3 root 330: /* VFP system registers. */
331: #define ARM_VFP_FPSID 0
332: #define ARM_VFP_FPSCR 1
1.1.1.5 root 333: #define ARM_VFP_MVFR1 6
334: #define ARM_VFP_MVFR0 7
1.1.1.3 root 335: #define ARM_VFP_FPEXC 8
336: #define ARM_VFP_FPINST 9
337: #define ARM_VFP_FPINST2 10
338:
1.1.1.5 root 339: /* iwMMXt coprocessor control registers. */
340: #define ARM_IWMMXT_wCID 0
341: #define ARM_IWMMXT_wCon 1
342: #define ARM_IWMMXT_wCSSF 2
343: #define ARM_IWMMXT_wCASF 3
344: #define ARM_IWMMXT_wCGR0 8
345: #define ARM_IWMMXT_wCGR1 9
346: #define ARM_IWMMXT_wCGR2 10
347: #define ARM_IWMMXT_wCGR3 11
1.1.1.3 root 348:
349: enum arm_features {
350: ARM_FEATURE_VFP,
1.1.1.5 root 351: ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
352: ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
353: ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
354: ARM_FEATURE_V6,
355: ARM_FEATURE_V6K,
356: ARM_FEATURE_V7,
357: ARM_FEATURE_THUMB2,
358: ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
359: ARM_FEATURE_VFP3,
1.1.1.8 root 360: ARM_FEATURE_VFP_FP16,
1.1.1.5 root 361: ARM_FEATURE_NEON,
362: ARM_FEATURE_DIV,
363: ARM_FEATURE_M, /* Microcontroller profile. */
1.1.1.6 root 364: ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
365: ARM_FEATURE_THUMB2EE
1.1.1.3 root 366: };
367:
368: static inline int arm_feature(CPUARMState *env, int feature)
369: {
370: return (env->features & (1u << feature)) != 0;
371: }
372:
1.1.1.10! root 373: void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1.1.1.3 root 374:
1.1.1.5 root 375: /* Interface between CPU and Interrupt controller. */
376: void armv7m_nvic_set_pending(void *opaque, int irq);
377: int armv7m_nvic_acknowledge_irq(void *opaque);
378: void armv7m_nvic_complete_irq(void *opaque, int irq);
379:
380: void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
381: ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
382: void *opaque);
383:
384: /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
385: Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
386: conventional cores (ie. Application or Realtime profile). */
387:
388: #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
389: #define ARM_CPUID(env) (env->cp15.c0_cpuid)
390:
391: #define ARM_CPUID_ARM1026 0x4106a262
392: #define ARM_CPUID_ARM926 0x41069265
393: #define ARM_CPUID_ARM946 0x41059461
394: #define ARM_CPUID_TI915T 0x54029152
395: #define ARM_CPUID_TI925T 0x54029252
396: #define ARM_CPUID_PXA250 0x69052100
397: #define ARM_CPUID_PXA255 0x69052d00
398: #define ARM_CPUID_PXA260 0x69052903
399: #define ARM_CPUID_PXA261 0x69052d05
400: #define ARM_CPUID_PXA262 0x69052d06
401: #define ARM_CPUID_PXA270 0x69054110
402: #define ARM_CPUID_PXA270_A0 0x69054110
403: #define ARM_CPUID_PXA270_A1 0x69054111
404: #define ARM_CPUID_PXA270_B0 0x69054112
405: #define ARM_CPUID_PXA270_B1 0x69054113
406: #define ARM_CPUID_PXA270_C0 0x69054114
407: #define ARM_CPUID_PXA270_C5 0x69054117
408: #define ARM_CPUID_ARM1136 0x4117b363
1.1.1.6 root 409: #define ARM_CPUID_ARM1136_R2 0x4107b362
1.1.1.5 root 410: #define ARM_CPUID_ARM11MPCORE 0x410fb022
411: #define ARM_CPUID_CORTEXA8 0x410fc080
1.1.1.8 root 412: #define ARM_CPUID_CORTEXA9 0x410fc090
1.1.1.5 root 413: #define ARM_CPUID_CORTEXM3 0x410fc231
414: #define ARM_CPUID_ANY 0xffffffff
1.1.1.3 root 415:
1.1.1.2 root 416: #if defined(CONFIG_USER_ONLY)
1.1 root 417: #define TARGET_PAGE_BITS 12
1.1.1.2 root 418: #else
419: /* The ARM MMU allows 1k pages. */
420: /* ??? Linux doesn't actually use these, and they're deprecated in recent
1.1.1.5 root 421: architecture revisions. Maybe a configure option to disable them. */
1.1.1.2 root 422: #define TARGET_PAGE_BITS 10
423: #endif
1.1.1.5 root 424:
1.1.1.9 root 425: #define TARGET_PHYS_ADDR_SPACE_BITS 32
426: #define TARGET_VIRT_ADDR_SPACE_BITS 32
427:
1.1.1.5 root 428: #define cpu_init cpu_arm_init
429: #define cpu_exec cpu_arm_exec
430: #define cpu_gen_code cpu_arm_gen_code
431: #define cpu_signal_handler cpu_arm_signal_handler
432: #define cpu_list arm_cpu_list
433:
1.1.1.8 root 434: #define CPU_SAVE_VERSION 2
1.1.1.5 root 435:
436: /* MMU modes definitions */
437: #define MMU_MODE0_SUFFIX _kernel
438: #define MMU_MODE1_SUFFIX _user
439: #define MMU_USER_IDX 1
440: static inline int cpu_mmu_index (CPUState *env)
441: {
442: return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
443: }
444:
1.1.1.6 root 445: #if defined(CONFIG_USER_ONLY)
446: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
447: {
448: if (newsp)
449: env->regs[13] = newsp;
450: env->regs[0] = 0;
451: }
452: #endif
453:
1.1 root 454: #include "cpu-all.h"
1.1.1.6 root 455:
1.1.1.10! root 456: /* Bit usage in the TB flags field: */
! 457: #define ARM_TBFLAG_THUMB_SHIFT 0
! 458: #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
! 459: #define ARM_TBFLAG_VECLEN_SHIFT 1
! 460: #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
! 461: #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
! 462: #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
! 463: #define ARM_TBFLAG_PRIV_SHIFT 6
! 464: #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
! 465: #define ARM_TBFLAG_VFPEN_SHIFT 7
! 466: #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
! 467: #define ARM_TBFLAG_CONDEXEC_SHIFT 8
! 468: #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
! 469: /* Bits 31..16 are currently unused. */
! 470:
! 471: /* some convenience accessor macros */
! 472: #define ARM_TBFLAG_THUMB(F) \
! 473: (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
! 474: #define ARM_TBFLAG_VECLEN(F) \
! 475: (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
! 476: #define ARM_TBFLAG_VECSTRIDE(F) \
! 477: (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
! 478: #define ARM_TBFLAG_PRIV(F) \
! 479: (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
! 480: #define ARM_TBFLAG_VFPEN(F) \
! 481: (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
! 482: #define ARM_TBFLAG_CONDEXEC(F) \
! 483: (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
! 484:
1.1.1.6 root 485: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
486: target_ulong *cs_base, int *flags)
487: {
1.1.1.10! root 488: int privmode;
1.1.1.6 root 489: *pc = env->regs[15];
490: *cs_base = 0;
1.1.1.10! root 491: *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
! 492: | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
! 493: | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
! 494: | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
! 495: if (arm_feature(env, ARM_FEATURE_M)) {
! 496: privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
! 497: } else {
! 498: privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
! 499: }
! 500: if (privmode) {
! 501: *flags |= ARM_TBFLAG_PRIV_MASK;
! 502: }
! 503: if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
! 504: *flags |= ARM_TBFLAG_VFPEN_MASK;
! 505: }
1.1.1.6 root 506: }
1.1 root 507:
508: #endif
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