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1.1 root 1: /*
2: * ARM virtual CPU header
1.1.1.5 root 3: *
1.1 root 4: * Copyright (c) 2003 Fabrice Bellard
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.7 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #ifndef CPU_ARM_H
20: #define CPU_ARM_H
21:
22: #define TARGET_LONG_BITS 32
23:
1.1.1.4 root 24: #define ELF_MACHINE EM_ARM
25:
1.1.1.13! root 26: #define CPUArchState struct CPUARMState
1.1.1.7 root 27:
1.1.1.10 root 28: #include "config.h"
29: #include "qemu-common.h"
1.1 root 30: #include "cpu-defs.h"
31:
32: #include "softfloat.h"
33:
34: #define TARGET_HAS_ICE 1
35:
36: #define EXCP_UDEF 1 /* undefined instruction */
37: #define EXCP_SWI 2 /* software interrupt */
38: #define EXCP_PREFETCH_ABORT 3
39: #define EXCP_DATA_ABORT 4
1.1.1.2 root 40: #define EXCP_IRQ 5
41: #define EXCP_FIQ 6
1.1.1.3 root 42: #define EXCP_BKPT 7
1.1.1.5 root 43: #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
1.1.1.6 root 44: #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
1.1.1.8 root 45: #define EXCP_STREX 10
1.1.1.5 root 46:
47: #define ARMV7M_EXCP_RESET 1
48: #define ARMV7M_EXCP_NMI 2
49: #define ARMV7M_EXCP_HARD 3
50: #define ARMV7M_EXCP_MEM 4
51: #define ARMV7M_EXCP_BUS 5
52: #define ARMV7M_EXCP_USAGE 6
53: #define ARMV7M_EXCP_SVC 11
54: #define ARMV7M_EXCP_DEBUG 12
55: #define ARMV7M_EXCP_PENDSV 14
56: #define ARMV7M_EXCP_SYSTICK 15
57:
1.1.1.11 root 58: /* ARM-specific interrupt pending bits. */
59: #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
60:
61:
1.1.1.5 root 62: typedef void ARMWriteCPFunc(void *opaque, int cp_info,
63: int srcreg, int operand, uint32_t value);
64: typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
65: int dstreg, int operand);
66:
1.1.1.6 root 67: struct arm_boot_info;
68:
1.1.1.5 root 69: #define NB_MMU_MODES 2
1.1 root 70:
71: /* We currently assume float and double are IEEE single and double
72: precision respectively.
73: Doing runtime conversions is tricky because VFP registers may contain
74: integer values (eg. as the result of a FTOSI instruction).
75: s<2n> maps to the least significant half of d<n>
76: s<2n+1> maps to the most significant half of d<n>
77: */
78:
79: typedef struct CPUARMState {
1.1.1.2 root 80: /* Regs for current mode. */
1.1 root 81: uint32_t regs[16];
1.1.1.2 root 82: /* Frequently accessed CPSR bits are stored separately for efficiently.
1.1.1.4 root 83: This contains all the other bits. Use cpsr_{read,write} to access
1.1.1.2 root 84: the whole CPSR. */
85: uint32_t uncached_cpsr;
86: uint32_t spsr;
87:
88: /* Banked registers. */
89: uint32_t banked_spsr[6];
90: uint32_t banked_r13[6];
91: uint32_t banked_r14[6];
1.1.1.5 root 92:
1.1.1.2 root 93: /* These hold r8-r12. */
94: uint32_t usr_regs[5];
95: uint32_t fiq_regs[5];
1.1.1.5 root 96:
1.1 root 97: /* cpsr flag cache for faster execution */
98: uint32_t CF; /* 0 or 1 */
99: uint32_t VF; /* V is the bit 31. All other bits are undefined */
1.1.1.6 root 100: uint32_t NF; /* N is bit 31. All other bits are undefined. */
101: uint32_t ZF; /* Z set if zero. */
1.1 root 102: uint32_t QF; /* 0 or 1 */
1.1.1.5 root 103: uint32_t GE; /* cpsr[19:16] */
1.1.1.6 root 104: uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
1.1.1.5 root 105: uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
1.1 root 106:
1.1.1.2 root 107: /* System control coprocessor (cp15) */
108: struct {
1.1.1.3 root 109: uint32_t c0_cpuid;
1.1.1.5 root 110: uint32_t c0_cachetype;
1.1.1.6 root 111: uint32_t c0_ccsid[16]; /* Cache size. */
112: uint32_t c0_clid; /* Cache level. */
113: uint32_t c0_cssel; /* Cache size selection. */
1.1.1.5 root 114: uint32_t c0_c1[8]; /* Feature registers. */
115: uint32_t c0_c2[8]; /* Instruction set registers. */
1.1.1.2 root 116: uint32_t c1_sys; /* System control register. */
117: uint32_t c1_coproc; /* Coprocessor access register. */
1.1.1.5 root 118: uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
1.1.1.13! root 119: uint32_t c1_scr; /* secure config register. */
1.1.1.5 root 120: uint32_t c2_base0; /* MMU translation table base 0. */
121: uint32_t c2_base1; /* MMU translation table base 1. */
1.1.1.6 root 122: uint32_t c2_control; /* MMU translation table base control. */
123: uint32_t c2_mask; /* MMU translation table base selection mask. */
124: uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
1.1.1.5 root 125: uint32_t c2_data; /* MPU data cachable bits. */
126: uint32_t c2_insn; /* MPU instruction cachable bits. */
127: uint32_t c3; /* MMU domain access control register
128: MPU write buffer control. */
1.1.1.2 root 129: uint32_t c5_insn; /* Fault status registers. */
130: uint32_t c5_data;
1.1.1.5 root 131: uint32_t c6_region[8]; /* MPU base/size registers. */
1.1.1.2 root 132: uint32_t c6_insn; /* Fault address registers. */
133: uint32_t c6_data;
1.1.1.11 root 134: uint32_t c7_par; /* Translation result. */
1.1.1.2 root 135: uint32_t c9_insn; /* Cache lockdown registers. */
136: uint32_t c9_data;
1.1.1.11 root 137: uint32_t c9_pmcr; /* performance monitor control register */
138: uint32_t c9_pmcnten; /* perf monitor counter enables */
139: uint32_t c9_pmovsr; /* perf monitor overflow status */
140: uint32_t c9_pmxevtyper; /* perf monitor event type */
141: uint32_t c9_pmuserenr; /* perf monitor user enable */
142: uint32_t c9_pminten; /* perf monitor interrupt enables */
1.1.1.2 root 143: uint32_t c13_fcse; /* FCSE PID. */
144: uint32_t c13_context; /* Context ID. */
1.1.1.5 root 145: uint32_t c13_tls1; /* User RW Thread register. */
146: uint32_t c13_tls2; /* User RO Thread register. */
147: uint32_t c13_tls3; /* Privileged Thread register. */
148: uint32_t c15_cpar; /* XScale Coprocessor Access Register */
149: uint32_t c15_ticonfig; /* TI925T configuration byte. */
150: uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
151: uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
152: uint32_t c15_threadid; /* TI debugger thread-ID. */
1.1.1.13! root 153: uint32_t c15_config_base_address; /* SCU base address. */
! 154: uint32_t c15_diagnostic; /* diagnostic register */
! 155: uint32_t c15_power_diagnostic;
! 156: uint32_t c15_power_control; /* power control */
1.1.1.2 root 157: } cp15;
1.1.1.3 root 158:
1.1.1.5 root 159: struct {
160: uint32_t other_sp;
161: uint32_t vecbase;
162: uint32_t basepri;
163: uint32_t control;
164: int current_sp;
165: int exception;
166: int pending_exception;
167: } v7m;
168:
1.1.1.6 root 169: /* Thumb-2 EE state. */
170: uint32_t teecr;
171: uint32_t teehbr;
172:
1.1 root 173: /* VFP coprocessor state. */
174: struct {
1.1.1.5 root 175: float64 regs[32];
1.1 root 176:
1.1.1.3 root 177: uint32_t xregs[16];
1.1 root 178: /* We store these fpcsr fields separately for convenience. */
179: int vec_len;
180: int vec_stride;
181:
1.1.1.5 root 182: /* scratch space when Tn are not sufficient. */
183: uint32_t scratch[8];
184:
1.1.1.10 root 185: /* fp_status is the "normal" fp status. standard_fp_status retains
186: * values corresponding to the ARM "Standard FPSCR Value", ie
187: * default-NaN, flush-to-zero, round-to-nearest and is used by
188: * any operations (generally Neon) which the architecture defines
189: * as controlled by the standard FPSCR value rather than the FPSCR.
190: *
191: * To avoid having to transfer exception bits around, we simply
192: * say that the FPSCR cumulative exception flags are the logical
193: * OR of the flags in the two fp statuses. This relies on the
194: * only thing which needs to read the exception flags being
195: * an explicit FPSCR read.
196: */
1.1 root 197: float_status fp_status;
1.1.1.10 root 198: float_status standard_fp_status;
1.1 root 199: } vfp;
1.1.1.8 root 200: uint32_t exclusive_addr;
201: uint32_t exclusive_val;
202: uint32_t exclusive_high;
1.1.1.5 root 203: #if defined(CONFIG_USER_ONLY)
1.1.1.8 root 204: uint32_t exclusive_test;
205: uint32_t exclusive_info;
1.1.1.5 root 206: #endif
207:
208: /* iwMMXt coprocessor state. */
209: struct {
210: uint64_t regs[16];
211: uint64_t val;
212:
213: uint32_t cregs[16];
214: } iwmmxt;
1.1 root 215:
1.1.1.13! root 216: /* For mixed endian mode. */
! 217: bool bswap_code;
! 218:
1.1.1.3 root 219: #if defined(CONFIG_USER_ONLY)
220: /* For usermode syscall translation. */
221: int eabi;
222: #endif
223:
1.1.1.2 root 224: CPU_COMMON
225:
1.1.1.5 root 226: /* These fields after the common ones so they are preserved on reset. */
1.1.1.9 root 227:
1.1.1.13! root 228: /* Internal CPU feature flags. */
! 229: uint32_t features;
! 230:
1.1.1.9 root 231: /* Coprocessor IO used by peripherals */
232: struct {
233: ARMReadCPFunc *cp_read;
234: ARMWriteCPFunc *cp_write;
235: void *opaque;
236: } cp[15];
237: void *nvic;
1.1.1.11 root 238: const struct arm_boot_info *boot_info;
1.1 root 239: } CPUARMState;
240:
1.1.1.13! root 241: #include "cpu-qom.h"
! 242:
! 243: ARMCPU *cpu_arm_init(const char *cpu_model);
1.1.1.6 root 244: void arm_translate_init(void);
1.1 root 245: int cpu_arm_exec(CPUARMState *s);
1.1.1.2 root 246: void do_interrupt(CPUARMState *);
247: void switch_mode(CPUARMState *, int);
1.1.1.5 root 248: uint32_t do_arm_semihosting(CPUARMState *env);
1.1.1.2 root 249:
1.1 root 250: /* you can call this signal handler from your SIGBUS and SIGSEGV
251: signal handlers to inform the virtual CPU of exceptions. non zero
252: is returned if the signal was handled by the virtual CPU. */
1.1.1.5 root 253: int cpu_arm_signal_handler(int host_signum, void *pinfo,
1.1 root 254: void *puc);
1.1.1.6 root 255: int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
1.1.1.12 root 256: int mmu_idx);
1.1.1.8 root 257: #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
1.1 root 258:
1.1.1.6 root 259: static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
260: {
261: env->cp15.c13_tls2 = newtls;
262: }
1.1.1.5 root 263:
1.1.1.2 root 264: #define CPSR_M (0x1f)
265: #define CPSR_T (1 << 5)
266: #define CPSR_F (1 << 6)
267: #define CPSR_I (1 << 7)
268: #define CPSR_A (1 << 8)
269: #define CPSR_E (1 << 9)
270: #define CPSR_IT_2_7 (0xfc00)
1.1.1.5 root 271: #define CPSR_GE (0xf << 16)
272: #define CPSR_RESERVED (0xf << 20)
1.1.1.2 root 273: #define CPSR_J (1 << 24)
274: #define CPSR_IT_0_1 (3 << 25)
275: #define CPSR_Q (1 << 27)
1.1.1.5 root 276: #define CPSR_V (1 << 28)
277: #define CPSR_C (1 << 29)
278: #define CPSR_Z (1 << 30)
279: #define CPSR_N (1 << 31)
280: #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
281:
282: #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
283: #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
284: /* Bits writable in user mode. */
285: #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
286: /* Execution state bits. MRS read as zero, MSR writes ignored. */
287: #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
1.1.1.2 root 288:
289: /* Return the current CPSR value. */
1.1.1.5 root 290: uint32_t cpsr_read(CPUARMState *env);
291: /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
292: void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
293:
294: /* Return the current xPSR value. */
295: static inline uint32_t xpsr_read(CPUARMState *env)
1.1.1.2 root 296: {
297: int ZF;
1.1.1.6 root 298: ZF = (env->ZF == 0);
299: return (env->NF & 0x80000000) | (ZF << 30)
1.1.1.5 root 300: | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
301: | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
302: | ((env->condexec_bits & 0xfc) << 8)
303: | env->v7m.exception;
1.1.1.2 root 304: }
305:
1.1.1.5 root 306: /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
307: static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1.1.1.2 root 308: {
309: if (mask & CPSR_NZCV) {
1.1.1.6 root 310: env->ZF = (~val) & CPSR_Z;
311: env->NF = val;
1.1.1.2 root 312: env->CF = (val >> 29) & 1;
313: env->VF = (val << 3) & 0x80000000;
314: }
315: if (mask & CPSR_Q)
316: env->QF = ((val & CPSR_Q) != 0);
1.1.1.5 root 317: if (mask & (1 << 24))
318: env->thumb = ((val & (1 << 24)) != 0);
319: if (mask & CPSR_IT_0_1) {
320: env->condexec_bits &= ~3;
321: env->condexec_bits |= (val >> 25) & 3;
322: }
323: if (mask & CPSR_IT_2_7) {
324: env->condexec_bits &= 3;
325: env->condexec_bits |= (val >> 8) & 0xfc;
326: }
327: if (mask & 0x1ff) {
328: env->v7m.exception = val & 0x1ff;
1.1.1.2 root 329: }
330: }
331:
1.1.1.10 root 332: /* Return the current FPSCR value. */
333: uint32_t vfp_get_fpscr(CPUARMState *env);
334: void vfp_set_fpscr(CPUARMState *env, uint32_t val);
335:
1.1.1.2 root 336: enum arm_cpu_mode {
337: ARM_CPU_MODE_USR = 0x10,
338: ARM_CPU_MODE_FIQ = 0x11,
339: ARM_CPU_MODE_IRQ = 0x12,
340: ARM_CPU_MODE_SVC = 0x13,
341: ARM_CPU_MODE_ABT = 0x17,
342: ARM_CPU_MODE_UND = 0x1b,
343: ARM_CPU_MODE_SYS = 0x1f
344: };
345:
1.1.1.3 root 346: /* VFP system registers. */
347: #define ARM_VFP_FPSID 0
348: #define ARM_VFP_FPSCR 1
1.1.1.5 root 349: #define ARM_VFP_MVFR1 6
350: #define ARM_VFP_MVFR0 7
1.1.1.3 root 351: #define ARM_VFP_FPEXC 8
352: #define ARM_VFP_FPINST 9
353: #define ARM_VFP_FPINST2 10
354:
1.1.1.5 root 355: /* iwMMXt coprocessor control registers. */
356: #define ARM_IWMMXT_wCID 0
357: #define ARM_IWMMXT_wCon 1
358: #define ARM_IWMMXT_wCSSF 2
359: #define ARM_IWMMXT_wCASF 3
360: #define ARM_IWMMXT_wCGR0 8
361: #define ARM_IWMMXT_wCGR1 9
362: #define ARM_IWMMXT_wCGR2 10
363: #define ARM_IWMMXT_wCGR3 11
1.1.1.3 root 364:
1.1.1.13! root 365: /* If adding a feature bit which corresponds to a Linux ELF
! 366: * HWCAP bit, remember to update the feature-bit-to-hwcap
! 367: * mapping in linux-user/elfload.c:get_elf_hwcap().
! 368: */
1.1.1.3 root 369: enum arm_features {
370: ARM_FEATURE_VFP,
1.1.1.5 root 371: ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
372: ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
373: ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
374: ARM_FEATURE_V6,
375: ARM_FEATURE_V6K,
376: ARM_FEATURE_V7,
377: ARM_FEATURE_THUMB2,
378: ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
379: ARM_FEATURE_VFP3,
1.1.1.8 root 380: ARM_FEATURE_VFP_FP16,
1.1.1.5 root 381: ARM_FEATURE_NEON,
1.1.1.12 root 382: ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
1.1.1.5 root 383: ARM_FEATURE_M, /* Microcontroller profile. */
1.1.1.6 root 384: ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
1.1.1.11 root 385: ARM_FEATURE_THUMB2EE,
386: ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
387: ARM_FEATURE_V4T,
388: ARM_FEATURE_V5,
389: ARM_FEATURE_STRONGARM,
390: ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
1.1.1.12 root 391: ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
392: ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
1.1.1.13! root 393: ARM_FEATURE_GENERIC_TIMER,
! 394: ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
1.1.1.3 root 395: };
396:
397: static inline int arm_feature(CPUARMState *env, int feature)
398: {
399: return (env->features & (1u << feature)) != 0;
400: }
401:
1.1.1.10 root 402: void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1.1.1.3 root 403:
1.1.1.5 root 404: /* Interface between CPU and Interrupt controller. */
405: void armv7m_nvic_set_pending(void *opaque, int irq);
406: int armv7m_nvic_acknowledge_irq(void *opaque);
407: void armv7m_nvic_complete_irq(void *opaque, int irq);
408:
409: void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
410: ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
411: void *opaque);
412:
413: /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
414: Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
415: conventional cores (ie. Application or Realtime profile). */
416:
417: #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
418: #define ARM_CPUID(env) (env->cp15.c0_cpuid)
419:
420: #define ARM_CPUID_ARM1026 0x4106a262
421: #define ARM_CPUID_ARM926 0x41069265
422: #define ARM_CPUID_ARM946 0x41059461
423: #define ARM_CPUID_TI915T 0x54029152
424: #define ARM_CPUID_TI925T 0x54029252
1.1.1.11 root 425: #define ARM_CPUID_SA1100 0x4401A11B
426: #define ARM_CPUID_SA1110 0x6901B119
1.1.1.5 root 427: #define ARM_CPUID_PXA250 0x69052100
428: #define ARM_CPUID_PXA255 0x69052d00
429: #define ARM_CPUID_PXA260 0x69052903
430: #define ARM_CPUID_PXA261 0x69052d05
431: #define ARM_CPUID_PXA262 0x69052d06
432: #define ARM_CPUID_PXA270 0x69054110
433: #define ARM_CPUID_PXA270_A0 0x69054110
434: #define ARM_CPUID_PXA270_A1 0x69054111
435: #define ARM_CPUID_PXA270_B0 0x69054112
436: #define ARM_CPUID_PXA270_B1 0x69054113
437: #define ARM_CPUID_PXA270_C0 0x69054114
438: #define ARM_CPUID_PXA270_C5 0x69054117
439: #define ARM_CPUID_ARM1136 0x4117b363
1.1.1.6 root 440: #define ARM_CPUID_ARM1136_R2 0x4107b362
1.1.1.12 root 441: #define ARM_CPUID_ARM1176 0x410fb767
1.1.1.5 root 442: #define ARM_CPUID_ARM11MPCORE 0x410fb022
443: #define ARM_CPUID_CORTEXA8 0x410fc080
1.1.1.8 root 444: #define ARM_CPUID_CORTEXA9 0x410fc090
1.1.1.13! root 445: #define ARM_CPUID_CORTEXA15 0x412fc0f1
1.1.1.5 root 446: #define ARM_CPUID_CORTEXM3 0x410fc231
447: #define ARM_CPUID_ANY 0xffffffff
1.1.1.3 root 448:
1.1.1.2 root 449: #if defined(CONFIG_USER_ONLY)
1.1 root 450: #define TARGET_PAGE_BITS 12
1.1.1.2 root 451: #else
452: /* The ARM MMU allows 1k pages. */
453: /* ??? Linux doesn't actually use these, and they're deprecated in recent
1.1.1.5 root 454: architecture revisions. Maybe a configure option to disable them. */
1.1.1.2 root 455: #define TARGET_PAGE_BITS 10
456: #endif
1.1.1.5 root 457:
1.1.1.9 root 458: #define TARGET_PHYS_ADDR_SPACE_BITS 32
459: #define TARGET_VIRT_ADDR_SPACE_BITS 32
460:
1.1.1.13! root 461: static inline CPUARMState *cpu_init(const char *cpu_model)
! 462: {
! 463: ARMCPU *cpu = cpu_arm_init(cpu_model);
! 464: if (cpu) {
! 465: return &cpu->env;
! 466: }
! 467: return NULL;
! 468: }
! 469:
1.1.1.5 root 470: #define cpu_exec cpu_arm_exec
471: #define cpu_gen_code cpu_arm_gen_code
472: #define cpu_signal_handler cpu_arm_signal_handler
473: #define cpu_list arm_cpu_list
474:
1.1.1.13! root 475: #define CPU_SAVE_VERSION 6
1.1.1.5 root 476:
477: /* MMU modes definitions */
478: #define MMU_MODE0_SUFFIX _kernel
479: #define MMU_MODE1_SUFFIX _user
480: #define MMU_USER_IDX 1
1.1.1.13! root 481: static inline int cpu_mmu_index (CPUARMState *env)
1.1.1.5 root 482: {
483: return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
484: }
485:
1.1.1.6 root 486: #if defined(CONFIG_USER_ONLY)
1.1.1.13! root 487: static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
1.1.1.6 root 488: {
489: if (newsp)
490: env->regs[13] = newsp;
491: env->regs[0] = 0;
492: }
493: #endif
494:
1.1 root 495: #include "cpu-all.h"
1.1.1.6 root 496:
1.1.1.10 root 497: /* Bit usage in the TB flags field: */
498: #define ARM_TBFLAG_THUMB_SHIFT 0
499: #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
500: #define ARM_TBFLAG_VECLEN_SHIFT 1
501: #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
502: #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
503: #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
504: #define ARM_TBFLAG_PRIV_SHIFT 6
505: #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
506: #define ARM_TBFLAG_VFPEN_SHIFT 7
507: #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
508: #define ARM_TBFLAG_CONDEXEC_SHIFT 8
509: #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1.1.1.13! root 510: #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
! 511: #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
! 512: /* Bits 31..17 are currently unused. */
1.1.1.10 root 513:
514: /* some convenience accessor macros */
515: #define ARM_TBFLAG_THUMB(F) \
516: (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
517: #define ARM_TBFLAG_VECLEN(F) \
518: (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
519: #define ARM_TBFLAG_VECSTRIDE(F) \
520: (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
521: #define ARM_TBFLAG_PRIV(F) \
522: (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
523: #define ARM_TBFLAG_VFPEN(F) \
524: (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
525: #define ARM_TBFLAG_CONDEXEC(F) \
526: (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
1.1.1.13! root 527: #define ARM_TBFLAG_BSWAP_CODE(F) \
! 528: (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
1.1.1.10 root 529:
1.1.1.13! root 530: static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
1.1.1.6 root 531: target_ulong *cs_base, int *flags)
532: {
1.1.1.10 root 533: int privmode;
1.1.1.6 root 534: *pc = env->regs[15];
535: *cs_base = 0;
1.1.1.10 root 536: *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
537: | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
538: | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
1.1.1.13! root 539: | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
! 540: | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
1.1.1.10 root 541: if (arm_feature(env, ARM_FEATURE_M)) {
542: privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
543: } else {
544: privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
545: }
546: if (privmode) {
547: *flags |= ARM_TBFLAG_PRIV_MASK;
548: }
549: if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
550: *flags |= ARM_TBFLAG_VFPEN_MASK;
551: }
1.1.1.6 root 552: }
1.1 root 553:
1.1.1.13! root 554: static inline bool cpu_has_work(CPUARMState *env)
1.1.1.11 root 555: {
556: return env->interrupt_request &
557: (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
558: }
559:
560: #include "exec-all.h"
561:
1.1.1.13! root 562: static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
1.1.1.11 root 563: {
564: env->regs[15] = tb->pc;
565: }
566:
1.1.1.13! root 567: /* Load an instruction and return it in the standard little-endian order */
! 568: static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
! 569: {
! 570: uint32_t insn = ldl_code(addr);
! 571: if (do_swap) {
! 572: return bswap32(insn);
! 573: }
! 574: return insn;
! 575: }
! 576:
! 577: /* Ditto, for a halfword (Thumb) instruction */
! 578: static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
! 579: {
! 580: uint16_t insn = lduw_code(addr);
! 581: if (do_swap) {
! 582: return bswap16(insn);
! 583: }
! 584: return insn;
! 585: }
! 586:
1.1 root 587: #endif
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