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1.1 root 1: /*
2: * ARM virtual CPU header
3: *
4: * Copyright (c) 2003 Fabrice Bellard
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #ifndef CPU_ARM_H
21: #define CPU_ARM_H
22:
23: #define TARGET_LONG_BITS 32
24:
25: #include "cpu-defs.h"
26:
27: #include "softfloat.h"
28:
29: #define TARGET_HAS_ICE 1
30:
31: #define EXCP_UDEF 1 /* undefined instruction */
32: #define EXCP_SWI 2 /* software interrupt */
33: #define EXCP_PREFETCH_ABORT 3
34: #define EXCP_DATA_ABORT 4
1.1.1.2 ! root 35: #define EXCP_IRQ 5
! 36: #define EXCP_FIQ 6
1.1 root 37:
38: /* We currently assume float and double are IEEE single and double
39: precision respectively.
40: Doing runtime conversions is tricky because VFP registers may contain
41: integer values (eg. as the result of a FTOSI instruction).
42: s<2n> maps to the least significant half of d<n>
43: s<2n+1> maps to the most significant half of d<n>
44: */
45:
46: typedef struct CPUARMState {
1.1.1.2 ! root 47: /* Regs for current mode. */
1.1 root 48: uint32_t regs[16];
1.1.1.2 ! root 49: /* Frequently accessed CPSR bits are stored separately for efficiently.
! 50: This contains all the other bits. Use cpsr_{read,write} to accless
! 51: the whole CPSR. */
! 52: uint32_t uncached_cpsr;
! 53: uint32_t spsr;
! 54:
! 55: /* Banked registers. */
! 56: uint32_t banked_spsr[6];
! 57: uint32_t banked_r13[6];
! 58: uint32_t banked_r14[6];
! 59:
! 60: /* These hold r8-r12. */
! 61: uint32_t usr_regs[5];
! 62: uint32_t fiq_regs[5];
1.1 root 63:
64: /* cpsr flag cache for faster execution */
65: uint32_t CF; /* 0 or 1 */
66: uint32_t VF; /* V is the bit 31. All other bits are undefined */
67: uint32_t NZF; /* N is bit 31. Z is computed from NZF */
68: uint32_t QF; /* 0 or 1 */
69:
70: int thumb; /* 0 = arm mode, 1 = thumb mode */
71:
1.1.1.2 ! root 72: /* System control coprocessor (cp15) */
! 73: struct {
! 74: uint32_t c1_sys; /* System control register. */
! 75: uint32_t c1_coproc; /* Coprocessor access register. */
! 76: uint32_t c2; /* MMU translation table base. */
! 77: uint32_t c3; /* MMU domain access control register. */
! 78: uint32_t c5_insn; /* Fault status registers. */
! 79: uint32_t c5_data;
! 80: uint32_t c6_insn; /* Fault address registers. */
! 81: uint32_t c6_data;
! 82: uint32_t c9_insn; /* Cache lockdown registers. */
! 83: uint32_t c9_data;
! 84: uint32_t c13_fcse; /* FCSE PID. */
! 85: uint32_t c13_context; /* Context ID. */
! 86: } cp15;
1.1 root 87:
88: /* exception/interrupt handling */
89: jmp_buf jmp_env;
90: int exception_index;
91: int interrupt_request;
92: int user_mode_only;
1.1.1.2 ! root 93: int halted;
1.1 root 94:
95: /* VFP coprocessor state. */
96: struct {
97: float64 regs[16];
98:
99: /* We store these fpcsr fields separately for convenience. */
100: int vec_len;
101: int vec_stride;
102:
103: uint32_t fpscr;
104:
105: /* Temporary variables if we don't have spare fp regs. */
106: float32 tmp0s, tmp1s;
107: float64 tmp0d, tmp1d;
108:
109: float_status fp_status;
110: } vfp;
111:
1.1.1.2 ! root 112: CPU_COMMON
! 113:
1.1 root 114: } CPUARMState;
115:
116: CPUARMState *cpu_arm_init(void);
117: int cpu_arm_exec(CPUARMState *s);
118: void cpu_arm_close(CPUARMState *s);
1.1.1.2 ! root 119: void do_interrupt(CPUARMState *);
! 120: void switch_mode(CPUARMState *, int);
! 121:
1.1 root 122: /* you can call this signal handler from your SIGBUS and SIGSEGV
123: signal handlers to inform the virtual CPU of exceptions. non zero
124: is returned if the signal was handled by the virtual CPU. */
125: struct siginfo;
126: int cpu_arm_signal_handler(int host_signum, struct siginfo *info,
127: void *puc);
128:
1.1.1.2 ! root 129: #define CPSR_M (0x1f)
! 130: #define CPSR_T (1 << 5)
! 131: #define CPSR_F (1 << 6)
! 132: #define CPSR_I (1 << 7)
! 133: #define CPSR_A (1 << 8)
! 134: #define CPSR_E (1 << 9)
! 135: #define CPSR_IT_2_7 (0xfc00)
! 136: /* Bits 20-23 reserved. */
! 137: #define CPSR_J (1 << 24)
! 138: #define CPSR_IT_0_1 (3 << 25)
! 139: #define CPSR_Q (1 << 27)
! 140: #define CPSR_NZCV (0xf << 28)
! 141:
! 142: #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
! 143: /* Return the current CPSR value. */
! 144: static inline uint32_t cpsr_read(CPUARMState *env)
! 145: {
! 146: int ZF;
! 147: ZF = (env->NZF == 0);
! 148: return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
! 149: (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
! 150: | (env->thumb << 5);
! 151: }
! 152:
! 153: /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
! 154: static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
! 155: {
! 156: /* NOTE: N = 1 and Z = 1 cannot be stored currently */
! 157: if (mask & CPSR_NZCV) {
! 158: env->NZF = (val & 0xc0000000) ^ 0x40000000;
! 159: env->CF = (val >> 29) & 1;
! 160: env->VF = (val << 3) & 0x80000000;
! 161: }
! 162: if (mask & CPSR_Q)
! 163: env->QF = ((val & CPSR_Q) != 0);
! 164: if (mask & CPSR_T)
! 165: env->thumb = ((val & CPSR_T) != 0);
! 166:
! 167: if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
! 168: switch_mode(env, val & CPSR_M);
! 169: }
! 170: mask &= ~CACHED_CPSR_BITS;
! 171: env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
! 172: }
! 173:
! 174: enum arm_cpu_mode {
! 175: ARM_CPU_MODE_USR = 0x10,
! 176: ARM_CPU_MODE_FIQ = 0x11,
! 177: ARM_CPU_MODE_IRQ = 0x12,
! 178: ARM_CPU_MODE_SVC = 0x13,
! 179: ARM_CPU_MODE_ABT = 0x17,
! 180: ARM_CPU_MODE_UND = 0x1b,
! 181: ARM_CPU_MODE_SYS = 0x1f
! 182: };
! 183:
! 184: #if defined(CONFIG_USER_ONLY)
1.1 root 185: #define TARGET_PAGE_BITS 12
1.1.1.2 ! root 186: #else
! 187: /* The ARM MMU allows 1k pages. */
! 188: /* ??? Linux doesn't actually use these, and they're deprecated in recent
! 189: architecture revisions. Maybe an a configure option to disable them. */
! 190: #define TARGET_PAGE_BITS 10
! 191: #endif
1.1 root 192: #include "cpu-all.h"
193:
194: #endif
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