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1.1 root 1: /*
2: * ARM virtual CPU header
3: *
4: * Copyright (c) 2003 Fabrice Bellard
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #ifndef CPU_ARM_H
21: #define CPU_ARM_H
22:
23: #define TARGET_LONG_BITS 32
24:
25: #include "cpu-defs.h"
26:
27: #include "softfloat.h"
28:
29: #define TARGET_HAS_ICE 1
30:
31: #define EXCP_UDEF 1 /* undefined instruction */
32: #define EXCP_SWI 2 /* software interrupt */
33: #define EXCP_PREFETCH_ABORT 3
34: #define EXCP_DATA_ABORT 4
1.1.1.2 root 35: #define EXCP_IRQ 5
36: #define EXCP_FIQ 6
1.1.1.3 ! root 37: #define EXCP_BKPT 7
1.1 root 38:
39: /* We currently assume float and double are IEEE single and double
40: precision respectively.
41: Doing runtime conversions is tricky because VFP registers may contain
42: integer values (eg. as the result of a FTOSI instruction).
43: s<2n> maps to the least significant half of d<n>
44: s<2n+1> maps to the most significant half of d<n>
45: */
46:
47: typedef struct CPUARMState {
1.1.1.2 root 48: /* Regs for current mode. */
1.1 root 49: uint32_t regs[16];
1.1.1.2 root 50: /* Frequently accessed CPSR bits are stored separately for efficiently.
51: This contains all the other bits. Use cpsr_{read,write} to accless
52: the whole CPSR. */
53: uint32_t uncached_cpsr;
54: uint32_t spsr;
55:
56: /* Banked registers. */
57: uint32_t banked_spsr[6];
58: uint32_t banked_r13[6];
59: uint32_t banked_r14[6];
60:
61: /* These hold r8-r12. */
62: uint32_t usr_regs[5];
63: uint32_t fiq_regs[5];
1.1 root 64:
65: /* cpsr flag cache for faster execution */
66: uint32_t CF; /* 0 or 1 */
67: uint32_t VF; /* V is the bit 31. All other bits are undefined */
68: uint32_t NZF; /* N is bit 31. Z is computed from NZF */
69: uint32_t QF; /* 0 or 1 */
70:
71: int thumb; /* 0 = arm mode, 1 = thumb mode */
72:
1.1.1.2 root 73: /* System control coprocessor (cp15) */
74: struct {
1.1.1.3 ! root 75: uint32_t c0_cpuid;
1.1.1.2 root 76: uint32_t c1_sys; /* System control register. */
77: uint32_t c1_coproc; /* Coprocessor access register. */
78: uint32_t c2; /* MMU translation table base. */
79: uint32_t c3; /* MMU domain access control register. */
80: uint32_t c5_insn; /* Fault status registers. */
81: uint32_t c5_data;
82: uint32_t c6_insn; /* Fault address registers. */
83: uint32_t c6_data;
84: uint32_t c9_insn; /* Cache lockdown registers. */
85: uint32_t c9_data;
86: uint32_t c13_fcse; /* FCSE PID. */
87: uint32_t c13_context; /* Context ID. */
88: } cp15;
1.1.1.3 ! root 89:
! 90: /* Internal CPU feature flags. */
! 91: uint32_t features;
! 92:
1.1 root 93: /* exception/interrupt handling */
94: jmp_buf jmp_env;
95: int exception_index;
96: int interrupt_request;
97: int user_mode_only;
1.1.1.2 root 98: int halted;
1.1 root 99:
100: /* VFP coprocessor state. */
101: struct {
102: float64 regs[16];
103:
1.1.1.3 ! root 104: uint32_t xregs[16];
1.1 root 105: /* We store these fpcsr fields separately for convenience. */
106: int vec_len;
107: int vec_stride;
108:
109: /* Temporary variables if we don't have spare fp regs. */
110: float32 tmp0s, tmp1s;
111: float64 tmp0d, tmp1d;
112:
113: float_status fp_status;
114: } vfp;
115:
1.1.1.3 ! root 116: #if defined(CONFIG_USER_ONLY)
! 117: /* For usermode syscall translation. */
! 118: int eabi;
! 119: #endif
! 120:
1.1.1.2 root 121: CPU_COMMON
122:
1.1 root 123: } CPUARMState;
124:
125: CPUARMState *cpu_arm_init(void);
126: int cpu_arm_exec(CPUARMState *s);
127: void cpu_arm_close(CPUARMState *s);
1.1.1.2 root 128: void do_interrupt(CPUARMState *);
129: void switch_mode(CPUARMState *, int);
130:
1.1 root 131: /* you can call this signal handler from your SIGBUS and SIGSEGV
132: signal handlers to inform the virtual CPU of exceptions. non zero
133: is returned if the signal was handled by the virtual CPU. */
134: struct siginfo;
135: int cpu_arm_signal_handler(int host_signum, struct siginfo *info,
136: void *puc);
137:
1.1.1.2 root 138: #define CPSR_M (0x1f)
139: #define CPSR_T (1 << 5)
140: #define CPSR_F (1 << 6)
141: #define CPSR_I (1 << 7)
142: #define CPSR_A (1 << 8)
143: #define CPSR_E (1 << 9)
144: #define CPSR_IT_2_7 (0xfc00)
145: /* Bits 20-23 reserved. */
146: #define CPSR_J (1 << 24)
147: #define CPSR_IT_0_1 (3 << 25)
148: #define CPSR_Q (1 << 27)
149: #define CPSR_NZCV (0xf << 28)
150:
151: #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
152: /* Return the current CPSR value. */
153: static inline uint32_t cpsr_read(CPUARMState *env)
154: {
155: int ZF;
156: ZF = (env->NZF == 0);
157: return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
158: (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
159: | (env->thumb << 5);
160: }
161:
162: /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
163: static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
164: {
165: /* NOTE: N = 1 and Z = 1 cannot be stored currently */
166: if (mask & CPSR_NZCV) {
167: env->NZF = (val & 0xc0000000) ^ 0x40000000;
168: env->CF = (val >> 29) & 1;
169: env->VF = (val << 3) & 0x80000000;
170: }
171: if (mask & CPSR_Q)
172: env->QF = ((val & CPSR_Q) != 0);
173: if (mask & CPSR_T)
174: env->thumb = ((val & CPSR_T) != 0);
175:
176: if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
177: switch_mode(env, val & CPSR_M);
178: }
179: mask &= ~CACHED_CPSR_BITS;
180: env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
181: }
182:
183: enum arm_cpu_mode {
184: ARM_CPU_MODE_USR = 0x10,
185: ARM_CPU_MODE_FIQ = 0x11,
186: ARM_CPU_MODE_IRQ = 0x12,
187: ARM_CPU_MODE_SVC = 0x13,
188: ARM_CPU_MODE_ABT = 0x17,
189: ARM_CPU_MODE_UND = 0x1b,
190: ARM_CPU_MODE_SYS = 0x1f
191: };
192:
1.1.1.3 ! root 193: /* VFP system registers. */
! 194: #define ARM_VFP_FPSID 0
! 195: #define ARM_VFP_FPSCR 1
! 196: #define ARM_VFP_FPEXC 8
! 197: #define ARM_VFP_FPINST 9
! 198: #define ARM_VFP_FPINST2 10
! 199:
! 200:
! 201: enum arm_features {
! 202: ARM_FEATURE_VFP,
! 203: ARM_FEATURE_AUXCR /* ARM1026 Auxiliary control register. */
! 204: };
! 205:
! 206: static inline int arm_feature(CPUARMState *env, int feature)
! 207: {
! 208: return (env->features & (1u << feature)) != 0;
! 209: }
! 210:
! 211: void cpu_arm_set_model(CPUARMState *env, uint32_t id);
! 212:
! 213: #define ARM_CPUID_ARM1026 0x4106a262
! 214: #define ARM_CPUID_ARM926 0x41069265
! 215:
1.1.1.2 root 216: #if defined(CONFIG_USER_ONLY)
1.1 root 217: #define TARGET_PAGE_BITS 12
1.1.1.2 root 218: #else
219: /* The ARM MMU allows 1k pages. */
220: /* ??? Linux doesn't actually use these, and they're deprecated in recent
221: architecture revisions. Maybe an a configure option to disable them. */
222: #define TARGET_PAGE_BITS 10
223: #endif
1.1 root 224: #include "cpu-all.h"
225:
226: #endif
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