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1.1 root 1: /*
2: * ARM virtual CPU header
3: *
4: * Copyright (c) 2003 Fabrice Bellard
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #ifndef CPU_ARM_H
21: #define CPU_ARM_H
22:
23: #define TARGET_LONG_BITS 32
24:
1.1.1.4 ! root 25: #define ELF_MACHINE EM_ARM
! 26:
1.1 root 27: #include "cpu-defs.h"
28:
29: #include "softfloat.h"
30:
31: #define TARGET_HAS_ICE 1
32:
33: #define EXCP_UDEF 1 /* undefined instruction */
34: #define EXCP_SWI 2 /* software interrupt */
35: #define EXCP_PREFETCH_ABORT 3
36: #define EXCP_DATA_ABORT 4
1.1.1.2 root 37: #define EXCP_IRQ 5
38: #define EXCP_FIQ 6
1.1.1.3 root 39: #define EXCP_BKPT 7
1.1 root 40:
41: /* We currently assume float and double are IEEE single and double
42: precision respectively.
43: Doing runtime conversions is tricky because VFP registers may contain
44: integer values (eg. as the result of a FTOSI instruction).
45: s<2n> maps to the least significant half of d<n>
46: s<2n+1> maps to the most significant half of d<n>
47: */
48:
49: typedef struct CPUARMState {
1.1.1.2 root 50: /* Regs for current mode. */
1.1 root 51: uint32_t regs[16];
1.1.1.2 root 52: /* Frequently accessed CPSR bits are stored separately for efficiently.
1.1.1.4 ! root 53: This contains all the other bits. Use cpsr_{read,write} to access
1.1.1.2 root 54: the whole CPSR. */
55: uint32_t uncached_cpsr;
56: uint32_t spsr;
57:
58: /* Banked registers. */
59: uint32_t banked_spsr[6];
60: uint32_t banked_r13[6];
61: uint32_t banked_r14[6];
62:
63: /* These hold r8-r12. */
64: uint32_t usr_regs[5];
65: uint32_t fiq_regs[5];
1.1 root 66:
67: /* cpsr flag cache for faster execution */
68: uint32_t CF; /* 0 or 1 */
69: uint32_t VF; /* V is the bit 31. All other bits are undefined */
70: uint32_t NZF; /* N is bit 31. Z is computed from NZF */
71: uint32_t QF; /* 0 or 1 */
72:
73: int thumb; /* 0 = arm mode, 1 = thumb mode */
74:
1.1.1.2 root 75: /* System control coprocessor (cp15) */
76: struct {
1.1.1.3 root 77: uint32_t c0_cpuid;
1.1.1.2 root 78: uint32_t c1_sys; /* System control register. */
79: uint32_t c1_coproc; /* Coprocessor access register. */
80: uint32_t c2; /* MMU translation table base. */
81: uint32_t c3; /* MMU domain access control register. */
82: uint32_t c5_insn; /* Fault status registers. */
83: uint32_t c5_data;
84: uint32_t c6_insn; /* Fault address registers. */
85: uint32_t c6_data;
86: uint32_t c9_insn; /* Cache lockdown registers. */
87: uint32_t c9_data;
88: uint32_t c13_fcse; /* FCSE PID. */
89: uint32_t c13_context; /* Context ID. */
90: } cp15;
1.1.1.3 root 91:
92: /* Internal CPU feature flags. */
93: uint32_t features;
94:
1.1 root 95: /* exception/interrupt handling */
96: jmp_buf jmp_env;
97: int exception_index;
98: int interrupt_request;
99: int user_mode_only;
1.1.1.2 root 100: int halted;
1.1 root 101:
102: /* VFP coprocessor state. */
103: struct {
104: float64 regs[16];
105:
1.1.1.3 root 106: uint32_t xregs[16];
1.1 root 107: /* We store these fpcsr fields separately for convenience. */
108: int vec_len;
109: int vec_stride;
110:
111: /* Temporary variables if we don't have spare fp regs. */
112: float32 tmp0s, tmp1s;
113: float64 tmp0d, tmp1d;
114:
115: float_status fp_status;
116: } vfp;
117:
1.1.1.3 root 118: #if defined(CONFIG_USER_ONLY)
119: /* For usermode syscall translation. */
120: int eabi;
121: #endif
122:
1.1.1.2 root 123: CPU_COMMON
124:
1.1 root 125: } CPUARMState;
126:
127: CPUARMState *cpu_arm_init(void);
128: int cpu_arm_exec(CPUARMState *s);
129: void cpu_arm_close(CPUARMState *s);
1.1.1.2 root 130: void do_interrupt(CPUARMState *);
131: void switch_mode(CPUARMState *, int);
132:
1.1 root 133: /* you can call this signal handler from your SIGBUS and SIGSEGV
134: signal handlers to inform the virtual CPU of exceptions. non zero
135: is returned if the signal was handled by the virtual CPU. */
1.1.1.4 ! root 136: int cpu_arm_signal_handler(int host_signum, void *pinfo,
1.1 root 137: void *puc);
138:
1.1.1.2 root 139: #define CPSR_M (0x1f)
140: #define CPSR_T (1 << 5)
141: #define CPSR_F (1 << 6)
142: #define CPSR_I (1 << 7)
143: #define CPSR_A (1 << 8)
144: #define CPSR_E (1 << 9)
145: #define CPSR_IT_2_7 (0xfc00)
146: /* Bits 20-23 reserved. */
147: #define CPSR_J (1 << 24)
148: #define CPSR_IT_0_1 (3 << 25)
149: #define CPSR_Q (1 << 27)
150: #define CPSR_NZCV (0xf << 28)
151:
152: #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
153: /* Return the current CPSR value. */
154: static inline uint32_t cpsr_read(CPUARMState *env)
155: {
156: int ZF;
157: ZF = (env->NZF == 0);
158: return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
159: (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
160: | (env->thumb << 5);
161: }
162:
163: /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
164: static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
165: {
166: /* NOTE: N = 1 and Z = 1 cannot be stored currently */
167: if (mask & CPSR_NZCV) {
168: env->NZF = (val & 0xc0000000) ^ 0x40000000;
169: env->CF = (val >> 29) & 1;
170: env->VF = (val << 3) & 0x80000000;
171: }
172: if (mask & CPSR_Q)
173: env->QF = ((val & CPSR_Q) != 0);
174: if (mask & CPSR_T)
175: env->thumb = ((val & CPSR_T) != 0);
176:
177: if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
178: switch_mode(env, val & CPSR_M);
179: }
180: mask &= ~CACHED_CPSR_BITS;
181: env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
182: }
183:
184: enum arm_cpu_mode {
185: ARM_CPU_MODE_USR = 0x10,
186: ARM_CPU_MODE_FIQ = 0x11,
187: ARM_CPU_MODE_IRQ = 0x12,
188: ARM_CPU_MODE_SVC = 0x13,
189: ARM_CPU_MODE_ABT = 0x17,
190: ARM_CPU_MODE_UND = 0x1b,
191: ARM_CPU_MODE_SYS = 0x1f
192: };
193:
1.1.1.3 root 194: /* VFP system registers. */
195: #define ARM_VFP_FPSID 0
196: #define ARM_VFP_FPSCR 1
197: #define ARM_VFP_FPEXC 8
198: #define ARM_VFP_FPINST 9
199: #define ARM_VFP_FPINST2 10
200:
201:
202: enum arm_features {
203: ARM_FEATURE_VFP,
204: ARM_FEATURE_AUXCR /* ARM1026 Auxiliary control register. */
205: };
206:
207: static inline int arm_feature(CPUARMState *env, int feature)
208: {
209: return (env->features & (1u << feature)) != 0;
210: }
211:
212: void cpu_arm_set_model(CPUARMState *env, uint32_t id);
213:
214: #define ARM_CPUID_ARM1026 0x4106a262
215: #define ARM_CPUID_ARM926 0x41069265
216:
1.1.1.2 root 217: #if defined(CONFIG_USER_ONLY)
1.1 root 218: #define TARGET_PAGE_BITS 12
1.1.1.2 root 219: #else
220: /* The ARM MMU allows 1k pages. */
221: /* ??? Linux doesn't actually use these, and they're deprecated in recent
222: architecture revisions. Maybe an a configure option to disable them. */
223: #define TARGET_PAGE_BITS 10
224: #endif
1.1 root 225: #include "cpu-all.h"
226:
227: #endif
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