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1.1 root 1: /*
2: * ARM virtual CPU header
1.1.1.5 root 3: *
1.1 root 4: * Copyright (c) 2003 Fabrice Bellard
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.7 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #ifndef CPU_ARM_H
20: #define CPU_ARM_H
21:
22: #define TARGET_LONG_BITS 32
23:
1.1.1.4 root 24: #define ELF_MACHINE EM_ARM
25:
1.1.1.7 root 26: #define CPUState struct CPUARMState
27:
1.1 root 28: #include "cpu-defs.h"
29:
30: #include "softfloat.h"
31:
32: #define TARGET_HAS_ICE 1
33:
34: #define EXCP_UDEF 1 /* undefined instruction */
35: #define EXCP_SWI 2 /* software interrupt */
36: #define EXCP_PREFETCH_ABORT 3
37: #define EXCP_DATA_ABORT 4
1.1.1.2 root 38: #define EXCP_IRQ 5
39: #define EXCP_FIQ 6
1.1.1.3 root 40: #define EXCP_BKPT 7
1.1.1.5 root 41: #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
1.1.1.6 root 42: #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
1.1.1.8 root 43: #define EXCP_STREX 10
1.1.1.5 root 44:
45: #define ARMV7M_EXCP_RESET 1
46: #define ARMV7M_EXCP_NMI 2
47: #define ARMV7M_EXCP_HARD 3
48: #define ARMV7M_EXCP_MEM 4
49: #define ARMV7M_EXCP_BUS 5
50: #define ARMV7M_EXCP_USAGE 6
51: #define ARMV7M_EXCP_SVC 11
52: #define ARMV7M_EXCP_DEBUG 12
53: #define ARMV7M_EXCP_PENDSV 14
54: #define ARMV7M_EXCP_SYSTICK 15
55:
56: typedef void ARMWriteCPFunc(void *opaque, int cp_info,
57: int srcreg, int operand, uint32_t value);
58: typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
59: int dstreg, int operand);
60:
1.1.1.6 root 61: struct arm_boot_info;
62:
1.1.1.5 root 63: #define NB_MMU_MODES 2
1.1 root 64:
65: /* We currently assume float and double are IEEE single and double
66: precision respectively.
67: Doing runtime conversions is tricky because VFP registers may contain
68: integer values (eg. as the result of a FTOSI instruction).
69: s<2n> maps to the least significant half of d<n>
70: s<2n+1> maps to the most significant half of d<n>
71: */
72:
73: typedef struct CPUARMState {
1.1.1.2 root 74: /* Regs for current mode. */
1.1 root 75: uint32_t regs[16];
1.1.1.2 root 76: /* Frequently accessed CPSR bits are stored separately for efficiently.
1.1.1.4 root 77: This contains all the other bits. Use cpsr_{read,write} to access
1.1.1.2 root 78: the whole CPSR. */
79: uint32_t uncached_cpsr;
80: uint32_t spsr;
81:
82: /* Banked registers. */
83: uint32_t banked_spsr[6];
84: uint32_t banked_r13[6];
85: uint32_t banked_r14[6];
1.1.1.5 root 86:
1.1.1.2 root 87: /* These hold r8-r12. */
88: uint32_t usr_regs[5];
89: uint32_t fiq_regs[5];
1.1.1.5 root 90:
1.1 root 91: /* cpsr flag cache for faster execution */
92: uint32_t CF; /* 0 or 1 */
93: uint32_t VF; /* V is the bit 31. All other bits are undefined */
1.1.1.6 root 94: uint32_t NF; /* N is bit 31. All other bits are undefined. */
95: uint32_t ZF; /* Z set if zero. */
1.1 root 96: uint32_t QF; /* 0 or 1 */
1.1.1.5 root 97: uint32_t GE; /* cpsr[19:16] */
1.1.1.6 root 98: uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
1.1.1.5 root 99: uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
1.1 root 100:
1.1.1.2 root 101: /* System control coprocessor (cp15) */
102: struct {
1.1.1.3 root 103: uint32_t c0_cpuid;
1.1.1.5 root 104: uint32_t c0_cachetype;
1.1.1.6 root 105: uint32_t c0_ccsid[16]; /* Cache size. */
106: uint32_t c0_clid; /* Cache level. */
107: uint32_t c0_cssel; /* Cache size selection. */
1.1.1.5 root 108: uint32_t c0_c1[8]; /* Feature registers. */
109: uint32_t c0_c2[8]; /* Instruction set registers. */
1.1.1.2 root 110: uint32_t c1_sys; /* System control register. */
111: uint32_t c1_coproc; /* Coprocessor access register. */
1.1.1.5 root 112: uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
113: uint32_t c2_base0; /* MMU translation table base 0. */
114: uint32_t c2_base1; /* MMU translation table base 1. */
1.1.1.6 root 115: uint32_t c2_control; /* MMU translation table base control. */
116: uint32_t c2_mask; /* MMU translation table base selection mask. */
117: uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
1.1.1.5 root 118: uint32_t c2_data; /* MPU data cachable bits. */
119: uint32_t c2_insn; /* MPU instruction cachable bits. */
120: uint32_t c3; /* MMU domain access control register
121: MPU write buffer control. */
1.1.1.2 root 122: uint32_t c5_insn; /* Fault status registers. */
123: uint32_t c5_data;
1.1.1.5 root 124: uint32_t c6_region[8]; /* MPU base/size registers. */
1.1.1.2 root 125: uint32_t c6_insn; /* Fault address registers. */
126: uint32_t c6_data;
127: uint32_t c9_insn; /* Cache lockdown registers. */
128: uint32_t c9_data;
129: uint32_t c13_fcse; /* FCSE PID. */
130: uint32_t c13_context; /* Context ID. */
1.1.1.5 root 131: uint32_t c13_tls1; /* User RW Thread register. */
132: uint32_t c13_tls2; /* User RO Thread register. */
133: uint32_t c13_tls3; /* Privileged Thread register. */
134: uint32_t c15_cpar; /* XScale Coprocessor Access Register */
135: uint32_t c15_ticonfig; /* TI925T configuration byte. */
136: uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
137: uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
138: uint32_t c15_threadid; /* TI debugger thread-ID. */
1.1.1.2 root 139: } cp15;
1.1.1.3 root 140:
1.1.1.5 root 141: struct {
142: uint32_t other_sp;
143: uint32_t vecbase;
144: uint32_t basepri;
145: uint32_t control;
146: int current_sp;
147: int exception;
148: int pending_exception;
149: } v7m;
150:
1.1.1.6 root 151: /* Thumb-2 EE state. */
152: uint32_t teecr;
153: uint32_t teehbr;
154:
1.1.1.3 root 155: /* Internal CPU feature flags. */
156: uint32_t features;
157:
1.1.1.5 root 158: /* Callback for vectored interrupt controller. */
159: int (*get_irq_vector)(struct CPUARMState *);
160: void *irq_opaque;
161:
1.1 root 162: /* VFP coprocessor state. */
163: struct {
1.1.1.5 root 164: float64 regs[32];
1.1 root 165:
1.1.1.3 root 166: uint32_t xregs[16];
1.1 root 167: /* We store these fpcsr fields separately for convenience. */
168: int vec_len;
169: int vec_stride;
170:
1.1.1.5 root 171: /* scratch space when Tn are not sufficient. */
172: uint32_t scratch[8];
173:
1.1 root 174: float_status fp_status;
175: } vfp;
1.1.1.8 root 176: uint32_t exclusive_addr;
177: uint32_t exclusive_val;
178: uint32_t exclusive_high;
1.1.1.5 root 179: #if defined(CONFIG_USER_ONLY)
1.1.1.8 root 180: uint32_t exclusive_test;
181: uint32_t exclusive_info;
1.1.1.5 root 182: #endif
183:
184: /* iwMMXt coprocessor state. */
185: struct {
186: uint64_t regs[16];
187: uint64_t val;
188:
189: uint32_t cregs[16];
190: } iwmmxt;
1.1 root 191:
1.1.1.3 root 192: #if defined(CONFIG_USER_ONLY)
193: /* For usermode syscall translation. */
194: int eabi;
195: #endif
196:
1.1.1.2 root 197: CPU_COMMON
198:
1.1.1.5 root 199: /* These fields after the common ones so they are preserved on reset. */
1.1.1.9 ! root 200:
! 201: /* Coprocessor IO used by peripherals */
! 202: struct {
! 203: ARMReadCPFunc *cp_read;
! 204: ARMWriteCPFunc *cp_write;
! 205: void *opaque;
! 206: } cp[15];
! 207: void *nvic;
1.1.1.6 root 208: struct arm_boot_info *boot_info;
1.1 root 209: } CPUARMState;
210:
1.1.1.5 root 211: CPUARMState *cpu_arm_init(const char *cpu_model);
1.1.1.6 root 212: void arm_translate_init(void);
1.1 root 213: int cpu_arm_exec(CPUARMState *s);
214: void cpu_arm_close(CPUARMState *s);
1.1.1.2 root 215: void do_interrupt(CPUARMState *);
216: void switch_mode(CPUARMState *, int);
1.1.1.5 root 217: uint32_t do_arm_semihosting(CPUARMState *env);
1.1.1.2 root 218:
1.1 root 219: /* you can call this signal handler from your SIGBUS and SIGSEGV
220: signal handlers to inform the virtual CPU of exceptions. non zero
221: is returned if the signal was handled by the virtual CPU. */
1.1.1.5 root 222: int cpu_arm_signal_handler(int host_signum, void *pinfo,
1.1 root 223: void *puc);
1.1.1.6 root 224: int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
225: int mmu_idx, int is_softmuu);
1.1.1.8 root 226: #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
1.1 root 227:
1.1.1.5 root 228: void cpu_lock(void);
229: void cpu_unlock(void);
1.1.1.6 root 230: static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
231: {
232: env->cp15.c13_tls2 = newtls;
233: }
1.1.1.5 root 234:
1.1.1.2 root 235: #define CPSR_M (0x1f)
236: #define CPSR_T (1 << 5)
237: #define CPSR_F (1 << 6)
238: #define CPSR_I (1 << 7)
239: #define CPSR_A (1 << 8)
240: #define CPSR_E (1 << 9)
241: #define CPSR_IT_2_7 (0xfc00)
1.1.1.5 root 242: #define CPSR_GE (0xf << 16)
243: #define CPSR_RESERVED (0xf << 20)
1.1.1.2 root 244: #define CPSR_J (1 << 24)
245: #define CPSR_IT_0_1 (3 << 25)
246: #define CPSR_Q (1 << 27)
1.1.1.5 root 247: #define CPSR_V (1 << 28)
248: #define CPSR_C (1 << 29)
249: #define CPSR_Z (1 << 30)
250: #define CPSR_N (1 << 31)
251: #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
252:
253: #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
254: #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
255: /* Bits writable in user mode. */
256: #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
257: /* Execution state bits. MRS read as zero, MSR writes ignored. */
258: #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
1.1.1.2 root 259:
260: /* Return the current CPSR value. */
1.1.1.5 root 261: uint32_t cpsr_read(CPUARMState *env);
262: /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
263: void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
264:
265: /* Return the current xPSR value. */
266: static inline uint32_t xpsr_read(CPUARMState *env)
1.1.1.2 root 267: {
268: int ZF;
1.1.1.6 root 269: ZF = (env->ZF == 0);
270: return (env->NF & 0x80000000) | (ZF << 30)
1.1.1.5 root 271: | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
272: | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
273: | ((env->condexec_bits & 0xfc) << 8)
274: | env->v7m.exception;
1.1.1.2 root 275: }
276:
1.1.1.5 root 277: /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
278: static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1.1.1.2 root 279: {
280: if (mask & CPSR_NZCV) {
1.1.1.6 root 281: env->ZF = (~val) & CPSR_Z;
282: env->NF = val;
1.1.1.2 root 283: env->CF = (val >> 29) & 1;
284: env->VF = (val << 3) & 0x80000000;
285: }
286: if (mask & CPSR_Q)
287: env->QF = ((val & CPSR_Q) != 0);
1.1.1.5 root 288: if (mask & (1 << 24))
289: env->thumb = ((val & (1 << 24)) != 0);
290: if (mask & CPSR_IT_0_1) {
291: env->condexec_bits &= ~3;
292: env->condexec_bits |= (val >> 25) & 3;
293: }
294: if (mask & CPSR_IT_2_7) {
295: env->condexec_bits &= 3;
296: env->condexec_bits |= (val >> 8) & 0xfc;
297: }
298: if (mask & 0x1ff) {
299: env->v7m.exception = val & 0x1ff;
1.1.1.2 root 300: }
301: }
302:
303: enum arm_cpu_mode {
304: ARM_CPU_MODE_USR = 0x10,
305: ARM_CPU_MODE_FIQ = 0x11,
306: ARM_CPU_MODE_IRQ = 0x12,
307: ARM_CPU_MODE_SVC = 0x13,
308: ARM_CPU_MODE_ABT = 0x17,
309: ARM_CPU_MODE_UND = 0x1b,
310: ARM_CPU_MODE_SYS = 0x1f
311: };
312:
1.1.1.3 root 313: /* VFP system registers. */
314: #define ARM_VFP_FPSID 0
315: #define ARM_VFP_FPSCR 1
1.1.1.5 root 316: #define ARM_VFP_MVFR1 6
317: #define ARM_VFP_MVFR0 7
1.1.1.3 root 318: #define ARM_VFP_FPEXC 8
319: #define ARM_VFP_FPINST 9
320: #define ARM_VFP_FPINST2 10
321:
1.1.1.5 root 322: /* iwMMXt coprocessor control registers. */
323: #define ARM_IWMMXT_wCID 0
324: #define ARM_IWMMXT_wCon 1
325: #define ARM_IWMMXT_wCSSF 2
326: #define ARM_IWMMXT_wCASF 3
327: #define ARM_IWMMXT_wCGR0 8
328: #define ARM_IWMMXT_wCGR1 9
329: #define ARM_IWMMXT_wCGR2 10
330: #define ARM_IWMMXT_wCGR3 11
1.1.1.3 root 331:
332: enum arm_features {
333: ARM_FEATURE_VFP,
1.1.1.5 root 334: ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
335: ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
336: ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
337: ARM_FEATURE_V6,
338: ARM_FEATURE_V6K,
339: ARM_FEATURE_V7,
340: ARM_FEATURE_THUMB2,
341: ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
342: ARM_FEATURE_VFP3,
1.1.1.8 root 343: ARM_FEATURE_VFP_FP16,
1.1.1.5 root 344: ARM_FEATURE_NEON,
345: ARM_FEATURE_DIV,
346: ARM_FEATURE_M, /* Microcontroller profile. */
1.1.1.6 root 347: ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
348: ARM_FEATURE_THUMB2EE
1.1.1.3 root 349: };
350:
351: static inline int arm_feature(CPUARMState *env, int feature)
352: {
353: return (env->features & (1u << feature)) != 0;
354: }
355:
1.1.1.5 root 356: void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1.1.1.3 root 357:
1.1.1.5 root 358: /* Interface between CPU and Interrupt controller. */
359: void armv7m_nvic_set_pending(void *opaque, int irq);
360: int armv7m_nvic_acknowledge_irq(void *opaque);
361: void armv7m_nvic_complete_irq(void *opaque, int irq);
362:
363: void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
364: ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
365: void *opaque);
366:
367: /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
368: Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
369: conventional cores (ie. Application or Realtime profile). */
370:
371: #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
372: #define ARM_CPUID(env) (env->cp15.c0_cpuid)
373:
374: #define ARM_CPUID_ARM1026 0x4106a262
375: #define ARM_CPUID_ARM926 0x41069265
376: #define ARM_CPUID_ARM946 0x41059461
377: #define ARM_CPUID_TI915T 0x54029152
378: #define ARM_CPUID_TI925T 0x54029252
379: #define ARM_CPUID_PXA250 0x69052100
380: #define ARM_CPUID_PXA255 0x69052d00
381: #define ARM_CPUID_PXA260 0x69052903
382: #define ARM_CPUID_PXA261 0x69052d05
383: #define ARM_CPUID_PXA262 0x69052d06
384: #define ARM_CPUID_PXA270 0x69054110
385: #define ARM_CPUID_PXA270_A0 0x69054110
386: #define ARM_CPUID_PXA270_A1 0x69054111
387: #define ARM_CPUID_PXA270_B0 0x69054112
388: #define ARM_CPUID_PXA270_B1 0x69054113
389: #define ARM_CPUID_PXA270_C0 0x69054114
390: #define ARM_CPUID_PXA270_C5 0x69054117
391: #define ARM_CPUID_ARM1136 0x4117b363
1.1.1.6 root 392: #define ARM_CPUID_ARM1136_R2 0x4107b362
1.1.1.5 root 393: #define ARM_CPUID_ARM11MPCORE 0x410fb022
394: #define ARM_CPUID_CORTEXA8 0x410fc080
1.1.1.8 root 395: #define ARM_CPUID_CORTEXA9 0x410fc090
1.1.1.5 root 396: #define ARM_CPUID_CORTEXM3 0x410fc231
397: #define ARM_CPUID_ANY 0xffffffff
1.1.1.3 root 398:
1.1.1.2 root 399: #if defined(CONFIG_USER_ONLY)
1.1 root 400: #define TARGET_PAGE_BITS 12
1.1.1.2 root 401: #else
402: /* The ARM MMU allows 1k pages. */
403: /* ??? Linux doesn't actually use these, and they're deprecated in recent
1.1.1.5 root 404: architecture revisions. Maybe a configure option to disable them. */
1.1.1.2 root 405: #define TARGET_PAGE_BITS 10
406: #endif
1.1.1.5 root 407:
1.1.1.9 ! root 408: #define TARGET_PHYS_ADDR_SPACE_BITS 32
! 409: #define TARGET_VIRT_ADDR_SPACE_BITS 32
! 410:
1.1.1.5 root 411: #define cpu_init cpu_arm_init
412: #define cpu_exec cpu_arm_exec
413: #define cpu_gen_code cpu_arm_gen_code
414: #define cpu_signal_handler cpu_arm_signal_handler
415: #define cpu_list arm_cpu_list
416:
1.1.1.8 root 417: #define CPU_SAVE_VERSION 2
1.1.1.5 root 418:
419: /* MMU modes definitions */
420: #define MMU_MODE0_SUFFIX _kernel
421: #define MMU_MODE1_SUFFIX _user
422: #define MMU_USER_IDX 1
423: static inline int cpu_mmu_index (CPUState *env)
424: {
425: return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
426: }
427:
1.1.1.6 root 428: #if defined(CONFIG_USER_ONLY)
429: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
430: {
431: if (newsp)
432: env->regs[13] = newsp;
433: env->regs[0] = 0;
434: }
435: #endif
436:
1.1 root 437: #include "cpu-all.h"
1.1.1.6 root 438:
439: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
440: target_ulong *cs_base, int *flags)
441: {
442: *pc = env->regs[15];
443: *cs_base = 0;
444: *flags = env->thumb | (env->vfp.vec_len << 1)
445: | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8);
446: if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
447: *flags |= (1 << 6);
448: if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
449: *flags |= (1 << 7);
450: }
1.1 root 451:
452: #endif
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