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1.1 root 1: /*
2: * CRIS virtual CPU header
3: *
4: * Copyright (c) 2007 AXIS Communications AB
5: * Written by Edgar E. Iglesias
6: *
7: * This library is free software; you can redistribute it and/or
8: * modify it under the terms of the GNU Lesser General Public
9: * License as published by the Free Software Foundation; either
10: * version 2 of the License, or (at your option) any later version.
11: *
12: * This library is distributed in the hope that it will be useful,
13: * but WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15: * General Public License for more details.
16: *
17: * You should have received a copy of the GNU Lesser General Public
18: * License along with this library; if not, write to the Free Software
19: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20: */
21: #ifndef CPU_CRIS_H
22: #define CPU_CRIS_H
23:
24: #define TARGET_LONG_BITS 32
25:
26: #include "cpu-defs.h"
27:
28: #include "softfloat.h"
29:
30: #define TARGET_HAS_ICE 1
31:
32: #define ELF_MACHINE EM_CRIS
33:
34: #define EXCP_MMU_EXEC 0
35: #define EXCP_MMU_READ 1
36: #define EXCP_MMU_WRITE 2
37: #define EXCP_MMU_FLUSH 3
38: #define EXCP_MMU_MISS 4
39: #define EXCP_BREAK 16 /* trap. */
40:
41: /* CPU flags. */
42: #define S_FLAG 0x200
43: #define R_FLAG 0x100
44: #define P_FLAG 0x80
45: #define U_FLAG 0x40
46: #define P_FLAG 0x80
47: #define U_FLAG 0x40
48: #define I_FLAG 0x20
49: #define X_FLAG 0x10
50: #define N_FLAG 0x08
51: #define Z_FLAG 0x04
52: #define V_FLAG 0x02
53: #define C_FLAG 0x01
54: #define ALU_FLAGS 0x1F
55:
56: /* Condition codes. */
57: #define CC_CC 0
58: #define CC_CS 1
59: #define CC_NE 2
60: #define CC_EQ 3
61: #define CC_VC 4
62: #define CC_VS 5
63: #define CC_PL 6
64: #define CC_MI 7
65: #define CC_LS 8
66: #define CC_HI 9
67: #define CC_GE 10
68: #define CC_LT 11
69: #define CC_GT 12
70: #define CC_LE 13
71: #define CC_A 14
72: #define CC_P 15
73:
74: /* Internal flags for the implementation. */
75: #define F_DELAYSLOT 1
76:
77: #define NB_MMU_MODES 2
78:
79: typedef struct CPUCRISState {
80: uint32_t debug1;
81: uint32_t debug2;
82: uint32_t debug3;
83:
84: /*
85: * We just store the stores to the tlbset here for later evaluation
86: * when the hw needs access to them.
87: *
88: * One for I and another for D.
89: */
90: struct
91: {
92: uint32_t hi;
93: uint32_t lo;
94: } tlbsets[2][4][16];
95:
96: uint32_t sregs[256][16]; /* grrr why so many?? */
97: uint32_t regs[16];
98: uint32_t pregs[16];
99: uint32_t pc;
100: uint32_t sr;
101: uint32_t flag_mask; /* Per insn mask of affected flags. */
102:
103: /* SSP and USP. */
104: int current_sp;
105: uint32_t sp[2];
106:
107: /* These are setup up by the guest code just before transfering the
108: control back to the host. */
109: int jmp;
110: uint32_t btarget;
111: int btaken;
112:
113: /* for traps. */
114: int trapnr;
115:
116: /* Condition flag tracking. */
117: uint32_t cc_op;
118: uint32_t cc_mask;
119: uint32_t cc_dest;
120: uint32_t cc_src;
121: uint32_t cc_result;
122:
123: /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
124: int cc_size;
125:
126: /* extended arithmetics. */
127: int cc_x_live;
128: int cc_x;
129:
130: int features;
131:
132: uint64_t pending_interrupts;
133: int interrupt_request;
134: int exception_index;
135: int user_mode_only;
136: int halted;
137:
138: struct
139: {
140: int exec_insns;
141: int exec_loads;
142: int exec_stores;
143: } stats;
144:
145:
146: jmp_buf jmp_env;
147: CPU_COMMON
148: } CPUCRISState;
149:
150: CPUCRISState *cpu_cris_init(const char *cpu_model);
151: int cpu_cris_exec(CPUCRISState *s);
152: void cpu_cris_close(CPUCRISState *s);
153: void do_interrupt(CPUCRISState *env);
154: /* you can call this signal handler from your SIGBUS and SIGSEGV
155: signal handlers to inform the virtual CPU of exceptions. non zero
156: is returned if the signal was handled by the virtual CPU. */
157: int cpu_cris_signal_handler(int host_signum, void *pinfo,
158: void *puc);
159: void cpu_cris_flush_flags(CPUCRISState *, int);
160:
161:
162: void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
163: int is_asi);
164:
165: enum {
166: CC_OP_DYNAMIC, /* Use env->cc_op */
167: CC_OP_FLAGS,
168: CC_OP_LOGIC,
169: CC_OP_CMP,
170: CC_OP_MOVE,
171: CC_OP_MOVE_PD,
172: CC_OP_MOVE_SD,
173: CC_OP_ADD,
174: CC_OP_ADDC,
175: CC_OP_MCP,
176: CC_OP_ADDU,
177: CC_OP_SUB,
178: CC_OP_SUBU,
179: CC_OP_NEG,
180: CC_OP_BTST,
181: CC_OP_MULS,
182: CC_OP_MULU,
183: CC_OP_DSTEP,
184: CC_OP_BOUND,
185:
186: CC_OP_OR,
187: CC_OP_AND,
188: CC_OP_XOR,
189: CC_OP_LSL,
190: CC_OP_LSR,
191: CC_OP_ASR,
192: CC_OP_LZ
193: };
194:
195: #define CCF_C 0x01
196: #define CCF_V 0x02
197: #define CCF_Z 0x04
198: #define CCF_N 0x08
199: #define CCF_X 0x10
200:
201: #define CRIS_SSP 0
202: #define CRIS_USP 1
203:
204: void cris_set_irq_level(CPUCRISState *env, int level, uint8_t vector);
205: void cris_set_macsr(CPUCRISState *env, uint32_t val);
206: void cris_switch_sp(CPUCRISState *env);
207:
208: void do_cris_semihosting(CPUCRISState *env, int nr);
209:
210: enum cris_features {
211: CRIS_FEATURE_CF_ISA_MUL,
212: };
213:
214: static inline int cris_feature(CPUCRISState *env, int feature)
215: {
216: return (env->features & (1u << feature)) != 0;
217: }
218:
219: void register_cris_insns (CPUCRISState *env);
220:
221: /* CRIS uses 8k pages. */
222: #define TARGET_PAGE_BITS 13
223:
224: #define CPUState CPUCRISState
225: #define cpu_init cpu_cris_init
226: #define cpu_exec cpu_cris_exec
227: #define cpu_gen_code cpu_cris_gen_code
228: #define cpu_signal_handler cpu_cris_signal_handler
229:
230: /* MMU modes definitions */
231: #define MMU_MODE0_SUFFIX _kernel
232: #define MMU_MODE1_SUFFIX _user
233: #define MMU_USER_IDX 1
234: /* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */
235: static inline int cpu_mmu_index (CPUState *env)
236: {
237: return 0;
238: }
239:
240: #include "cpu-all.h"
241:
242: /* Register aliases. */
243: #define REG_SP 14
244: #define REG_ACR 15
245: #define REG_MOF 7
246:
247: /* Support regs. */
248: #define SR_PID 2
249: #define SR_SRS 3
250: #define SR_EBP 9
251: #define SR_ERP 10
252: #define SR_CCS 13
253:
254: /* Support func regs. */
255: #define SFR_RW_GC_CFG 0][0
256: #define SFR_RW_MM_CFG 1][0
257: #define SFR_RW_MM_KBASE_LO 1][1
258: #define SFR_RW_MM_KBASE_HI 1][2
259: #define SFR_R_MM_CAUSE 1][3
260: #define SFR_RW_MM_TLB_SEL 1][4
261: #define SFR_RW_MM_TLB_LO 1][5
262: #define SFR_RW_MM_TLB_HI 1][6
263:
264: #endif
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