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1.1 root 1: /*
2: * CRIS virtual CPU header
3: *
4: * Copyright (c) 2007 AXIS Communications AB
5: * Written by Edgar E. Iglesias
6: *
7: * This library is free software; you can redistribute it and/or
8: * modify it under the terms of the GNU Lesser General Public
9: * License as published by the Free Software Foundation; either
10: * version 2 of the License, or (at your option) any later version.
11: *
12: * This library is distributed in the hope that it will be useful,
13: * but WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15: * General Public License for more details.
16: *
17: * You should have received a copy of the GNU Lesser General Public
1.1.1.3 root 18: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 19: */
20: #ifndef CPU_CRIS_H
21: #define CPU_CRIS_H
22:
23: #define TARGET_LONG_BITS 32
24:
1.1.1.3 root 25: #define CPUState struct CPUCRISState
26:
1.1 root 27: #include "cpu-defs.h"
28:
29: #define TARGET_HAS_ICE 1
30:
31: #define ELF_MACHINE EM_CRIS
32:
1.1.1.2 root 33: #define EXCP_NMI 1
34: #define EXCP_GURU 2
35: #define EXCP_BUSFAULT 3
36: #define EXCP_IRQ 4
37: #define EXCP_BREAK 5
38:
39: /* Register aliases. R0 - R15 */
40: #define R_FP 8
41: #define R_SP 14
42: #define R_ACR 15
43:
44: /* Support regs, P0 - P15 */
45: #define PR_BZ 0
46: #define PR_VR 1
47: #define PR_PID 2
48: #define PR_SRS 3
49: #define PR_WZ 4
50: #define PR_EXS 5
51: #define PR_EDA 6
1.1.1.5 root 52: #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
1.1.1.2 root 53: #define PR_MOF 7
54: #define PR_DZ 8
55: #define PR_EBP 9
56: #define PR_ERP 10
57: #define PR_SRP 11
58: #define PR_NRP 12
59: #define PR_CCS 13
60: #define PR_USP 14
61: #define PR_SPC 15
1.1 root 62:
63: /* CPU flags. */
1.1.1.2 root 64: #define Q_FLAG 0x80000000
65: #define M_FLAG 0x40000000
1.1.1.5 root 66: #define PFIX_FLAG 0x800 /* CRISv10 Only. */
1.1 root 67: #define S_FLAG 0x200
68: #define R_FLAG 0x100
69: #define P_FLAG 0x80
70: #define U_FLAG 0x40
71: #define I_FLAG 0x20
72: #define X_FLAG 0x10
73: #define N_FLAG 0x08
74: #define Z_FLAG 0x04
75: #define V_FLAG 0x02
76: #define C_FLAG 0x01
77: #define ALU_FLAGS 0x1F
78:
79: /* Condition codes. */
80: #define CC_CC 0
81: #define CC_CS 1
82: #define CC_NE 2
83: #define CC_EQ 3
84: #define CC_VC 4
85: #define CC_VS 5
86: #define CC_PL 6
87: #define CC_MI 7
88: #define CC_LS 8
89: #define CC_HI 9
90: #define CC_GE 10
91: #define CC_LT 11
92: #define CC_GT 12
93: #define CC_LE 13
94: #define CC_A 14
95: #define CC_P 15
96:
97: #define NB_MMU_MODES 2
98:
99: typedef struct CPUCRISState {
100: uint32_t regs[16];
1.1.1.2 root 101: /* P0 - P15 are referred to as special registers in the docs. */
1.1 root 102: uint32_t pregs[16];
1.1.1.2 root 103:
104: /* Pseudo register for the PC. Not directly accessable on CRIS. */
1.1 root 105: uint32_t pc;
106:
1.1.1.2 root 107: /* Pseudo register for the kernel stack. */
108: uint32_t ksp;
1.1 root 109:
1.1.1.2 root 110: /* Branch. */
111: int dslot;
112: int btaken;
113: uint32_t btarget;
1.1 root 114:
115: /* Condition flag tracking. */
116: uint32_t cc_op;
117: uint32_t cc_mask;
118: uint32_t cc_dest;
119: uint32_t cc_src;
120: uint32_t cc_result;
121: /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
122: int cc_size;
1.1.1.2 root 123: /* X flag at the time of cc snapshot. */
1.1 root 124: int cc_x;
125:
1.1.1.5 root 126: /* CRIS has certain insns that lockout interrupts. */
127: int locked_irq;
1.1.1.2 root 128: int interrupt_vector;
129: int fault_vector;
130: int trap_vector;
131:
132: /* FIXME: add a check in the translator to avoid writing to support
133: register sets beyond the 4th. The ISA allows up to 256! but in
134: practice there is no core that implements more than 4.
135:
136: Support function registers are used to control units close to the
137: core. Accesses do not pass down the normal hierarchy.
138: */
139: uint32_t sregs[4][16];
140:
141: /* Linear feedback shift reg in the mmu. Used to provide pseudo
142: randomness for the 'hint' the mmu gives to sw for chosing valid
143: sets on TLB refills. */
144: uint32_t mmu_rand_lfsr;
1.1 root 145:
1.1.1.2 root 146: /*
147: * We just store the stores to the tlbset here for later evaluation
148: * when the hw needs access to them.
149: *
150: * One for I and another for D.
151: */
1.1 root 152: struct
153: {
1.1.1.2 root 154: uint32_t hi;
155: uint32_t lo;
156: } tlbsets[2][4][16];
1.1 root 157:
158: CPU_COMMON
1.1.1.6 ! root 159:
! 160: /* Members after CPU_COMMON are preserved across resets. */
! 161: void *load_info;
1.1 root 162: } CPUCRISState;
163:
164: CPUCRISState *cpu_cris_init(const char *cpu_model);
165: int cpu_cris_exec(CPUCRISState *s);
166: void cpu_cris_close(CPUCRISState *s);
167: void do_interrupt(CPUCRISState *env);
168: /* you can call this signal handler from your SIGBUS and SIGSEGV
169: signal handlers to inform the virtual CPU of exceptions. non zero
170: is returned if the signal was handled by the virtual CPU. */
171: int cpu_cris_signal_handler(int host_signum, void *pinfo,
172: void *puc);
173:
174: enum {
175: CC_OP_DYNAMIC, /* Use env->cc_op */
176: CC_OP_FLAGS,
177: CC_OP_CMP,
178: CC_OP_MOVE,
179: CC_OP_ADD,
180: CC_OP_ADDC,
181: CC_OP_MCP,
182: CC_OP_ADDU,
183: CC_OP_SUB,
184: CC_OP_SUBU,
185: CC_OP_NEG,
186: CC_OP_BTST,
187: CC_OP_MULS,
188: CC_OP_MULU,
189: CC_OP_DSTEP,
1.1.1.5 root 190: CC_OP_MSTEP,
1.1 root 191: CC_OP_BOUND,
192:
193: CC_OP_OR,
194: CC_OP_AND,
195: CC_OP_XOR,
196: CC_OP_LSL,
197: CC_OP_LSR,
198: CC_OP_ASR,
199: CC_OP_LZ
200: };
201:
202: /* CRIS uses 8k pages. */
203: #define TARGET_PAGE_BITS 13
1.1.1.2 root 204: #define MMAP_SHIFT TARGET_PAGE_BITS
1.1 root 205:
1.1.1.5 root 206: #define TARGET_PHYS_ADDR_SPACE_BITS 32
207: #define TARGET_VIRT_ADDR_SPACE_BITS 32
208:
1.1 root 209: #define cpu_init cpu_cris_init
210: #define cpu_exec cpu_cris_exec
211: #define cpu_gen_code cpu_cris_gen_code
212: #define cpu_signal_handler cpu_cris_signal_handler
213:
1.1.1.2 root 214: #define CPU_SAVE_VERSION 1
215:
1.1 root 216: /* MMU modes definitions */
217: #define MMU_MODE0_SUFFIX _kernel
218: #define MMU_MODE1_SUFFIX _user
219: #define MMU_USER_IDX 1
220: static inline int cpu_mmu_index (CPUState *env)
221: {
1.1.1.2 root 222: return !!(env->pregs[PR_CCS] & U_FLAG);
1.1 root 223: }
224:
1.1.1.2 root 225: int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
226: int mmu_idx, int is_softmmu);
1.1.1.4 root 227: #define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
1.1 root 228:
1.1.1.2 root 229: #if defined(CONFIG_USER_ONLY)
230: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
231: {
232: if (newsp)
233: env->regs[14] = newsp;
234: env->regs[10] = 0;
235: }
236: #endif
1.1 root 237:
1.1.1.2 root 238: static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
239: {
240: env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
241: }
242:
243: /* Support function regs. */
1.1 root 244: #define SFR_RW_GC_CFG 0][0
1.1.1.2 root 245: #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
246: #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
247: #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
248: #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
249: #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
250: #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
251: #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
252:
253: #include "cpu-all.h"
254:
255: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
256: target_ulong *cs_base, int *flags)
257: {
258: *pc = env->pc;
259: *cs_base = 0;
260: *flags = env->dslot |
1.1.1.5 root 261: (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
262: | X_FLAG | PFIX_FLAG));
1.1.1.2 root 263: }
1.1 root 264:
1.1.1.5 root 265: #define cpu_list cris_cpu_list
1.1.1.6 ! root 266: void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1.1.1.5 root 267:
1.1 root 268: #endif
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