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1.1 root 1: /*
2: * CRIS virtual CPU header
3: *
4: * Copyright (c) 2007 AXIS Communications AB
5: * Written by Edgar E. Iglesias
6: *
7: * This library is free software; you can redistribute it and/or
8: * modify it under the terms of the GNU Lesser General Public
9: * License as published by the Free Software Foundation; either
10: * version 2 of the License, or (at your option) any later version.
11: *
12: * This library is distributed in the hope that it will be useful,
13: * but WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15: * General Public License for more details.
16: *
17: * You should have received a copy of the GNU Lesser General Public
1.1.1.3 root 18: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 19: */
20: #ifndef CPU_CRIS_H
21: #define CPU_CRIS_H
22:
1.1.1.9 ! root 23: #include "config.h"
! 24: #include "qemu-common.h"
! 25:
1.1 root 26: #define TARGET_LONG_BITS 32
27:
1.1.1.9 ! root 28: #define CPUArchState struct CPUCRISState
1.1.1.3 root 29:
1.1 root 30: #include "cpu-defs.h"
31:
32: #define TARGET_HAS_ICE 1
33:
34: #define ELF_MACHINE EM_CRIS
35:
1.1.1.2 root 36: #define EXCP_NMI 1
37: #define EXCP_GURU 2
38: #define EXCP_BUSFAULT 3
39: #define EXCP_IRQ 4
40: #define EXCP_BREAK 5
41:
1.1.1.7 root 42: /* CRIS-specific interrupt pending bits. */
43: #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
44:
1.1.1.2 root 45: /* Register aliases. R0 - R15 */
46: #define R_FP 8
47: #define R_SP 14
48: #define R_ACR 15
49:
50: /* Support regs, P0 - P15 */
51: #define PR_BZ 0
52: #define PR_VR 1
53: #define PR_PID 2
54: #define PR_SRS 3
55: #define PR_WZ 4
56: #define PR_EXS 5
57: #define PR_EDA 6
1.1.1.5 root 58: #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
1.1.1.2 root 59: #define PR_MOF 7
60: #define PR_DZ 8
61: #define PR_EBP 9
62: #define PR_ERP 10
63: #define PR_SRP 11
64: #define PR_NRP 12
65: #define PR_CCS 13
66: #define PR_USP 14
67: #define PR_SPC 15
1.1 root 68:
69: /* CPU flags. */
1.1.1.2 root 70: #define Q_FLAG 0x80000000
71: #define M_FLAG 0x40000000
1.1.1.5 root 72: #define PFIX_FLAG 0x800 /* CRISv10 Only. */
1.1.1.8 root 73: #define F_FLAG_V10 0x400
74: #define P_FLAG_V10 0x200
1.1 root 75: #define S_FLAG 0x200
76: #define R_FLAG 0x100
77: #define P_FLAG 0x80
78: #define U_FLAG 0x40
79: #define I_FLAG 0x20
80: #define X_FLAG 0x10
81: #define N_FLAG 0x08
82: #define Z_FLAG 0x04
83: #define V_FLAG 0x02
84: #define C_FLAG 0x01
85: #define ALU_FLAGS 0x1F
86:
87: /* Condition codes. */
88: #define CC_CC 0
89: #define CC_CS 1
90: #define CC_NE 2
91: #define CC_EQ 3
92: #define CC_VC 4
93: #define CC_VS 5
94: #define CC_PL 6
95: #define CC_MI 7
96: #define CC_LS 8
97: #define CC_HI 9
98: #define CC_GE 10
99: #define CC_LT 11
100: #define CC_GT 12
101: #define CC_LE 13
102: #define CC_A 14
103: #define CC_P 15
104:
105: #define NB_MMU_MODES 2
106:
107: typedef struct CPUCRISState {
108: uint32_t regs[16];
1.1.1.2 root 109: /* P0 - P15 are referred to as special registers in the docs. */
1.1 root 110: uint32_t pregs[16];
1.1.1.2 root 111:
1.1.1.7 root 112: /* Pseudo register for the PC. Not directly accessible on CRIS. */
1.1 root 113: uint32_t pc;
114:
1.1.1.2 root 115: /* Pseudo register for the kernel stack. */
116: uint32_t ksp;
1.1 root 117:
1.1.1.2 root 118: /* Branch. */
119: int dslot;
120: int btaken;
121: uint32_t btarget;
1.1 root 122:
123: /* Condition flag tracking. */
124: uint32_t cc_op;
125: uint32_t cc_mask;
126: uint32_t cc_dest;
127: uint32_t cc_src;
128: uint32_t cc_result;
129: /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
130: int cc_size;
1.1.1.2 root 131: /* X flag at the time of cc snapshot. */
1.1 root 132: int cc_x;
133:
1.1.1.5 root 134: /* CRIS has certain insns that lockout interrupts. */
135: int locked_irq;
1.1.1.2 root 136: int interrupt_vector;
137: int fault_vector;
138: int trap_vector;
139:
140: /* FIXME: add a check in the translator to avoid writing to support
141: register sets beyond the 4th. The ISA allows up to 256! but in
142: practice there is no core that implements more than 4.
143:
144: Support function registers are used to control units close to the
145: core. Accesses do not pass down the normal hierarchy.
146: */
147: uint32_t sregs[4][16];
148:
149: /* Linear feedback shift reg in the mmu. Used to provide pseudo
150: randomness for the 'hint' the mmu gives to sw for chosing valid
151: sets on TLB refills. */
152: uint32_t mmu_rand_lfsr;
1.1 root 153:
1.1.1.2 root 154: /*
155: * We just store the stores to the tlbset here for later evaluation
156: * when the hw needs access to them.
157: *
158: * One for I and another for D.
159: */
1.1 root 160: struct
161: {
1.1.1.2 root 162: uint32_t hi;
163: uint32_t lo;
164: } tlbsets[2][4][16];
1.1 root 165:
166: CPU_COMMON
1.1.1.6 root 167:
168: /* Members after CPU_COMMON are preserved across resets. */
169: void *load_info;
1.1 root 170: } CPUCRISState;
171:
1.1.1.9 ! root 172: #include "cpu-qom.h"
! 173:
1.1 root 174: CPUCRISState *cpu_cris_init(const char *cpu_model);
175: int cpu_cris_exec(CPUCRISState *s);
176: void cpu_cris_close(CPUCRISState *s);
177: void do_interrupt(CPUCRISState *env);
178: /* you can call this signal handler from your SIGBUS and SIGSEGV
179: signal handlers to inform the virtual CPU of exceptions. non zero
180: is returned if the signal was handled by the virtual CPU. */
181: int cpu_cris_signal_handler(int host_signum, void *pinfo,
182: void *puc);
183:
184: enum {
185: CC_OP_DYNAMIC, /* Use env->cc_op */
186: CC_OP_FLAGS,
187: CC_OP_CMP,
188: CC_OP_MOVE,
189: CC_OP_ADD,
190: CC_OP_ADDC,
191: CC_OP_MCP,
192: CC_OP_ADDU,
193: CC_OP_SUB,
194: CC_OP_SUBU,
195: CC_OP_NEG,
196: CC_OP_BTST,
197: CC_OP_MULS,
198: CC_OP_MULU,
199: CC_OP_DSTEP,
1.1.1.5 root 200: CC_OP_MSTEP,
1.1 root 201: CC_OP_BOUND,
202:
203: CC_OP_OR,
204: CC_OP_AND,
205: CC_OP_XOR,
206: CC_OP_LSL,
207: CC_OP_LSR,
208: CC_OP_ASR,
209: CC_OP_LZ
210: };
211:
212: /* CRIS uses 8k pages. */
213: #define TARGET_PAGE_BITS 13
1.1.1.2 root 214: #define MMAP_SHIFT TARGET_PAGE_BITS
1.1 root 215:
1.1.1.5 root 216: #define TARGET_PHYS_ADDR_SPACE_BITS 32
217: #define TARGET_VIRT_ADDR_SPACE_BITS 32
218:
1.1 root 219: #define cpu_init cpu_cris_init
220: #define cpu_exec cpu_cris_exec
221: #define cpu_gen_code cpu_cris_gen_code
222: #define cpu_signal_handler cpu_cris_signal_handler
223:
1.1.1.2 root 224: #define CPU_SAVE_VERSION 1
225:
1.1 root 226: /* MMU modes definitions */
227: #define MMU_MODE0_SUFFIX _kernel
228: #define MMU_MODE1_SUFFIX _user
229: #define MMU_USER_IDX 1
1.1.1.9 ! root 230: static inline int cpu_mmu_index (CPUCRISState *env)
1.1 root 231: {
1.1.1.2 root 232: return !!(env->pregs[PR_CCS] & U_FLAG);
1.1 root 233: }
234:
1.1.1.9 ! root 235: int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
1.1.1.8 root 236: int mmu_idx);
1.1.1.4 root 237: #define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
1.1 root 238:
1.1.1.2 root 239: #if defined(CONFIG_USER_ONLY)
1.1.1.9 ! root 240: static inline void cpu_clone_regs(CPUCRISState *env, target_ulong newsp)
1.1.1.2 root 241: {
242: if (newsp)
243: env->regs[14] = newsp;
244: env->regs[10] = 0;
245: }
246: #endif
1.1 root 247:
1.1.1.2 root 248: static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
249: {
250: env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
251: }
252:
253: /* Support function regs. */
1.1 root 254: #define SFR_RW_GC_CFG 0][0
1.1.1.2 root 255: #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
256: #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
257: #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
258: #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
259: #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
260: #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
261: #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
262:
263: #include "cpu-all.h"
264:
1.1.1.9 ! root 265: static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
1.1.1.2 root 266: target_ulong *cs_base, int *flags)
267: {
268: *pc = env->pc;
269: *cs_base = 0;
270: *flags = env->dslot |
1.1.1.5 root 271: (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
272: | X_FLAG | PFIX_FLAG));
1.1.1.2 root 273: }
1.1 root 274:
1.1.1.5 root 275: #define cpu_list cris_cpu_list
1.1.1.6 root 276: void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1.1.1.5 root 277:
1.1.1.9 ! root 278: static inline bool cpu_has_work(CPUCRISState *env)
1.1.1.7 root 279: {
280: return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
281: }
282:
283: #include "exec-all.h"
284:
1.1.1.9 ! root 285: static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *tb)
1.1.1.7 root 286: {
287: env->pc = tb->pc;
288: }
1.1 root 289: #endif
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