File:  [Qemu by Fabrice Bellard] / qemu / target-cris / cpu.h
Revision 1.1.1.7 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 19:03:27 2018 UTC (3 years, 5 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu1000, qemu0151, HEAD
qemu 0.15.1

    1: /*
    2:  *  CRIS virtual CPU header
    3:  *
    4:  *  Copyright (c) 2007 AXIS Communications AB
    5:  *  Written by Edgar E. Iglesias
    6:  *
    7:  * This library is free software; you can redistribute it and/or
    8:  * modify it under the terms of the GNU Lesser General Public
    9:  * License as published by the Free Software Foundation; either
   10:  * version 2 of the License, or (at your option) any later version.
   11:  *
   12:  * This library is distributed in the hope that it will be useful,
   13:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   14:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   15:  * General Public License for more details.
   16:  *
   17:  * You should have received a copy of the GNU Lesser General Public
   18:  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
   19:  */
   20: #ifndef CPU_CRIS_H
   21: #define CPU_CRIS_H
   22: 
   23: #define TARGET_LONG_BITS 32
   24: 
   25: #define CPUState struct CPUCRISState
   26: 
   27: #include "cpu-defs.h"
   28: 
   29: #define TARGET_HAS_ICE 1
   30: 
   31: #define ELF_MACHINE	EM_CRIS
   32: 
   33: #define EXCP_NMI        1
   34: #define EXCP_GURU       2
   35: #define EXCP_BUSFAULT   3
   36: #define EXCP_IRQ        4
   37: #define EXCP_BREAK      5
   38: 
   39: /* CRIS-specific interrupt pending bits.  */
   40: #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
   41: 
   42: /* Register aliases. R0 - R15 */
   43: #define R_FP  8
   44: #define R_SP  14
   45: #define R_ACR 15
   46: 
   47: /* Support regs, P0 - P15  */
   48: #define PR_BZ  0
   49: #define PR_VR  1
   50: #define PR_PID 2
   51: #define PR_SRS 3
   52: #define PR_WZ  4
   53: #define PR_EXS 5
   54: #define PR_EDA 6
   55: #define PR_PREFIX 6    /* On CRISv10 P6 is reserved, we use it as prefix.  */
   56: #define PR_MOF 7
   57: #define PR_DZ  8
   58: #define PR_EBP 9
   59: #define PR_ERP 10
   60: #define PR_SRP 11
   61: #define PR_NRP 12
   62: #define PR_CCS 13
   63: #define PR_USP 14
   64: #define PR_SPC 15
   65: 
   66: /* CPU flags.  */
   67: #define Q_FLAG 0x80000000
   68: #define M_FLAG 0x40000000
   69: #define PFIX_FLAG 0x800      /* CRISv10 Only.  */
   70: #define S_FLAG 0x200
   71: #define R_FLAG 0x100
   72: #define P_FLAG 0x80
   73: #define U_FLAG 0x40
   74: #define I_FLAG 0x20
   75: #define X_FLAG 0x10
   76: #define N_FLAG 0x08
   77: #define Z_FLAG 0x04
   78: #define V_FLAG 0x02
   79: #define C_FLAG 0x01
   80: #define ALU_FLAGS 0x1F
   81: 
   82: /* Condition codes.  */
   83: #define CC_CC   0
   84: #define CC_CS   1
   85: #define CC_NE   2
   86: #define CC_EQ   3
   87: #define CC_VC   4
   88: #define CC_VS   5
   89: #define CC_PL   6
   90: #define CC_MI   7
   91: #define CC_LS   8
   92: #define CC_HI   9
   93: #define CC_GE  10
   94: #define CC_LT  11
   95: #define CC_GT  12
   96: #define CC_LE  13
   97: #define CC_A   14
   98: #define CC_P   15
   99: 
  100: #define NB_MMU_MODES 2
  101: 
  102: typedef struct CPUCRISState {
  103: 	uint32_t regs[16];
  104: 	/* P0 - P15 are referred to as special registers in the docs.  */
  105: 	uint32_t pregs[16];
  106: 
  107: 	/* Pseudo register for the PC. Not directly accessible on CRIS.  */
  108: 	uint32_t pc;
  109: 
  110: 	/* Pseudo register for the kernel stack.  */
  111: 	uint32_t ksp;
  112: 
  113: 	/* Branch.  */
  114: 	int dslot;
  115: 	int btaken;
  116: 	uint32_t btarget;
  117: 
  118: 	/* Condition flag tracking.  */
  119: 	uint32_t cc_op;
  120: 	uint32_t cc_mask;
  121: 	uint32_t cc_dest;
  122: 	uint32_t cc_src;
  123: 	uint32_t cc_result;
  124: 	/* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
  125: 	int cc_size;
  126: 	/* X flag at the time of cc snapshot.  */
  127: 	int cc_x;
  128: 
  129: 	/* CRIS has certain insns that lockout interrupts.  */
  130: 	int locked_irq;
  131: 	int interrupt_vector;
  132: 	int fault_vector;
  133: 	int trap_vector;
  134: 
  135: 	/* FIXME: add a check in the translator to avoid writing to support
  136: 	   register sets beyond the 4th. The ISA allows up to 256! but in
  137: 	   practice there is no core that implements more than 4.
  138: 
  139: 	   Support function registers are used to control units close to the
  140: 	   core. Accesses do not pass down the normal hierarchy.
  141: 	*/
  142: 	uint32_t sregs[4][16];
  143: 
  144: 	/* Linear feedback shift reg in the mmu. Used to provide pseudo
  145: 	   randomness for the 'hint' the mmu gives to sw for chosing valid
  146: 	   sets on TLB refills.  */
  147: 	uint32_t mmu_rand_lfsr;
  148: 
  149: 	/*
  150: 	 * We just store the stores to the tlbset here for later evaluation
  151: 	 * when the hw needs access to them.
  152: 	 *
  153: 	 * One for I and another for D.
  154: 	 */
  155: 	struct
  156: 	{
  157: 		uint32_t hi;
  158: 		uint32_t lo;
  159: 	} tlbsets[2][4][16];
  160: 
  161: 	CPU_COMMON
  162: 
  163: 	/* Members after CPU_COMMON are preserved across resets.  */
  164: 	void *load_info;
  165: } CPUCRISState;
  166: 
  167: CPUCRISState *cpu_cris_init(const char *cpu_model);
  168: int cpu_cris_exec(CPUCRISState *s);
  169: void cpu_cris_close(CPUCRISState *s);
  170: void do_interrupt(CPUCRISState *env);
  171: /* you can call this signal handler from your SIGBUS and SIGSEGV
  172:    signal handlers to inform the virtual CPU of exceptions. non zero
  173:    is returned if the signal was handled by the virtual CPU.  */
  174: int cpu_cris_signal_handler(int host_signum, void *pinfo,
  175:                            void *puc);
  176: 
  177: enum {
  178:     CC_OP_DYNAMIC, /* Use env->cc_op  */
  179:     CC_OP_FLAGS,
  180:     CC_OP_CMP,
  181:     CC_OP_MOVE,
  182:     CC_OP_ADD,
  183:     CC_OP_ADDC,
  184:     CC_OP_MCP,
  185:     CC_OP_ADDU,
  186:     CC_OP_SUB,
  187:     CC_OP_SUBU,
  188:     CC_OP_NEG,
  189:     CC_OP_BTST,
  190:     CC_OP_MULS,
  191:     CC_OP_MULU,
  192:     CC_OP_DSTEP,
  193:     CC_OP_MSTEP,
  194:     CC_OP_BOUND,
  195: 
  196:     CC_OP_OR,
  197:     CC_OP_AND,
  198:     CC_OP_XOR,
  199:     CC_OP_LSL,
  200:     CC_OP_LSR,
  201:     CC_OP_ASR,
  202:     CC_OP_LZ
  203: };
  204: 
  205: /* CRIS uses 8k pages.  */
  206: #define TARGET_PAGE_BITS 13
  207: #define MMAP_SHIFT TARGET_PAGE_BITS
  208: 
  209: #define TARGET_PHYS_ADDR_SPACE_BITS 32
  210: #define TARGET_VIRT_ADDR_SPACE_BITS 32
  211: 
  212: #define cpu_init cpu_cris_init
  213: #define cpu_exec cpu_cris_exec
  214: #define cpu_gen_code cpu_cris_gen_code
  215: #define cpu_signal_handler cpu_cris_signal_handler
  216: 
  217: #define CPU_SAVE_VERSION 1
  218: 
  219: /* MMU modes definitions */
  220: #define MMU_MODE0_SUFFIX _kernel
  221: #define MMU_MODE1_SUFFIX _user
  222: #define MMU_USER_IDX 1
  223: static inline int cpu_mmu_index (CPUState *env)
  224: {
  225: 	return !!(env->pregs[PR_CCS] & U_FLAG);
  226: }
  227: 
  228: int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
  229:                               int mmu_idx, int is_softmmu);
  230: #define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
  231: 
  232: #if defined(CONFIG_USER_ONLY)
  233: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
  234: {
  235:     if (newsp)
  236:         env->regs[14] = newsp;
  237:     env->regs[10] = 0;
  238: }
  239: #endif
  240: 
  241: static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
  242: {
  243: 	env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
  244: }
  245: 
  246: /* Support function regs.  */
  247: #define SFR_RW_GC_CFG      0][0
  248: #define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
  249: #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
  250: #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
  251: #define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
  252: #define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
  253: #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
  254: #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
  255: 
  256: #include "cpu-all.h"
  257: 
  258: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
  259:                                         target_ulong *cs_base, int *flags)
  260: {
  261:     *pc = env->pc;
  262:     *cs_base = 0;
  263:     *flags = env->dslot |
  264:             (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
  265: 				     | X_FLAG | PFIX_FLAG));
  266: }
  267: 
  268: #define cpu_list cris_cpu_list
  269: void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
  270: 
  271: static inline bool cpu_has_work(CPUState *env)
  272: {
  273:     return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  274: }
  275: 
  276: #include "exec-all.h"
  277: 
  278: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
  279: {
  280:     env->pc = tb->pc;
  281: }
  282: #endif

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