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1.1 root 1: /*
2: * CRIS emulation for qemu: main translation routines.
3: *
1.1.1.2 ! root 4: * Copyright (c) 2008 AXIS Communications AB
1.1 root 5: * Written by Edgar E. Iglesias.
6: *
7: * This library is free software; you can redistribute it and/or
8: * modify it under the terms of the GNU Lesser General Public
9: * License as published by the Free Software Foundation; either
10: * version 2 of the License, or (at your option) any later version.
11: *
12: * This library is distributed in the hope that it will be useful,
13: * but WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15: * Lesser General Public License for more details.
16: *
17: * You should have received a copy of the GNU Lesser General Public
18: * License along with this library; if not, write to the Free Software
1.1.1.2 ! root 19: * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
1.1 root 20: */
21:
22: /*
1.1.1.2 ! root 23: * FIXME:
! 24: * The condition code translation is in need of attention.
1.1 root 25: */
26:
27: #include <stdarg.h>
28: #include <stdlib.h>
29: #include <stdio.h>
30: #include <string.h>
31: #include <inttypes.h>
32: #include <assert.h>
33:
34: #include "cpu.h"
35: #include "exec-all.h"
36: #include "disas.h"
1.1.1.2 ! root 37: #include "tcg-op.h"
! 38: #include "helper.h"
! 39: #include "mmu.h"
1.1 root 40: #include "crisv32-decode.h"
1.1.1.2 ! root 41: #include "qemu-common.h"
1.1 root 42:
1.1.1.2 ! root 43: #define GEN_HELPER 1
! 44: #include "helper.h"
1.1 root 45:
46: #define DISAS_CRIS 0
47: #if DISAS_CRIS
1.1.1.2 ! root 48: # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
1.1 root 49: #else
1.1.1.2 ! root 50: # define LOG_DIS(...) do { } while (0)
1.1 root 51: #endif
52:
1.1.1.2 ! root 53: #define D(x)
1.1 root 54: #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
55: #define BUG_ON(x) ({if (x) BUG();})
56:
1.1.1.2 ! root 57: #define DISAS_SWI 5
! 58:
1.1 root 59: /* Used by the decoder. */
60: #define EXTRACT_FIELD(src, start, end) \
61: (((src) >> start) & ((1 << (end - start + 1)) - 1))
62:
63: #define CC_MASK_NZ 0xc
64: #define CC_MASK_NZV 0xe
65: #define CC_MASK_NZVC 0xf
66: #define CC_MASK_RNZV 0x10e
67:
1.1.1.2 ! root 68: static TCGv_ptr cpu_env;
! 69: static TCGv cpu_R[16];
! 70: static TCGv cpu_PR[16];
! 71: static TCGv cc_x;
! 72: static TCGv cc_src;
! 73: static TCGv cc_dest;
! 74: static TCGv cc_result;
! 75: static TCGv cc_op;
! 76: static TCGv cc_size;
! 77: static TCGv cc_mask;
! 78:
! 79: static TCGv env_btaken;
! 80: static TCGv env_btarget;
! 81: static TCGv env_pc;
1.1 root 82:
1.1.1.2 ! root 83: #include "gen-icount.h"
1.1 root 84:
85: /* This is the state at translation time. */
86: typedef struct DisasContext {
87: CPUState *env;
1.1.1.2 ! root 88: target_ulong pc, ppc;
1.1 root 89:
90: /* Decoder. */
91: uint32_t ir;
92: uint32_t opcode;
93: unsigned int op1;
94: unsigned int op2;
95: unsigned int zsize, zzsize;
96: unsigned int mode;
97: unsigned int postinc;
98:
99: int update_cc;
100: int cc_op;
101: int cc_size;
102: uint32_t cc_mask;
1.1.1.2 ! root 103:
! 104: int cc_size_uptodate; /* -1 invalid or last written value. */
! 105:
! 106: int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
! 107: int flags_uptodate; /* Wether or not $ccs is uptodate. */
! 108: int flagx_known; /* Wether or not flags_x has the x flag known at
! 109: translation time. */
1.1 root 110: int flags_x;
111:
1.1.1.2 ! root 112: int clear_x; /* Clear x after this insn? */
! 113: int cpustate_changed;
! 114: unsigned int tb_flags; /* tb dependent flags. */
1.1 root 115: int is_jmp;
116:
1.1.1.2 ! root 117: #define JMP_NOJMP 0
! 118: #define JMP_DIRECT 1
! 119: #define JMP_INDIRECT 2
! 120: int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
! 121: uint32_t jmp_pc;
! 122:
1.1 root 123: int delayed_branch;
124:
125: struct TranslationBlock *tb;
126: int singlestep_enabled;
127: } DisasContext;
128:
1.1.1.2 ! root 129: static void gen_BUG(DisasContext *dc, const char *file, int line)
1.1 root 130: {
131: printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
1.1.1.2 ! root 132: qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
! 133: cpu_abort(dc->env, "%s:%d\n", file, line);
1.1 root 134: }
135:
1.1.1.2 ! root 136: static const char *regnames[] =
1.1 root 137: {
1.1.1.2 ! root 138: "$r0", "$r1", "$r2", "$r3",
! 139: "$r4", "$r5", "$r6", "$r7",
! 140: "$r8", "$r9", "$r10", "$r11",
! 141: "$r12", "$r13", "$sp", "$acr",
1.1 root 142: };
1.1.1.2 ! root 143: static const char *pregnames[] =
1.1 root 144: {
1.1.1.2 ! root 145: "$bz", "$vr", "$pid", "$srs",
! 146: "$wz", "$exs", "$eda", "$mof",
! 147: "$dz", "$ebp", "$erp", "$srp",
! 148: "$nrp", "$ccs", "$usp", "$spc",
1.1 root 149: };
150:
1.1.1.2 ! root 151: /* We need this table to handle preg-moves with implicit width. */
! 152: static int preg_sizes[] = {
! 153: 1, /* bz. */
! 154: 1, /* vr. */
! 155: 4, /* pid. */
! 156: 1, /* srs. */
! 157: 2, /* wz. */
! 158: 4, 4, 4,
! 159: 4, 4, 4, 4,
! 160: 4, 4, 4, 4,
! 161: };
! 162:
! 163: #define t_gen_mov_TN_env(tn, member) \
! 164: _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
! 165: #define t_gen_mov_env_TN(member, tn) \
! 166: _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
! 167:
! 168: static inline void t_gen_mov_TN_reg(TCGv tn, int r)
! 169: {
! 170: if (r < 0 || r > 15)
! 171: fprintf(stderr, "wrong register read $r%d\n", r);
! 172: tcg_gen_mov_tl(tn, cpu_R[r]);
! 173: }
! 174: static inline void t_gen_mov_reg_TN(int r, TCGv tn)
! 175: {
! 176: if (r < 0 || r > 15)
! 177: fprintf(stderr, "wrong register write $r%d\n", r);
! 178: tcg_gen_mov_tl(cpu_R[r], tn);
1.1 root 179: }
180:
1.1.1.2 ! root 181: static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
! 182: {
! 183: if (offset > sizeof (CPUState))
! 184: fprintf(stderr, "wrong load from env from off=%d\n", offset);
! 185: tcg_gen_ld_tl(tn, cpu_env, offset);
! 186: }
! 187: static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
! 188: {
! 189: if (offset > sizeof (CPUState))
! 190: fprintf(stderr, "wrong store to env at off=%d\n", offset);
! 191: tcg_gen_st_tl(tn, cpu_env, offset);
1.1 root 192: }
193:
1.1.1.2 ! root 194: static inline void t_gen_mov_TN_preg(TCGv tn, int r)
! 195: {
! 196: if (r < 0 || r > 15)
! 197: fprintf(stderr, "wrong register read $p%d\n", r);
! 198: if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
! 199: tcg_gen_mov_tl(tn, tcg_const_tl(0));
! 200: else if (r == PR_VR)
! 201: tcg_gen_mov_tl(tn, tcg_const_tl(32));
! 202: else if (r == PR_EDA) {
! 203: printf("read from EDA!\n");
! 204: tcg_gen_mov_tl(tn, cpu_PR[r]);
! 205: }
! 206: else
! 207: tcg_gen_mov_tl(tn, cpu_PR[r]);
! 208: }
! 209: static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
! 210: {
! 211: if (r < 0 || r > 15)
! 212: fprintf(stderr, "wrong register write $p%d\n", r);
! 213: if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
! 214: return;
! 215: else if (r == PR_SRS)
! 216: tcg_gen_andi_tl(cpu_PR[r], tn, 3);
! 217: else {
! 218: if (r == PR_PID)
! 219: gen_helper_tlb_flush_pid(tn);
! 220: if (dc->tb_flags & S_FLAG && r == PR_SPC)
! 221: gen_helper_spc_write(tn);
! 222: else if (r == PR_CCS)
! 223: dc->cpustate_changed = 1;
! 224: tcg_gen_mov_tl(cpu_PR[r], tn);
! 225: }
1.1 root 226: }
227:
1.1.1.2 ! root 228: static inline void t_gen_raise_exception(uint32_t index)
! 229: {
! 230: TCGv_i32 tmp = tcg_const_i32(index);
! 231: gen_helper_raise_exception(tmp);
! 232: tcg_temp_free_i32(tmp);
1.1 root 233: }
234:
1.1.1.2 ! root 235: static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
1.1 root 236: {
1.1.1.2 ! root 237: TCGv t0, t_31;
! 238:
! 239: t0 = tcg_temp_new();
! 240: t_31 = tcg_const_tl(31);
! 241: tcg_gen_shl_tl(d, a, b);
! 242:
! 243: tcg_gen_sub_tl(t0, t_31, b);
! 244: tcg_gen_sar_tl(t0, t0, t_31);
! 245: tcg_gen_and_tl(t0, t0, d);
! 246: tcg_gen_xor_tl(d, d, t0);
! 247: tcg_temp_free(t0);
! 248: tcg_temp_free(t_31);
! 249: }
! 250:
! 251: static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
1.1 root 252: {
1.1.1.2 ! root 253: TCGv t0, t_31;
1.1 root 254:
1.1.1.2 ! root 255: t0 = tcg_temp_new();
! 256: t_31 = tcg_temp_new();
! 257: tcg_gen_shr_tl(d, a, b);
1.1 root 258:
1.1.1.2 ! root 259: tcg_gen_movi_tl(t_31, 31);
! 260: tcg_gen_sub_tl(t0, t_31, b);
! 261: tcg_gen_sar_tl(t0, t0, t_31);
! 262: tcg_gen_and_tl(t0, t0, d);
! 263: tcg_gen_xor_tl(d, d, t0);
! 264: tcg_temp_free(t0);
! 265: tcg_temp_free(t_31);
! 266: }
! 267:
! 268: static void t_gen_asr(TCGv d, TCGv a, TCGv b)
! 269: {
! 270: TCGv t0, t_31;
! 271:
! 272: t0 = tcg_temp_new();
! 273: t_31 = tcg_temp_new();
! 274: tcg_gen_sar_tl(d, a, b);
! 275:
! 276: tcg_gen_movi_tl(t_31, 31);
! 277: tcg_gen_sub_tl(t0, t_31, b);
! 278: tcg_gen_sar_tl(t0, t0, t_31);
! 279: tcg_gen_or_tl(d, d, t0);
! 280: tcg_temp_free(t0);
! 281: tcg_temp_free(t_31);
! 282: }
! 283:
! 284: /* 64-bit signed mul, lower result in d and upper in d2. */
! 285: static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
! 286: {
! 287: TCGv_i64 t0, t1;
! 288:
! 289: t0 = tcg_temp_new_i64();
! 290: t1 = tcg_temp_new_i64();
! 291:
! 292: tcg_gen_ext_i32_i64(t0, a);
! 293: tcg_gen_ext_i32_i64(t1, b);
! 294: tcg_gen_mul_i64(t0, t0, t1);
! 295:
! 296: tcg_gen_trunc_i64_i32(d, t0);
! 297: tcg_gen_shri_i64(t0, t0, 32);
! 298: tcg_gen_trunc_i64_i32(d2, t0);
! 299:
! 300: tcg_temp_free_i64(t0);
! 301: tcg_temp_free_i64(t1);
! 302: }
! 303:
! 304: /* 64-bit unsigned muls, lower result in d and upper in d2. */
! 305: static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
! 306: {
! 307: TCGv_i64 t0, t1;
! 308:
! 309: t0 = tcg_temp_new_i64();
! 310: t1 = tcg_temp_new_i64();
1.1 root 311:
1.1.1.2 ! root 312: tcg_gen_extu_i32_i64(t0, a);
! 313: tcg_gen_extu_i32_i64(t1, b);
! 314: tcg_gen_mul_i64(t0, t0, t1);
! 315:
! 316: tcg_gen_trunc_i64_i32(d, t0);
! 317: tcg_gen_shri_i64(t0, t0, 32);
! 318: tcg_gen_trunc_i64_i32(d2, t0);
! 319:
! 320: tcg_temp_free_i64(t0);
! 321: tcg_temp_free_i64(t1);
! 322: }
! 323:
! 324: static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
! 325: {
! 326: int l1;
! 327:
! 328: l1 = gen_new_label();
! 329:
! 330: /*
! 331: * d <<= 1
! 332: * if (d >= s)
! 333: * d -= s;
! 334: */
! 335: tcg_gen_shli_tl(d, a, 1);
! 336: tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
! 337: tcg_gen_sub_tl(d, d, b);
! 338: gen_set_label(l1);
! 339: }
! 340:
! 341: /* Extended arithmetics on CRIS. */
! 342: static inline void t_gen_add_flag(TCGv d, int flag)
! 343: {
! 344: TCGv c;
! 345:
! 346: c = tcg_temp_new();
! 347: t_gen_mov_TN_preg(c, PR_CCS);
! 348: /* Propagate carry into d. */
! 349: tcg_gen_andi_tl(c, c, 1 << flag);
! 350: if (flag)
! 351: tcg_gen_shri_tl(c, c, flag);
! 352: tcg_gen_add_tl(d, d, c);
! 353: tcg_temp_free(c);
! 354: }
! 355:
! 356: static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
! 357: {
! 358: if (dc->flagx_known) {
! 359: if (dc->flags_x) {
! 360: TCGv c;
! 361:
! 362: c = tcg_temp_new();
! 363: t_gen_mov_TN_preg(c, PR_CCS);
! 364: /* C flag is already at bit 0. */
! 365: tcg_gen_andi_tl(c, c, C_FLAG);
! 366: tcg_gen_add_tl(d, d, c);
! 367: tcg_temp_free(c);
! 368: }
! 369: } else {
! 370: TCGv x, c;
! 371:
! 372: x = tcg_temp_new();
! 373: c = tcg_temp_new();
! 374: t_gen_mov_TN_preg(x, PR_CCS);
! 375: tcg_gen_mov_tl(c, x);
! 376:
! 377: /* Propagate carry into d if X is set. Branch free. */
! 378: tcg_gen_andi_tl(c, c, C_FLAG);
! 379: tcg_gen_andi_tl(x, x, X_FLAG);
! 380: tcg_gen_shri_tl(x, x, 4);
! 381:
! 382: tcg_gen_and_tl(x, x, c);
! 383: tcg_gen_add_tl(d, d, x);
! 384: tcg_temp_free(x);
! 385: tcg_temp_free(c);
! 386: }
! 387: }
! 388:
! 389: static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
! 390: {
! 391: if (dc->flagx_known) {
! 392: if (dc->flags_x) {
! 393: TCGv c;
! 394:
! 395: c = tcg_temp_new();
! 396: t_gen_mov_TN_preg(c, PR_CCS);
! 397: /* C flag is already at bit 0. */
! 398: tcg_gen_andi_tl(c, c, C_FLAG);
! 399: tcg_gen_sub_tl(d, d, c);
! 400: tcg_temp_free(c);
! 401: }
! 402: } else {
! 403: TCGv x, c;
! 404:
! 405: x = tcg_temp_new();
! 406: c = tcg_temp_new();
! 407: t_gen_mov_TN_preg(x, PR_CCS);
! 408: tcg_gen_mov_tl(c, x);
! 409:
! 410: /* Propagate carry into d if X is set. Branch free. */
! 411: tcg_gen_andi_tl(c, c, C_FLAG);
! 412: tcg_gen_andi_tl(x, x, X_FLAG);
! 413: tcg_gen_shri_tl(x, x, 4);
! 414:
! 415: tcg_gen_and_tl(x, x, c);
! 416: tcg_gen_sub_tl(d, d, x);
! 417: tcg_temp_free(x);
! 418: tcg_temp_free(c);
! 419: }
! 420: }
! 421:
! 422: /* Swap the two bytes within each half word of the s operand.
! 423: T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
! 424: static inline void t_gen_swapb(TCGv d, TCGv s)
! 425: {
! 426: TCGv t, org_s;
! 427:
! 428: t = tcg_temp_new();
! 429: org_s = tcg_temp_new();
! 430:
! 431: /* d and s may refer to the same object. */
! 432: tcg_gen_mov_tl(org_s, s);
! 433: tcg_gen_shli_tl(t, org_s, 8);
! 434: tcg_gen_andi_tl(d, t, 0xff00ff00);
! 435: tcg_gen_shri_tl(t, org_s, 8);
! 436: tcg_gen_andi_tl(t, t, 0x00ff00ff);
! 437: tcg_gen_or_tl(d, d, t);
! 438: tcg_temp_free(t);
! 439: tcg_temp_free(org_s);
! 440: }
! 441:
! 442: /* Swap the halfwords of the s operand. */
! 443: static inline void t_gen_swapw(TCGv d, TCGv s)
! 444: {
! 445: TCGv t;
! 446: /* d and s refer the same object. */
! 447: t = tcg_temp_new();
! 448: tcg_gen_mov_tl(t, s);
! 449: tcg_gen_shli_tl(d, t, 16);
! 450: tcg_gen_shri_tl(t, t, 16);
! 451: tcg_gen_or_tl(d, d, t);
! 452: tcg_temp_free(t);
! 453: }
! 454:
! 455: /* Reverse the within each byte.
! 456: T0 = (((T0 << 7) & 0x80808080) |
! 457: ((T0 << 5) & 0x40404040) |
! 458: ((T0 << 3) & 0x20202020) |
! 459: ((T0 << 1) & 0x10101010) |
! 460: ((T0 >> 1) & 0x08080808) |
! 461: ((T0 >> 3) & 0x04040404) |
! 462: ((T0 >> 5) & 0x02020202) |
! 463: ((T0 >> 7) & 0x01010101));
! 464: */
! 465: static inline void t_gen_swapr(TCGv d, TCGv s)
! 466: {
! 467: struct {
! 468: int shift; /* LSL when positive, LSR when negative. */
! 469: uint32_t mask;
! 470: } bitrev [] = {
! 471: {7, 0x80808080},
! 472: {5, 0x40404040},
! 473: {3, 0x20202020},
! 474: {1, 0x10101010},
! 475: {-1, 0x08080808},
! 476: {-3, 0x04040404},
! 477: {-5, 0x02020202},
! 478: {-7, 0x01010101}
! 479: };
! 480: int i;
! 481: TCGv t, org_s;
! 482:
! 483: /* d and s refer the same object. */
! 484: t = tcg_temp_new();
! 485: org_s = tcg_temp_new();
! 486: tcg_gen_mov_tl(org_s, s);
! 487:
! 488: tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
! 489: tcg_gen_andi_tl(d, t, bitrev[0].mask);
! 490: for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
! 491: if (bitrev[i].shift >= 0) {
! 492: tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
! 493: } else {
! 494: tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
! 495: }
! 496: tcg_gen_andi_tl(t, t, bitrev[i].mask);
! 497: tcg_gen_or_tl(d, d, t);
! 498: }
! 499: tcg_temp_free(t);
! 500: tcg_temp_free(org_s);
! 501: }
! 502:
! 503: static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
! 504: {
! 505: TCGv btaken;
! 506: int l1;
! 507:
! 508: l1 = gen_new_label();
! 509: btaken = tcg_temp_new();
! 510:
! 511: /* Conditional jmp. */
! 512: tcg_gen_mov_tl(btaken, env_btaken);
! 513: tcg_gen_mov_tl(env_pc, pc_false);
! 514: tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
! 515: tcg_gen_mov_tl(env_pc, pc_true);
! 516: gen_set_label(l1);
! 517:
! 518: tcg_temp_free(btaken);
! 519: }
1.1 root 520:
521: static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
522: {
523: TranslationBlock *tb;
524: tb = dc->tb;
525: if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1.1.1.2 ! root 526: tcg_gen_goto_tb(n);
! 527: tcg_gen_movi_tl(env_pc, dest);
! 528: tcg_gen_exit_tb((long)tb + n);
1.1 root 529: } else {
1.1.1.2 ! root 530: tcg_gen_movi_tl(env_pc, dest);
! 531: tcg_gen_exit_tb(0);
1.1 root 532: }
533: }
534:
535: /* Sign extend at translation time. */
536: static int sign_extend(unsigned int val, unsigned int width)
537: {
538: int sval;
539:
540: /* LSL. */
541: val <<= 31 - width;
542: sval = val;
543: /* ASR. */
544: sval >>= 31 - width;
545: return sval;
546: }
547:
1.1.1.2 ! root 548: static inline void cris_clear_x_flag(DisasContext *dc)
! 549: {
! 550: if (dc->flagx_known && dc->flags_x)
! 551: dc->flags_uptodate = 0;
! 552:
! 553: dc->flagx_known = 1;
! 554: dc->flags_x = 0;
! 555: }
! 556:
! 557: static void cris_flush_cc_state(DisasContext *dc)
! 558: {
! 559: if (dc->cc_size_uptodate != dc->cc_size) {
! 560: tcg_gen_movi_tl(cc_size, dc->cc_size);
! 561: dc->cc_size_uptodate = dc->cc_size;
! 562: }
! 563: tcg_gen_movi_tl(cc_op, dc->cc_op);
! 564: tcg_gen_movi_tl(cc_mask, dc->cc_mask);
! 565: }
! 566:
1.1 root 567: static void cris_evaluate_flags(DisasContext *dc)
568: {
1.1.1.2 ! root 569: if (dc->flags_uptodate)
! 570: return;
1.1 root 571:
1.1.1.2 ! root 572: cris_flush_cc_state(dc);
! 573:
! 574: switch (dc->cc_op)
! 575: {
! 576: case CC_OP_MCP:
! 577: gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
! 578: cpu_PR[PR_CCS], cc_src,
! 579: cc_dest, cc_result);
! 580: break;
! 581: case CC_OP_MULS:
! 582: gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
! 583: cpu_PR[PR_CCS], cc_result,
! 584: cpu_PR[PR_MOF]);
! 585: break;
! 586: case CC_OP_MULU:
! 587: gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
! 588: cpu_PR[PR_CCS], cc_result,
! 589: cpu_PR[PR_MOF]);
! 590: break;
! 591: case CC_OP_MOVE:
! 592: case CC_OP_AND:
! 593: case CC_OP_OR:
! 594: case CC_OP_XOR:
! 595: case CC_OP_ASR:
! 596: case CC_OP_LSR:
! 597: case CC_OP_LSL:
! 598: switch (dc->cc_size)
1.1 root 599: {
1.1.1.2 ! root 600: case 4:
! 601: gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
! 602: cpu_PR[PR_CCS], cc_result);
! 603: break;
! 604: case 2:
! 605: gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
! 606: cpu_PR[PR_CCS], cc_result);
! 607: break;
! 608: default:
! 609: gen_helper_evaluate_flags();
! 610: break;
! 611: }
! 612: break;
! 613: case CC_OP_FLAGS:
! 614: /* live. */
! 615: break;
! 616: case CC_OP_SUB:
! 617: case CC_OP_CMP:
! 618: if (dc->cc_size == 4)
! 619: gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
! 620: cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
! 621: else
! 622: gen_helper_evaluate_flags();
1.1 root 623:
1.1.1.2 ! root 624: break;
! 625: default:
! 626: switch (dc->cc_size)
! 627: {
! 628: case 4:
! 629: gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
! 630: cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
! 631: break;
1.1 root 632: default:
1.1.1.2 ! root 633: gen_helper_evaluate_flags();
! 634: break;
1.1 root 635: }
1.1.1.2 ! root 636: break;
1.1 root 637: }
1.1.1.2 ! root 638:
! 639: if (dc->flagx_known) {
! 640: if (dc->flags_x)
! 641: tcg_gen_ori_tl(cpu_PR[PR_CCS],
! 642: cpu_PR[PR_CCS], X_FLAG);
! 643: else
! 644: tcg_gen_andi_tl(cpu_PR[PR_CCS],
! 645: cpu_PR[PR_CCS], ~X_FLAG);
! 646: }
! 647: dc->flags_uptodate = 1;
1.1 root 648: }
649:
650: static void cris_cc_mask(DisasContext *dc, unsigned int mask)
651: {
652: uint32_t ovl;
653:
1.1.1.2 ! root 654: if (!mask) {
! 655: dc->update_cc = 0;
! 656: return;
! 657: }
! 658:
! 659: /* Check if we need to evaluate the condition codes due to
! 660: CC overlaying. */
1.1 root 661: ovl = (dc->cc_mask ^ mask) & ~mask;
662: if (ovl) {
663: /* TODO: optimize this case. It trigs all the time. */
664: cris_evaluate_flags (dc);
665: }
666: dc->cc_mask = mask;
667: dc->update_cc = 1;
668: }
669:
1.1.1.2 ! root 670: static void cris_update_cc_op(DisasContext *dc, int op, int size)
1.1 root 671: {
672: dc->cc_op = op;
1.1.1.2 ! root 673: dc->cc_size = size;
! 674: dc->flags_uptodate = 0;
1.1 root 675: }
1.1.1.2 ! root 676:
! 677: static inline void cris_update_cc_x(DisasContext *dc)
1.1 root 678: {
1.1.1.2 ! root 679: /* Save the x flag state at the time of the cc snapshot. */
! 680: if (dc->flagx_known) {
! 681: if (dc->cc_x_uptodate == (2 | dc->flags_x))
! 682: return;
! 683: tcg_gen_movi_tl(cc_x, dc->flags_x);
! 684: dc->cc_x_uptodate = 2 | dc->flags_x;
! 685: }
! 686: else {
! 687: tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
! 688: dc->cc_x_uptodate = 1;
! 689: }
1.1 root 690: }
691:
1.1.1.2 ! root 692: /* Update cc prior to executing ALU op. Needs source operands untouched. */
! 693: static void cris_pre_alu_update_cc(DisasContext *dc, int op,
! 694: TCGv dst, TCGv src, int size)
1.1 root 695: {
696: if (dc->update_cc) {
1.1.1.2 ! root 697: cris_update_cc_op(dc, op, size);
! 698: tcg_gen_mov_tl(cc_src, src);
! 699:
! 700: if (op != CC_OP_MOVE
! 701: && op != CC_OP_AND
! 702: && op != CC_OP_OR
! 703: && op != CC_OP_XOR
! 704: && op != CC_OP_ASR
! 705: && op != CC_OP_LSR
! 706: && op != CC_OP_LSL)
! 707: tcg_gen_mov_tl(cc_dest, dst);
! 708:
! 709: cris_update_cc_x(dc);
1.1 root 710: }
1.1.1.2 ! root 711: }
1.1 root 712:
1.1.1.2 ! root 713: /* Update cc after executing ALU op. needs the result. */
! 714: static inline void cris_update_result(DisasContext *dc, TCGv res)
! 715: {
! 716: if (dc->update_cc)
! 717: tcg_gen_mov_tl(cc_result, res);
! 718: }
! 719:
! 720: /* Returns one if the write back stage should execute. */
! 721: static void cris_alu_op_exec(DisasContext *dc, int op,
! 722: TCGv dst, TCGv a, TCGv b, int size)
! 723: {
1.1 root 724: /* Emit the ALU insns. */
725: switch (op)
726: {
727: case CC_OP_ADD:
1.1.1.2 ! root 728: tcg_gen_add_tl(dst, a, b);
1.1 root 729: /* Extended arithmetics. */
1.1.1.2 ! root 730: t_gen_addx_carry(dc, dst);
1.1 root 731: break;
732: case CC_OP_ADDC:
1.1.1.2 ! root 733: tcg_gen_add_tl(dst, a, b);
! 734: t_gen_add_flag(dst, 0); /* C_FLAG. */
1.1 root 735: break;
736: case CC_OP_MCP:
1.1.1.2 ! root 737: tcg_gen_add_tl(dst, a, b);
! 738: t_gen_add_flag(dst, 8); /* R_FLAG. */
1.1 root 739: break;
740: case CC_OP_SUB:
1.1.1.2 ! root 741: tcg_gen_sub_tl(dst, a, b);
1.1 root 742: /* Extended arithmetics. */
1.1.1.2 ! root 743: t_gen_subx_carry(dc, dst);
1.1 root 744: break;
745: case CC_OP_MOVE:
1.1.1.2 ! root 746: tcg_gen_mov_tl(dst, b);
1.1 root 747: break;
748: case CC_OP_OR:
1.1.1.2 ! root 749: tcg_gen_or_tl(dst, a, b);
1.1 root 750: break;
751: case CC_OP_AND:
1.1.1.2 ! root 752: tcg_gen_and_tl(dst, a, b);
1.1 root 753: break;
754: case CC_OP_XOR:
1.1.1.2 ! root 755: tcg_gen_xor_tl(dst, a, b);
1.1 root 756: break;
757: case CC_OP_LSL:
1.1.1.2 ! root 758: t_gen_lsl(dst, a, b);
1.1 root 759: break;
760: case CC_OP_LSR:
1.1.1.2 ! root 761: t_gen_lsr(dst, a, b);
1.1 root 762: break;
763: case CC_OP_ASR:
1.1.1.2 ! root 764: t_gen_asr(dst, a, b);
1.1 root 765: break;
766: case CC_OP_NEG:
1.1.1.2 ! root 767: tcg_gen_neg_tl(dst, b);
1.1 root 768: /* Extended arithmetics. */
1.1.1.2 ! root 769: t_gen_subx_carry(dc, dst);
1.1 root 770: break;
771: case CC_OP_LZ:
1.1.1.2 ! root 772: gen_helper_lz(dst, b);
1.1 root 773: break;
774: case CC_OP_MULS:
1.1.1.2 ! root 775: t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
1.1 root 776: break;
777: case CC_OP_MULU:
1.1.1.2 ! root 778: t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
1.1 root 779: break;
780: case CC_OP_DSTEP:
1.1.1.2 ! root 781: t_gen_cris_dstep(dst, a, b);
1.1 root 782: break;
783: case CC_OP_BOUND:
1.1.1.2 ! root 784: {
! 785: int l1;
! 786: l1 = gen_new_label();
! 787: tcg_gen_mov_tl(dst, a);
! 788: tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
! 789: tcg_gen_mov_tl(dst, b);
! 790: gen_set_label(l1);
! 791: }
! 792: break;
1.1 root 793: case CC_OP_CMP:
1.1.1.2 ! root 794: tcg_gen_sub_tl(dst, a, b);
1.1 root 795: /* Extended arithmetics. */
1.1.1.2 ! root 796: t_gen_subx_carry(dc, dst);
1.1 root 797: break;
798: default:
1.1.1.2 ! root 799: qemu_log("illegal ALU op.\n");
1.1 root 800: BUG();
801: break;
802: }
803:
804: if (size == 1)
1.1.1.2 ! root 805: tcg_gen_andi_tl(dst, dst, 0xff);
1.1 root 806: else if (size == 2)
1.1.1.2 ! root 807: tcg_gen_andi_tl(dst, dst, 0xffff);
! 808: }
! 809:
! 810: static void cris_alu(DisasContext *dc, int op,
! 811: TCGv d, TCGv op_a, TCGv op_b, int size)
! 812: {
! 813: TCGv tmp;
! 814: int writeback;
! 815:
! 816: writeback = 1;
! 817:
! 818: if (op == CC_OP_CMP) {
! 819: tmp = tcg_temp_new();
! 820: writeback = 0;
! 821: } else if (size == 4) {
! 822: tmp = d;
! 823: writeback = 0;
! 824: } else
! 825: tmp = tcg_temp_new();
! 826:
! 827:
! 828: cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
! 829: cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
! 830: cris_update_result(dc, tmp);
! 831:
1.1 root 832: /* Writeback. */
833: if (writeback) {
1.1.1.2 ! root 834: if (size == 1)
! 835: tcg_gen_andi_tl(d, d, ~0xff);
! 836: else
! 837: tcg_gen_andi_tl(d, d, ~0xffff);
! 838: tcg_gen_or_tl(d, d, tmp);
1.1 root 839: }
1.1.1.2 ! root 840: if (!TCGV_EQUAL(tmp, d))
! 841: tcg_temp_free(tmp);
1.1 root 842: }
843:
844: static int arith_cc(DisasContext *dc)
845: {
846: if (dc->update_cc) {
847: switch (dc->cc_op) {
1.1.1.2 ! root 848: case CC_OP_ADDC: return 1;
1.1 root 849: case CC_OP_ADD: return 1;
850: case CC_OP_SUB: return 1;
1.1.1.2 ! root 851: case CC_OP_DSTEP: return 1;
1.1 root 852: case CC_OP_LSL: return 1;
853: case CC_OP_LSR: return 1;
854: case CC_OP_ASR: return 1;
855: case CC_OP_CMP: return 1;
1.1.1.2 ! root 856: case CC_OP_NEG: return 1;
! 857: case CC_OP_OR: return 1;
! 858: case CC_OP_AND: return 1;
! 859: case CC_OP_XOR: return 1;
! 860: case CC_OP_MULU: return 1;
! 861: case CC_OP_MULS: return 1;
1.1 root 862: default:
863: return 0;
864: }
865: }
866: return 0;
867: }
868:
1.1.1.2 ! root 869: static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
1.1 root 870: {
1.1.1.2 ! root 871: int arith_opt, move_opt;
1.1 root 872:
873: /* TODO: optimize more condition codes. */
1.1.1.2 ! root 874:
! 875: /*
! 876: * If the flags are live, we've gotta look into the bits of CCS.
! 877: * Otherwise, if we just did an arithmetic operation we try to
! 878: * evaluate the condition code faster.
! 879: *
! 880: * When this function is done, T0 should be non-zero if the condition
! 881: * code is true.
! 882: */
! 883: arith_opt = arith_cc(dc) && !dc->flags_uptodate;
! 884: move_opt = (dc->cc_op == CC_OP_MOVE);
1.1 root 885: switch (cond) {
886: case CC_EQ:
1.1.1.2 ! root 887: if (arith_opt || move_opt) {
! 888: /* If cc_result is zero, T0 should be
! 889: non-zero otherwise T0 should be zero. */
! 890: int l1;
! 891: l1 = gen_new_label();
! 892: tcg_gen_movi_tl(cc, 0);
! 893: tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
! 894: 0, l1);
! 895: tcg_gen_movi_tl(cc, 1);
! 896: gen_set_label(l1);
! 897: }
1.1 root 898: else {
899: cris_evaluate_flags(dc);
1.1.1.2 ! root 900: tcg_gen_andi_tl(cc,
! 901: cpu_PR[PR_CCS], Z_FLAG);
1.1 root 902: }
903: break;
904: case CC_NE:
1.1.1.2 ! root 905: if (arith_opt || move_opt)
! 906: tcg_gen_mov_tl(cc, cc_result);
1.1 root 907: else {
908: cris_evaluate_flags(dc);
1.1.1.2 ! root 909: tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
! 910: Z_FLAG);
! 911: tcg_gen_andi_tl(cc, cc, Z_FLAG);
1.1 root 912: }
913: break;
914: case CC_CS:
915: cris_evaluate_flags(dc);
1.1.1.2 ! root 916: tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
1.1 root 917: break;
918: case CC_CC:
919: cris_evaluate_flags(dc);
1.1.1.2 ! root 920: tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
! 921: tcg_gen_andi_tl(cc, cc, C_FLAG);
1.1 root 922: break;
923: case CC_VS:
924: cris_evaluate_flags(dc);
1.1.1.2 ! root 925: tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
1.1 root 926: break;
927: case CC_VC:
928: cris_evaluate_flags(dc);
1.1.1.2 ! root 929: tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
! 930: V_FLAG);
! 931: tcg_gen_andi_tl(cc, cc, V_FLAG);
1.1 root 932: break;
933: case CC_PL:
1.1.1.2 ! root 934: if (arith_opt || move_opt) {
! 935: int bits = 31;
! 936:
! 937: if (dc->cc_size == 1)
! 938: bits = 7;
! 939: else if (dc->cc_size == 2)
! 940: bits = 15;
! 941:
! 942: tcg_gen_shri_tl(cc, cc_result, bits);
! 943: tcg_gen_xori_tl(cc, cc, 1);
! 944: } else {
1.1 root 945: cris_evaluate_flags(dc);
1.1.1.2 ! root 946: tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
! 947: N_FLAG);
! 948: tcg_gen_andi_tl(cc, cc, N_FLAG);
1.1 root 949: }
950: break;
951: case CC_MI:
1.1.1.2 ! root 952: if (arith_opt || move_opt) {
! 953: int bits = 31;
! 954:
! 955: if (dc->cc_size == 1)
! 956: bits = 7;
! 957: else if (dc->cc_size == 2)
! 958: bits = 15;
! 959:
! 960: tcg_gen_shri_tl(cc, cc_result, 31);
! 961: }
1.1 root 962: else {
963: cris_evaluate_flags(dc);
1.1.1.2 ! root 964: tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
! 965: N_FLAG);
1.1 root 966: }
967: break;
968: case CC_LS:
969: cris_evaluate_flags(dc);
1.1.1.2 ! root 970: tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
! 971: C_FLAG | Z_FLAG);
1.1 root 972: break;
973: case CC_HI:
974: cris_evaluate_flags(dc);
1.1.1.2 ! root 975: {
! 976: TCGv tmp;
! 977:
! 978: tmp = tcg_temp_new();
! 979: tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
! 980: C_FLAG | Z_FLAG);
! 981: /* Overlay the C flag on top of the Z. */
! 982: tcg_gen_shli_tl(cc, tmp, 2);
! 983: tcg_gen_and_tl(cc, tmp, cc);
! 984: tcg_gen_andi_tl(cc, cc, Z_FLAG);
! 985:
! 986: tcg_temp_free(tmp);
! 987: }
1.1 root 988: break;
989: case CC_GE:
990: cris_evaluate_flags(dc);
1.1.1.2 ! root 991: /* Overlay the V flag on top of the N. */
! 992: tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
! 993: tcg_gen_xor_tl(cc,
! 994: cpu_PR[PR_CCS], cc);
! 995: tcg_gen_andi_tl(cc, cc, N_FLAG);
! 996: tcg_gen_xori_tl(cc, cc, N_FLAG);
1.1 root 997: break;
998: case CC_LT:
999: cris_evaluate_flags(dc);
1.1.1.2 ! root 1000: /* Overlay the V flag on top of the N. */
! 1001: tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
! 1002: tcg_gen_xor_tl(cc,
! 1003: cpu_PR[PR_CCS], cc);
! 1004: tcg_gen_andi_tl(cc, cc, N_FLAG);
1.1 root 1005: break;
1006: case CC_GT:
1007: cris_evaluate_flags(dc);
1.1.1.2 ! root 1008: {
! 1009: TCGv n, z;
! 1010:
! 1011: n = tcg_temp_new();
! 1012: z = tcg_temp_new();
! 1013:
! 1014: /* To avoid a shift we overlay everything on
! 1015: the V flag. */
! 1016: tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
! 1017: tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
! 1018: /* invert Z. */
! 1019: tcg_gen_xori_tl(z, z, 2);
! 1020:
! 1021: tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
! 1022: tcg_gen_xori_tl(n, n, 2);
! 1023: tcg_gen_and_tl(cc, z, n);
! 1024: tcg_gen_andi_tl(cc, cc, 2);
! 1025:
! 1026: tcg_temp_free(n);
! 1027: tcg_temp_free(z);
! 1028: }
1.1 root 1029: break;
1030: case CC_LE:
1031: cris_evaluate_flags(dc);
1.1.1.2 ! root 1032: {
! 1033: TCGv n, z;
! 1034:
! 1035: n = tcg_temp_new();
! 1036: z = tcg_temp_new();
! 1037:
! 1038: /* To avoid a shift we overlay everything on
! 1039: the V flag. */
! 1040: tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
! 1041: tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
! 1042:
! 1043: tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
! 1044: tcg_gen_or_tl(cc, z, n);
! 1045: tcg_gen_andi_tl(cc, cc, 2);
! 1046:
! 1047: tcg_temp_free(n);
! 1048: tcg_temp_free(z);
! 1049: }
1.1 root 1050: break;
1051: case CC_P:
1052: cris_evaluate_flags(dc);
1.1.1.2 ! root 1053: tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1.1 root 1054: break;
1055: case CC_A:
1.1.1.2 ! root 1056: tcg_gen_movi_tl(cc, 1);
1.1 root 1057: break;
1058: default:
1059: BUG();
1060: break;
1061: };
1062: }
1063:
1.1.1.2 ! root 1064: static void cris_store_direct_jmp(DisasContext *dc)
! 1065: {
! 1066: /* Store the direct jmp state into the cpu-state. */
! 1067: if (dc->jmp == JMP_DIRECT) {
! 1068: tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
! 1069: tcg_gen_movi_tl(env_btaken, 1);
! 1070: }
! 1071: }
! 1072:
! 1073: static void cris_prepare_cc_branch (DisasContext *dc,
! 1074: int offset, int cond)
1.1 root 1075: {
1076: /* This helps us re-schedule the micro-code to insns in delay-slots
1077: before the actual jump. */
1078: dc->delayed_branch = 2;
1.1.1.2 ! root 1079: dc->jmp_pc = dc->pc + offset;
! 1080:
1.1 root 1081: if (cond != CC_A)
1082: {
1.1.1.2 ! root 1083: dc->jmp = JMP_INDIRECT;
! 1084: gen_tst_cc (dc, env_btaken, cond);
! 1085: tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
! 1086: } else {
! 1087: /* Allow chaining. */
! 1088: dc->jmp = JMP_DIRECT;
1.1 root 1089: }
1090: }
1091:
1.1.1.2 ! root 1092:
! 1093: /* jumps, when the dest is in a live reg for example. Direct should be set
! 1094: when the dest addr is constant to allow tb chaining. */
! 1095: static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1.1 root 1096: {
1097: /* This helps us re-schedule the micro-code to insns in delay-slots
1098: before the actual jump. */
1099: dc->delayed_branch = 2;
1.1.1.2 ! root 1100: dc->jmp = type;
! 1101: if (type == JMP_INDIRECT)
! 1102: tcg_gen_movi_tl(env_btaken, 1);
1.1 root 1103: }
1104:
1.1.1.2 ! root 1105: static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1.1 root 1106: {
1.1.1.2 ! root 1107: int mem_index = cpu_mmu_index(dc->env);
! 1108:
! 1109: /* If we get a fault on a delayslot we must keep the jmp state in
! 1110: the cpu-state to be able to re-execute the jmp. */
! 1111: if (dc->delayed_branch == 1)
! 1112: cris_store_direct_jmp(dc);
! 1113:
! 1114: tcg_gen_qemu_ld64(dst, addr, mem_index);
1.1 root 1115: }
1116:
1.1.1.2 ! root 1117: static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
! 1118: unsigned int size, int sign)
1.1 root 1119: {
1.1.1.2 ! root 1120: int mem_index = cpu_mmu_index(dc->env);
! 1121:
! 1122: /* If we get a fault on a delayslot we must keep the jmp state in
! 1123: the cpu-state to be able to re-execute the jmp. */
! 1124: if (dc->delayed_branch == 1)
! 1125: cris_store_direct_jmp(dc);
! 1126:
1.1 root 1127: if (size == 1) {
1128: if (sign)
1.1.1.2 ! root 1129: tcg_gen_qemu_ld8s(dst, addr, mem_index);
1.1 root 1130: else
1.1.1.2 ! root 1131: tcg_gen_qemu_ld8u(dst, addr, mem_index);
1.1 root 1132: }
1133: else if (size == 2) {
1134: if (sign)
1.1.1.2 ! root 1135: tcg_gen_qemu_ld16s(dst, addr, mem_index);
1.1 root 1136: else
1.1.1.2 ! root 1137: tcg_gen_qemu_ld16u(dst, addr, mem_index);
! 1138: }
! 1139: else if (size == 4) {
! 1140: tcg_gen_qemu_ld32u(dst, addr, mem_index);
1.1 root 1141: }
1142: else {
1.1.1.2 ! root 1143: abort();
1.1 root 1144: }
1145: }
1146:
1.1.1.2 ! root 1147: static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
! 1148: unsigned int size)
1.1 root 1149: {
1.1.1.2 ! root 1150: int mem_index = cpu_mmu_index(dc->env);
1.1 root 1151:
1.1.1.2 ! root 1152: /* If we get a fault on a delayslot we must keep the jmp state in
! 1153: the cpu-state to be able to re-execute the jmp. */
! 1154: if (dc->delayed_branch == 1)
! 1155: cris_store_direct_jmp(dc);
1.1 root 1156:
1157:
1.1.1.2 ! root 1158: /* Conditional writes. We only support the kind were X and P are known
! 1159: at translation time. */
! 1160: if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
! 1161: dc->postinc = 0;
! 1162: cris_evaluate_flags(dc);
! 1163: tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
! 1164: return;
! 1165: }
1.1 root 1166:
1167: if (size == 1)
1.1.1.2 ! root 1168: tcg_gen_qemu_st8(val, addr, mem_index);
1.1 root 1169: else if (size == 2)
1.1.1.2 ! root 1170: tcg_gen_qemu_st16(val, addr, mem_index);
! 1171: else
! 1172: tcg_gen_qemu_st32(val, addr, mem_index);
! 1173:
! 1174: if (dc->flagx_known && dc->flags_x) {
! 1175: cris_evaluate_flags(dc);
! 1176: tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
! 1177: }
1.1 root 1178: }
1179:
1.1.1.2 ! root 1180: static inline void t_gen_sext(TCGv d, TCGv s, int size)
1.1 root 1181: {
1182: if (size == 1)
1.1.1.2 ! root 1183: tcg_gen_ext8s_i32(d, s);
1.1 root 1184: else if (size == 2)
1.1.1.2 ! root 1185: tcg_gen_ext16s_i32(d, s);
! 1186: else if(!TCGV_EQUAL(d, s))
! 1187: tcg_gen_mov_tl(d, s);
1.1 root 1188: }
1189:
1.1.1.2 ! root 1190: static inline void t_gen_zext(TCGv d, TCGv s, int size)
1.1 root 1191: {
1192: if (size == 1)
1.1.1.2 ! root 1193: tcg_gen_ext8u_i32(d, s);
1.1 root 1194: else if (size == 2)
1.1.1.2 ! root 1195: tcg_gen_ext16u_i32(d, s);
! 1196: else if (!TCGV_EQUAL(d, s))
! 1197: tcg_gen_mov_tl(d, s);
1.1 root 1198: }
1199:
1200: #if DISAS_CRIS
1201: static char memsize_char(int size)
1202: {
1203: switch (size)
1204: {
1205: case 1: return 'b'; break;
1206: case 2: return 'w'; break;
1207: case 4: return 'd'; break;
1208: default:
1209: return 'x';
1210: break;
1211: }
1212: }
1213: #endif
1214:
1.1.1.2 ! root 1215: static inline unsigned int memsize_z(DisasContext *dc)
1.1 root 1216: {
1217: return dc->zsize + 1;
1218: }
1219:
1.1.1.2 ! root 1220: static inline unsigned int memsize_zz(DisasContext *dc)
1.1 root 1221: {
1222: switch (dc->zzsize)
1223: {
1224: case 0: return 1;
1225: case 1: return 2;
1226: default:
1227: return 4;
1228: }
1229: }
1230:
1.1.1.2 ! root 1231: static inline void do_postinc (DisasContext *dc, int size)
1.1 root 1232: {
1.1.1.2 ! root 1233: if (dc->postinc)
! 1234: tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1.1 root 1235: }
1236:
1.1.1.2 ! root 1237: static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
! 1238: int size, int s_ext, TCGv dst)
1.1 root 1239: {
1240: if (s_ext)
1.1.1.2 ! root 1241: t_gen_sext(dst, cpu_R[rs], size);
1.1 root 1242: else
1.1.1.2 ! root 1243: t_gen_zext(dst, cpu_R[rs], size);
1.1 root 1244: }
1245:
1246: /* Prepare T0 and T1 for a register alu operation.
1247: s_ext decides if the operand1 should be sign-extended or zero-extended when
1248: needed. */
1249: static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1.1.1.2 ! root 1250: int size, int s_ext, TCGv dst, TCGv src)
1.1 root 1251: {
1.1.1.2 ! root 1252: dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1.1 root 1253:
1254: if (s_ext)
1.1.1.2 ! root 1255: t_gen_sext(dst, cpu_R[rd], size);
1.1 root 1256: else
1.1.1.2 ! root 1257: t_gen_zext(dst, cpu_R[rd], size);
1.1 root 1258: }
1259:
1.1.1.2 ! root 1260: static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
! 1261: TCGv dst)
1.1 root 1262: {
1263: unsigned int rs, rd;
1264: uint32_t imm;
1265: int is_imm;
1266: int insn_len = 2;
1267:
1268: rs = dc->op1;
1269: rd = dc->op2;
1270: is_imm = rs == 15 && dc->postinc;
1271:
1272: /* Load [$rs] onto T1. */
1273: if (is_imm) {
1274: insn_len = 2 + memsize;
1275: if (memsize == 1)
1276: insn_len++;
1277:
1278: if (memsize != 4) {
1279: if (s_ext) {
1.1.1.2 ! root 1280: if (memsize == 1)
! 1281: imm = ldsb_code(dc->pc + 2);
! 1282: else
! 1283: imm = ldsw_code(dc->pc + 2);
1.1 root 1284: } else {
1285: if (memsize == 1)
1.1.1.2 ! root 1286: imm = ldub_code(dc->pc + 2);
1.1 root 1287: else
1.1.1.2 ! root 1288: imm = lduw_code(dc->pc + 2);
1.1 root 1289: }
1.1.1.2 ! root 1290: } else
! 1291: imm = ldl_code(dc->pc + 2);
! 1292:
! 1293: tcg_gen_movi_tl(dst, imm);
1.1 root 1294: dc->postinc = 0;
1295: } else {
1.1.1.2 ! root 1296: cris_flush_cc_state(dc);
! 1297: gen_load(dc, dst, cpu_R[rs], memsize, 0);
1.1 root 1298: if (s_ext)
1.1.1.2 ! root 1299: t_gen_sext(dst, dst, memsize);
1.1 root 1300: else
1.1.1.2 ! root 1301: t_gen_zext(dst, dst, memsize);
1.1 root 1302: }
1.1.1.2 ! root 1303: return insn_len;
! 1304: }
! 1305:
! 1306: /* Prepare T0 and T1 for a memory + alu operation.
! 1307: s_ext decides if the operand1 should be sign-extended or zero-extended when
! 1308: needed. */
! 1309: static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
! 1310: TCGv dst, TCGv src)
! 1311: {
! 1312: int insn_len;
1.1 root 1313:
1.1.1.2 ! root 1314: insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
! 1315: tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1.1 root 1316: return insn_len;
1317: }
1318:
1319: #if DISAS_CRIS
1320: static const char *cc_name(int cc)
1321: {
1.1.1.2 ! root 1322: static const char *cc_names[16] = {
1.1 root 1323: "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1324: "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1325: };
1326: assert(cc < 16);
1327: return cc_names[cc];
1328: }
1329: #endif
1330:
1.1.1.2 ! root 1331: /* Start of insn decoders. */
! 1332:
1.1 root 1333: static unsigned int dec_bccq(DisasContext *dc)
1334: {
1335: int32_t offset;
1336: int sign;
1337: uint32_t cond = dc->op2;
1338: int tmp;
1339:
1340: offset = EXTRACT_FIELD (dc->ir, 1, 7);
1341: sign = EXTRACT_FIELD(dc->ir, 0, 0);
1342:
1343: offset *= 2;
1344: offset |= sign << 8;
1345: tmp = offset;
1346: offset = sign_extend(offset, 8);
1347:
1.1.1.2 ! root 1348: LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
! 1349:
1.1 root 1350: /* op2 holds the condition-code. */
1351: cris_cc_mask(dc, 0);
1352: cris_prepare_cc_branch (dc, offset, cond);
1353: return 2;
1354: }
1355: static unsigned int dec_addoq(DisasContext *dc)
1356: {
1.1.1.2 ! root 1357: int32_t imm;
1.1 root 1358:
1359: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1360: imm = sign_extend(dc->op1, 7);
1361:
1.1.1.2 ! root 1362: LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1.1 root 1363: cris_cc_mask(dc, 0);
1364: /* Fetch register operand, */
1.1.1.2 ! root 1365: tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
! 1366:
1.1 root 1367: return 2;
1368: }
1369: static unsigned int dec_addq(DisasContext *dc)
1370: {
1.1.1.2 ! root 1371: LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1.1 root 1372:
1373: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1374:
1375: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1376:
! 1377: cris_alu(dc, CC_OP_ADD,
! 1378: cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1.1 root 1379: return 2;
1380: }
1381: static unsigned int dec_moveq(DisasContext *dc)
1382: {
1383: uint32_t imm;
1384:
1385: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1386: imm = sign_extend(dc->op1, 5);
1.1.1.2 ! root 1387: LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1.1 root 1388:
1.1.1.2 ! root 1389: tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1.1 root 1390: return 2;
1391: }
1392: static unsigned int dec_subq(DisasContext *dc)
1393: {
1394: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1395:
1.1.1.2 ! root 1396: LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1.1 root 1397:
1398: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1399: cris_alu(dc, CC_OP_SUB,
! 1400: cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1.1 root 1401: return 2;
1402: }
1403: static unsigned int dec_cmpq(DisasContext *dc)
1404: {
1405: uint32_t imm;
1406: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1407: imm = sign_extend(dc->op1, 5);
1408:
1.1.1.2 ! root 1409: LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1.1 root 1410: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1411:
! 1412: cris_alu(dc, CC_OP_CMP,
! 1413: cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1.1 root 1414: return 2;
1415: }
1416: static unsigned int dec_andq(DisasContext *dc)
1417: {
1418: uint32_t imm;
1419: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1420: imm = sign_extend(dc->op1, 5);
1421:
1.1.1.2 ! root 1422: LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1.1 root 1423: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1424:
! 1425: cris_alu(dc, CC_OP_AND,
! 1426: cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1.1 root 1427: return 2;
1428: }
1429: static unsigned int dec_orq(DisasContext *dc)
1430: {
1431: uint32_t imm;
1432: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1433: imm = sign_extend(dc->op1, 5);
1.1.1.2 ! root 1434: LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1.1 root 1435: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1436:
! 1437: cris_alu(dc, CC_OP_OR,
! 1438: cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1.1 root 1439: return 2;
1440: }
1441: static unsigned int dec_btstq(DisasContext *dc)
1442: {
1443: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1.1.1.2 ! root 1444: LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
! 1445:
1.1 root 1446: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1447: cris_evaluate_flags(dc);
! 1448: gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
! 1449: tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
! 1450: cris_alu(dc, CC_OP_MOVE,
! 1451: cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
! 1452: cris_update_cc_op(dc, CC_OP_FLAGS, 4);
! 1453: dc->flags_uptodate = 1;
1.1 root 1454: return 2;
1455: }
1456: static unsigned int dec_asrq(DisasContext *dc)
1457: {
1458: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1.1.1.2 ! root 1459: LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1.1 root 1460: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1461:
! 1462: tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
! 1463: cris_alu(dc, CC_OP_MOVE,
! 1464: cpu_R[dc->op2],
! 1465: cpu_R[dc->op2], cpu_R[dc->op2], 4);
1.1 root 1466: return 2;
1467: }
1468: static unsigned int dec_lslq(DisasContext *dc)
1469: {
1470: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1.1.1.2 ! root 1471: LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1.1 root 1472:
1473: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1474:
! 1475: tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
! 1476:
! 1477: cris_alu(dc, CC_OP_MOVE,
! 1478: cpu_R[dc->op2],
! 1479: cpu_R[dc->op2], cpu_R[dc->op2], 4);
1.1 root 1480: return 2;
1481: }
1482: static unsigned int dec_lsrq(DisasContext *dc)
1483: {
1484: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1.1.1.2 ! root 1485: LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1.1 root 1486:
1487: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1488:
! 1489: tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
! 1490: cris_alu(dc, CC_OP_MOVE,
! 1491: cpu_R[dc->op2],
! 1492: cpu_R[dc->op2], cpu_R[dc->op2], 4);
1.1 root 1493: return 2;
1494: }
1495:
1496: static unsigned int dec_move_r(DisasContext *dc)
1497: {
1498: int size = memsize_zz(dc);
1499:
1.1.1.2 ! root 1500: LOG_DIS("move.%c $r%u, $r%u\n",
! 1501: memsize_char(size), dc->op1, dc->op2);
1.1 root 1502:
1503: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1504: if (size == 4) {
! 1505: dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
! 1506: cris_cc_mask(dc, CC_MASK_NZ);
! 1507: cris_update_cc_op(dc, CC_OP_MOVE, 4);
! 1508: cris_update_cc_x(dc);
! 1509: cris_update_result(dc, cpu_R[dc->op2]);
! 1510: }
! 1511: else {
! 1512: TCGv t0;
! 1513:
! 1514: t0 = tcg_temp_new();
! 1515: dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
! 1516: cris_alu(dc, CC_OP_MOVE,
! 1517: cpu_R[dc->op2],
! 1518: cpu_R[dc->op2], t0, size);
! 1519: tcg_temp_free(t0);
! 1520: }
1.1 root 1521: return 2;
1522: }
1523:
1524: static unsigned int dec_scc_r(DisasContext *dc)
1525: {
1526: int cond = dc->op2;
1527:
1.1.1.2 ! root 1528: LOG_DIS("s%s $r%u\n",
! 1529: cc_name(cond), dc->op1);
1.1 root 1530:
1531: if (cond != CC_A)
1532: {
1.1.1.2 ! root 1533: int l1;
! 1534:
! 1535: gen_tst_cc (dc, cpu_R[dc->op1], cond);
! 1536: l1 = gen_new_label();
! 1537: tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
! 1538: tcg_gen_movi_tl(cpu_R[dc->op1], 1);
! 1539: gen_set_label(l1);
1.1 root 1540: }
1541: else
1.1.1.2 ! root 1542: tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1.1 root 1543:
1544: cris_cc_mask(dc, 0);
1545: return 2;
1546: }
1547:
1.1.1.2 ! root 1548: static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
! 1549: {
! 1550: if (size == 4) {
! 1551: t[0] = cpu_R[dc->op2];
! 1552: t[1] = cpu_R[dc->op1];
! 1553: } else {
! 1554: t[0] = tcg_temp_new();
! 1555: t[1] = tcg_temp_new();
! 1556: }
! 1557: }
! 1558:
! 1559: static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
! 1560: {
! 1561: if (size != 4) {
! 1562: tcg_temp_free(t[0]);
! 1563: tcg_temp_free(t[1]);
! 1564: }
! 1565: }
! 1566:
1.1 root 1567: static unsigned int dec_and_r(DisasContext *dc)
1568: {
1.1.1.2 ! root 1569: TCGv t[2];
1.1 root 1570: int size = memsize_zz(dc);
1571:
1.1.1.2 ! root 1572: LOG_DIS("and.%c $r%u, $r%u\n",
! 1573: memsize_char(size), dc->op1, dc->op2);
! 1574:
1.1 root 1575: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1576:
! 1577: cris_alu_alloc_temps(dc, size, t);
! 1578: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1579: cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
! 1580: cris_alu_free_temps(dc, size, t);
1.1 root 1581: return 2;
1582: }
1583:
1584: static unsigned int dec_lz_r(DisasContext *dc)
1585: {
1.1.1.2 ! root 1586: TCGv t0;
! 1587: LOG_DIS("lz $r%u, $r%u\n",
! 1588: dc->op1, dc->op2);
! 1589: cris_cc_mask(dc, CC_MASK_NZ);
! 1590: t0 = tcg_temp_new();
! 1591: dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
! 1592: cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
! 1593: tcg_temp_free(t0);
1.1 root 1594: return 2;
1595: }
1596:
1597: static unsigned int dec_lsl_r(DisasContext *dc)
1598: {
1.1.1.2 ! root 1599: TCGv t[2];
1.1 root 1600: int size = memsize_zz(dc);
1601:
1.1.1.2 ! root 1602: LOG_DIS("lsl.%c $r%u, $r%u\n",
! 1603: memsize_char(size), dc->op1, dc->op2);
! 1604:
1.1 root 1605: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1606: cris_alu_alloc_temps(dc, size, t);
! 1607: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1608: tcg_gen_andi_tl(t[1], t[1], 63);
! 1609: cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
! 1610: cris_alu_alloc_temps(dc, size, t);
1.1 root 1611: return 2;
1612: }
1613:
1614: static unsigned int dec_lsr_r(DisasContext *dc)
1615: {
1.1.1.2 ! root 1616: TCGv t[2];
1.1 root 1617: int size = memsize_zz(dc);
1618:
1.1.1.2 ! root 1619: LOG_DIS("lsr.%c $r%u, $r%u\n",
! 1620: memsize_char(size), dc->op1, dc->op2);
! 1621:
1.1 root 1622: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1623: cris_alu_alloc_temps(dc, size, t);
! 1624: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1625: tcg_gen_andi_tl(t[1], t[1], 63);
! 1626: cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
! 1627: cris_alu_free_temps(dc, size, t);
1.1 root 1628: return 2;
1629: }
1630:
1631: static unsigned int dec_asr_r(DisasContext *dc)
1632: {
1.1.1.2 ! root 1633: TCGv t[2];
1.1 root 1634: int size = memsize_zz(dc);
1635:
1.1.1.2 ! root 1636: LOG_DIS("asr.%c $r%u, $r%u\n",
! 1637: memsize_char(size), dc->op1, dc->op2);
! 1638:
1.1 root 1639: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1640: cris_alu_alloc_temps(dc, size, t);
! 1641: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
! 1642: tcg_gen_andi_tl(t[1], t[1], 63);
! 1643: cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
! 1644: cris_alu_free_temps(dc, size, t);
1.1 root 1645: return 2;
1646: }
1647:
1648: static unsigned int dec_muls_r(DisasContext *dc)
1649: {
1.1.1.2 ! root 1650: TCGv t[2];
1.1 root 1651: int size = memsize_zz(dc);
1652:
1.1.1.2 ! root 1653: LOG_DIS("muls.%c $r%u, $r%u\n",
! 1654: memsize_char(size), dc->op1, dc->op2);
1.1 root 1655: cris_cc_mask(dc, CC_MASK_NZV);
1.1.1.2 ! root 1656: cris_alu_alloc_temps(dc, size, t);
! 1657: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
! 1658:
! 1659: cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
! 1660: cris_alu_free_temps(dc, size, t);
1.1 root 1661: return 2;
1662: }
1663:
1664: static unsigned int dec_mulu_r(DisasContext *dc)
1665: {
1.1.1.2 ! root 1666: TCGv t[2];
1.1 root 1667: int size = memsize_zz(dc);
1668:
1.1.1.2 ! root 1669: LOG_DIS("mulu.%c $r%u, $r%u\n",
! 1670: memsize_char(size), dc->op1, dc->op2);
1.1 root 1671: cris_cc_mask(dc, CC_MASK_NZV);
1.1.1.2 ! root 1672: cris_alu_alloc_temps(dc, size, t);
! 1673: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1674:
! 1675: cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
! 1676: cris_alu_alloc_temps(dc, size, t);
1.1 root 1677: return 2;
1678: }
1679:
1680:
1681: static unsigned int dec_dstep_r(DisasContext *dc)
1682: {
1.1.1.2 ! root 1683: LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1.1 root 1684: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1685: cris_alu(dc, CC_OP_DSTEP,
! 1686: cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1.1 root 1687: return 2;
1688: }
1689:
1690: static unsigned int dec_xor_r(DisasContext *dc)
1691: {
1.1.1.2 ! root 1692: TCGv t[2];
1.1 root 1693: int size = memsize_zz(dc);
1.1.1.2 ! root 1694: LOG_DIS("xor.%c $r%u, $r%u\n",
! 1695: memsize_char(size), dc->op1, dc->op2);
1.1 root 1696: BUG_ON(size != 4); /* xor is dword. */
1697: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1698: cris_alu_alloc_temps(dc, size, t);
! 1699: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1700:
! 1701: cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
! 1702: cris_alu_free_temps(dc, size, t);
1.1 root 1703: return 2;
1704: }
1705:
1706: static unsigned int dec_bound_r(DisasContext *dc)
1707: {
1.1.1.2 ! root 1708: TCGv l0;
1.1 root 1709: int size = memsize_zz(dc);
1.1.1.2 ! root 1710: LOG_DIS("bound.%c $r%u, $r%u\n",
! 1711: memsize_char(size), dc->op1, dc->op2);
1.1 root 1712: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1713: l0 = tcg_temp_local_new();
! 1714: dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
! 1715: cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
! 1716: tcg_temp_free(l0);
1.1 root 1717: return 2;
1718: }
1719:
1720: static unsigned int dec_cmp_r(DisasContext *dc)
1721: {
1.1.1.2 ! root 1722: TCGv t[2];
1.1 root 1723: int size = memsize_zz(dc);
1.1.1.2 ! root 1724: LOG_DIS("cmp.%c $r%u, $r%u\n",
! 1725: memsize_char(size), dc->op1, dc->op2);
1.1 root 1726: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1727: cris_alu_alloc_temps(dc, size, t);
! 1728: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1729:
! 1730: cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
! 1731: cris_alu_free_temps(dc, size, t);
1.1 root 1732: return 2;
1733: }
1734:
1735: static unsigned int dec_abs_r(DisasContext *dc)
1736: {
1.1.1.2 ! root 1737: TCGv t0;
! 1738:
! 1739: LOG_DIS("abs $r%u, $r%u\n",
! 1740: dc->op1, dc->op2);
1.1 root 1741: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1742:
! 1743: t0 = tcg_temp_new();
! 1744: tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
! 1745: tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
! 1746: tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
! 1747: tcg_temp_free(t0);
! 1748:
! 1749: cris_alu(dc, CC_OP_MOVE,
! 1750: cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1.1 root 1751: return 2;
1752: }
1753:
1754: static unsigned int dec_add_r(DisasContext *dc)
1755: {
1.1.1.2 ! root 1756: TCGv t[2];
1.1 root 1757: int size = memsize_zz(dc);
1.1.1.2 ! root 1758: LOG_DIS("add.%c $r%u, $r%u\n",
! 1759: memsize_char(size), dc->op1, dc->op2);
1.1 root 1760: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1761: cris_alu_alloc_temps(dc, size, t);
! 1762: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1763:
! 1764: cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
! 1765: cris_alu_free_temps(dc, size, t);
1.1 root 1766: return 2;
1767: }
1768:
1769: static unsigned int dec_addc_r(DisasContext *dc)
1770: {
1.1.1.2 ! root 1771: LOG_DIS("addc $r%u, $r%u\n",
! 1772: dc->op1, dc->op2);
1.1 root 1773: cris_evaluate_flags(dc);
1.1.1.2 ! root 1774: /* Set for this insn. */
! 1775: dc->flagx_known = 1;
! 1776: dc->flags_x = X_FLAG;
! 1777:
1.1 root 1778: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1779: cris_alu(dc, CC_OP_ADDC,
! 1780: cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1.1 root 1781: return 2;
1782: }
1783:
1784: static unsigned int dec_mcp_r(DisasContext *dc)
1785: {
1.1.1.2 ! root 1786: LOG_DIS("mcp $p%u, $r%u\n",
! 1787: dc->op2, dc->op1);
1.1 root 1788: cris_evaluate_flags(dc);
1789: cris_cc_mask(dc, CC_MASK_RNZV);
1.1.1.2 ! root 1790: cris_alu(dc, CC_OP_MCP,
! 1791: cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1.1 root 1792: return 2;
1793: }
1794:
1795: #if DISAS_CRIS
1796: static char * swapmode_name(int mode, char *modename) {
1797: int i = 0;
1798: if (mode & 8)
1799: modename[i++] = 'n';
1800: if (mode & 4)
1801: modename[i++] = 'w';
1802: if (mode & 2)
1803: modename[i++] = 'b';
1804: if (mode & 1)
1805: modename[i++] = 'r';
1806: modename[i++] = 0;
1807: return modename;
1808: }
1809: #endif
1810:
1811: static unsigned int dec_swap_r(DisasContext *dc)
1812: {
1.1.1.2 ! root 1813: TCGv t0;
! 1814: #if DISAS_CRIS
! 1815: char modename[4];
! 1816: #endif
! 1817: LOG_DIS("swap%s $r%u\n",
! 1818: swapmode_name(dc->op2, modename), dc->op1);
1.1 root 1819:
1820: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1821: t0 = tcg_temp_new();
! 1822: t_gen_mov_TN_reg(t0, dc->op1);
1.1 root 1823: if (dc->op2 & 8)
1.1.1.2 ! root 1824: tcg_gen_not_tl(t0, t0);
1.1 root 1825: if (dc->op2 & 4)
1.1.1.2 ! root 1826: t_gen_swapw(t0, t0);
1.1 root 1827: if (dc->op2 & 2)
1.1.1.2 ! root 1828: t_gen_swapb(t0, t0);
1.1 root 1829: if (dc->op2 & 1)
1.1.1.2 ! root 1830: t_gen_swapr(t0, t0);
! 1831: cris_alu(dc, CC_OP_MOVE,
! 1832: cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
! 1833: tcg_temp_free(t0);
1.1 root 1834: return 2;
1835: }
1836:
1837: static unsigned int dec_or_r(DisasContext *dc)
1838: {
1.1.1.2 ! root 1839: TCGv t[2];
1.1 root 1840: int size = memsize_zz(dc);
1.1.1.2 ! root 1841: LOG_DIS("or.%c $r%u, $r%u\n",
! 1842: memsize_char(size), dc->op1, dc->op2);
1.1 root 1843: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1844: cris_alu_alloc_temps(dc, size, t);
! 1845: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1846: cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
! 1847: cris_alu_free_temps(dc, size, t);
1.1 root 1848: return 2;
1849: }
1850:
1851: static unsigned int dec_addi_r(DisasContext *dc)
1852: {
1.1.1.2 ! root 1853: TCGv t0;
! 1854: LOG_DIS("addi.%c $r%u, $r%u\n",
! 1855: memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
! 1856: cris_cc_mask(dc, 0);
! 1857: t0 = tcg_temp_new();
! 1858: tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
! 1859: tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
! 1860: tcg_temp_free(t0);
1.1 root 1861: return 2;
1862: }
1863:
1864: static unsigned int dec_addi_acr(DisasContext *dc)
1865: {
1.1.1.2 ! root 1866: TCGv t0;
! 1867: LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
! 1868: memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
! 1869: cris_cc_mask(dc, 0);
! 1870: t0 = tcg_temp_new();
! 1871: tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
! 1872: tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
! 1873: tcg_temp_free(t0);
1.1 root 1874: return 2;
1875: }
1876:
1877: static unsigned int dec_neg_r(DisasContext *dc)
1878: {
1.1.1.2 ! root 1879: TCGv t[2];
1.1 root 1880: int size = memsize_zz(dc);
1.1.1.2 ! root 1881: LOG_DIS("neg.%c $r%u, $r%u\n",
! 1882: memsize_char(size), dc->op1, dc->op2);
1.1 root 1883: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1884: cris_alu_alloc_temps(dc, size, t);
! 1885: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1886:
! 1887: cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
! 1888: cris_alu_free_temps(dc, size, t);
1.1 root 1889: return 2;
1890: }
1891:
1892: static unsigned int dec_btst_r(DisasContext *dc)
1893: {
1.1.1.2 ! root 1894: LOG_DIS("btst $r%u, $r%u\n",
! 1895: dc->op1, dc->op2);
1.1 root 1896: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1897: cris_evaluate_flags(dc);
! 1898: gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
! 1899: cpu_R[dc->op1], cpu_PR[PR_CCS]);
! 1900: cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
! 1901: cpu_R[dc->op2], cpu_R[dc->op2], 4);
! 1902: cris_update_cc_op(dc, CC_OP_FLAGS, 4);
! 1903: dc->flags_uptodate = 1;
1.1 root 1904: return 2;
1905: }
1906:
1907: static unsigned int dec_sub_r(DisasContext *dc)
1908: {
1.1.1.2 ! root 1909: TCGv t[2];
1.1 root 1910: int size = memsize_zz(dc);
1.1.1.2 ! root 1911: LOG_DIS("sub.%c $r%u, $r%u\n",
! 1912: memsize_char(size), dc->op1, dc->op2);
1.1 root 1913: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1914: cris_alu_alloc_temps(dc, size, t);
! 1915: dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
! 1916: cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
! 1917: cris_alu_free_temps(dc, size, t);
1.1 root 1918: return 2;
1919: }
1920:
1921: /* Zero extension. From size to dword. */
1922: static unsigned int dec_movu_r(DisasContext *dc)
1923: {
1.1.1.2 ! root 1924: TCGv t0;
1.1 root 1925: int size = memsize_z(dc);
1.1.1.2 ! root 1926: LOG_DIS("movu.%c $r%u, $r%u\n",
1.1 root 1927: memsize_char(size),
1.1.1.2 ! root 1928: dc->op1, dc->op2);
1.1 root 1929:
1930: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1931: t0 = tcg_temp_new();
! 1932: dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
! 1933: cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
! 1934: tcg_temp_free(t0);
1.1 root 1935: return 2;
1936: }
1937:
1938: /* Sign extension. From size to dword. */
1939: static unsigned int dec_movs_r(DisasContext *dc)
1940: {
1.1.1.2 ! root 1941: TCGv t0;
1.1 root 1942: int size = memsize_z(dc);
1.1.1.2 ! root 1943: LOG_DIS("movs.%c $r%u, $r%u\n",
1.1 root 1944: memsize_char(size),
1.1.1.2 ! root 1945: dc->op1, dc->op2);
1.1 root 1946:
1947: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 1948: t0 = tcg_temp_new();
1.1 root 1949: /* Size can only be qi or hi. */
1.1.1.2 ! root 1950: t_gen_sext(t0, cpu_R[dc->op1], size);
! 1951: cris_alu(dc, CC_OP_MOVE,
! 1952: cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
! 1953: tcg_temp_free(t0);
1.1 root 1954: return 2;
1955: }
1956:
1957: /* zero extension. From size to dword. */
1958: static unsigned int dec_addu_r(DisasContext *dc)
1959: {
1.1.1.2 ! root 1960: TCGv t0;
1.1 root 1961: int size = memsize_z(dc);
1.1.1.2 ! root 1962: LOG_DIS("addu.%c $r%u, $r%u\n",
1.1 root 1963: memsize_char(size),
1.1.1.2 ! root 1964: dc->op1, dc->op2);
1.1 root 1965:
1966: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1967: t0 = tcg_temp_new();
1.1 root 1968: /* Size can only be qi or hi. */
1.1.1.2 ! root 1969: t_gen_zext(t0, cpu_R[dc->op1], size);
! 1970: cris_alu(dc, CC_OP_ADD,
! 1971: cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
! 1972: tcg_temp_free(t0);
1.1 root 1973: return 2;
1974: }
1.1.1.2 ! root 1975:
1.1 root 1976: /* Sign extension. From size to dword. */
1977: static unsigned int dec_adds_r(DisasContext *dc)
1978: {
1.1.1.2 ! root 1979: TCGv t0;
1.1 root 1980: int size = memsize_z(dc);
1.1.1.2 ! root 1981: LOG_DIS("adds.%c $r%u, $r%u\n",
1.1 root 1982: memsize_char(size),
1.1.1.2 ! root 1983: dc->op1, dc->op2);
1.1 root 1984:
1985: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 1986: t0 = tcg_temp_new();
1.1 root 1987: /* Size can only be qi or hi. */
1.1.1.2 ! root 1988: t_gen_sext(t0, cpu_R[dc->op1], size);
! 1989: cris_alu(dc, CC_OP_ADD,
! 1990: cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
! 1991: tcg_temp_free(t0);
1.1 root 1992: return 2;
1993: }
1994:
1995: /* Zero extension. From size to dword. */
1996: static unsigned int dec_subu_r(DisasContext *dc)
1997: {
1.1.1.2 ! root 1998: TCGv t0;
1.1 root 1999: int size = memsize_z(dc);
1.1.1.2 ! root 2000: LOG_DIS("subu.%c $r%u, $r%u\n",
1.1 root 2001: memsize_char(size),
1.1.1.2 ! root 2002: dc->op1, dc->op2);
1.1 root 2003:
2004: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2005: t0 = tcg_temp_new();
1.1 root 2006: /* Size can only be qi or hi. */
1.1.1.2 ! root 2007: t_gen_zext(t0, cpu_R[dc->op1], size);
! 2008: cris_alu(dc, CC_OP_SUB,
! 2009: cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
! 2010: tcg_temp_free(t0);
1.1 root 2011: return 2;
2012: }
2013:
2014: /* Sign extension. From size to dword. */
2015: static unsigned int dec_subs_r(DisasContext *dc)
2016: {
1.1.1.2 ! root 2017: TCGv t0;
1.1 root 2018: int size = memsize_z(dc);
1.1.1.2 ! root 2019: LOG_DIS("subs.%c $r%u, $r%u\n",
1.1 root 2020: memsize_char(size),
1.1.1.2 ! root 2021: dc->op1, dc->op2);
1.1 root 2022:
2023: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2024: t0 = tcg_temp_new();
1.1 root 2025: /* Size can only be qi or hi. */
1.1.1.2 ! root 2026: t_gen_sext(t0, cpu_R[dc->op1], size);
! 2027: cris_alu(dc, CC_OP_SUB,
! 2028: cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
! 2029: tcg_temp_free(t0);
1.1 root 2030: return 2;
2031: }
2032:
2033: static unsigned int dec_setclrf(DisasContext *dc)
2034: {
2035: uint32_t flags;
2036: int set = (~dc->opcode >> 2) & 1;
2037:
1.1.1.2 ! root 2038:
1.1 root 2039: flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2040: | EXTRACT_FIELD(dc->ir, 0, 3);
1.1.1.2 ! root 2041: if (set && flags == 0) {
! 2042: LOG_DIS("nop\n");
! 2043: return 2;
! 2044: } else if (!set && (flags & 0x20)) {
! 2045: LOG_DIS("di\n");
! 2046: }
! 2047: else {
! 2048: LOG_DIS("%sf %x\n",
! 2049: set ? "set" : "clr",
! 2050: flags);
! 2051: }
! 2052:
! 2053: /* User space is not allowed to touch these. Silently ignore. */
! 2054: if (dc->tb_flags & U_FLAG) {
! 2055: flags &= ~(S_FLAG | I_FLAG | U_FLAG);
1.1 root 2056: }
2057:
1.1.1.2 ! root 2058: if (flags & X_FLAG) {
! 2059: dc->flagx_known = 1;
! 2060: if (set)
! 2061: dc->flags_x = X_FLAG;
! 2062: else
! 2063: dc->flags_x = 0;
! 2064: }
! 2065:
! 2066: /* Break the TB if the P flag changes. */
! 2067: if (flags & P_FLAG) {
! 2068: if ((set && !(dc->tb_flags & P_FLAG))
! 2069: || (!set && (dc->tb_flags & P_FLAG))) {
! 2070: tcg_gen_movi_tl(env_pc, dc->pc + 2);
! 2071: dc->is_jmp = DISAS_UPDATE;
! 2072: dc->cpustate_changed = 1;
! 2073: }
! 2074: }
! 2075: if (flags & S_FLAG) {
! 2076: dc->cpustate_changed = 1;
! 2077: }
! 2078:
! 2079:
1.1 root 2080: /* Simply decode the flags. */
2081: cris_evaluate_flags (dc);
1.1.1.2 ! root 2082: cris_update_cc_op(dc, CC_OP_FLAGS, 4);
! 2083: cris_update_cc_x(dc);
! 2084: tcg_gen_movi_tl(cc_op, dc->cc_op);
! 2085:
! 2086: if (set) {
! 2087: if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
! 2088: /* Enter user mode. */
! 2089: t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
! 2090: tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
! 2091: dc->cpustate_changed = 1;
! 2092: }
! 2093: tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
! 2094: }
1.1 root 2095: else
1.1.1.2 ! root 2096: tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
! 2097:
! 2098: dc->flags_uptodate = 1;
! 2099: dc->clear_x = 0;
1.1 root 2100: return 2;
2101: }
2102:
2103: static unsigned int dec_move_rs(DisasContext *dc)
2104: {
1.1.1.2 ! root 2105: LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
1.1 root 2106: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2107: gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
1.1 root 2108: return 2;
2109: }
2110: static unsigned int dec_move_sr(DisasContext *dc)
2111: {
1.1.1.2 ! root 2112: LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
1.1 root 2113: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2114: gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
1.1 root 2115: return 2;
2116: }
1.1.1.2 ! root 2117:
1.1 root 2118: static unsigned int dec_move_rp(DisasContext *dc)
2119: {
1.1.1.2 ! root 2120: TCGv t[2];
! 2121: LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
1.1 root 2122: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2123:
! 2124: t[0] = tcg_temp_new();
! 2125: if (dc->op2 == PR_CCS) {
! 2126: cris_evaluate_flags(dc);
! 2127: t_gen_mov_TN_reg(t[0], dc->op1);
! 2128: if (dc->tb_flags & U_FLAG) {
! 2129: t[1] = tcg_temp_new();
! 2130: /* User space is not allowed to touch all flags. */
! 2131: tcg_gen_andi_tl(t[0], t[0], 0x39f);
! 2132: tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
! 2133: tcg_gen_or_tl(t[0], t[1], t[0]);
! 2134: tcg_temp_free(t[1]);
! 2135: }
! 2136: }
! 2137: else
! 2138: t_gen_mov_TN_reg(t[0], dc->op1);
! 2139:
! 2140: t_gen_mov_preg_TN(dc, dc->op2, t[0]);
! 2141: if (dc->op2 == PR_CCS) {
! 2142: cris_update_cc_op(dc, CC_OP_FLAGS, 4);
! 2143: dc->flags_uptodate = 1;
! 2144: }
! 2145: tcg_temp_free(t[0]);
1.1 root 2146: return 2;
2147: }
2148: static unsigned int dec_move_pr(DisasContext *dc)
2149: {
1.1.1.2 ! root 2150: TCGv t0;
! 2151: LOG_DIS("move $p%u, $r%u\n", dc->op1, dc->op2);
1.1 root 2152: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2153:
! 2154: if (dc->op2 == PR_CCS)
! 2155: cris_evaluate_flags(dc);
! 2156:
! 2157: t0 = tcg_temp_new();
! 2158: t_gen_mov_TN_preg(t0, dc->op2);
! 2159: cris_alu(dc, CC_OP_MOVE,
! 2160: cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]);
! 2161: tcg_temp_free(t0);
1.1 root 2162: return 2;
2163: }
2164:
2165: static unsigned int dec_move_mr(DisasContext *dc)
2166: {
2167: int memsize = memsize_zz(dc);
2168: int insn_len;
1.1.1.2 ! root 2169: LOG_DIS("move.%c [$r%u%s, $r%u\n",
1.1 root 2170: memsize_char(memsize),
2171: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2172: dc->op2);
1.1 root 2173:
1.1.1.2 ! root 2174: if (memsize == 4) {
! 2175: insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
! 2176: cris_cc_mask(dc, CC_MASK_NZ);
! 2177: cris_update_cc_op(dc, CC_OP_MOVE, 4);
! 2178: cris_update_cc_x(dc);
! 2179: cris_update_result(dc, cpu_R[dc->op2]);
! 2180: }
! 2181: else {
! 2182: TCGv t0;
! 2183:
! 2184: t0 = tcg_temp_new();
! 2185: insn_len = dec_prep_move_m(dc, 0, memsize, t0);
! 2186: cris_cc_mask(dc, CC_MASK_NZ);
! 2187: cris_alu(dc, CC_OP_MOVE,
! 2188: cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
! 2189: tcg_temp_free(t0);
! 2190: }
1.1 root 2191: do_postinc(dc, memsize);
2192: return insn_len;
2193: }
2194:
1.1.1.2 ! root 2195: static inline void cris_alu_m_alloc_temps(TCGv *t)
! 2196: {
! 2197: t[0] = tcg_temp_new();
! 2198: t[1] = tcg_temp_new();
! 2199: }
! 2200:
! 2201: static inline void cris_alu_m_free_temps(TCGv *t)
! 2202: {
! 2203: tcg_temp_free(t[0]);
! 2204: tcg_temp_free(t[1]);
! 2205: }
! 2206:
1.1 root 2207: static unsigned int dec_movs_m(DisasContext *dc)
2208: {
1.1.1.2 ! root 2209: TCGv t[2];
1.1 root 2210: int memsize = memsize_z(dc);
2211: int insn_len;
1.1.1.2 ! root 2212: LOG_DIS("movs.%c [$r%u%s, $r%u\n",
1.1 root 2213: memsize_char(memsize),
2214: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2215: dc->op2);
1.1 root 2216:
1.1.1.2 ! root 2217: cris_alu_m_alloc_temps(t);
1.1 root 2218: /* sign extend. */
1.1.1.2 ! root 2219: insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
1.1 root 2220: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 2221: cris_alu(dc, CC_OP_MOVE,
! 2222: cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
1.1 root 2223: do_postinc(dc, memsize);
1.1.1.2 ! root 2224: cris_alu_m_free_temps(t);
1.1 root 2225: return insn_len;
2226: }
2227:
2228: static unsigned int dec_addu_m(DisasContext *dc)
2229: {
1.1.1.2 ! root 2230: TCGv t[2];
1.1 root 2231: int memsize = memsize_z(dc);
2232: int insn_len;
1.1.1.2 ! root 2233: LOG_DIS("addu.%c [$r%u%s, $r%u\n",
1.1 root 2234: memsize_char(memsize),
2235: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2236: dc->op2);
1.1 root 2237:
1.1.1.2 ! root 2238: cris_alu_m_alloc_temps(t);
1.1 root 2239: /* sign extend. */
1.1.1.2 ! root 2240: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2241: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2242: cris_alu(dc, CC_OP_ADD,
! 2243: cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
1.1 root 2244: do_postinc(dc, memsize);
1.1.1.2 ! root 2245: cris_alu_m_free_temps(t);
1.1 root 2246: return insn_len;
2247: }
2248:
2249: static unsigned int dec_adds_m(DisasContext *dc)
2250: {
1.1.1.2 ! root 2251: TCGv t[2];
1.1 root 2252: int memsize = memsize_z(dc);
2253: int insn_len;
1.1.1.2 ! root 2254: LOG_DIS("adds.%c [$r%u%s, $r%u\n",
1.1 root 2255: memsize_char(memsize),
2256: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2257: dc->op2);
1.1 root 2258:
1.1.1.2 ! root 2259: cris_alu_m_alloc_temps(t);
1.1 root 2260: /* sign extend. */
1.1.1.2 ! root 2261: insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
1.1 root 2262: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2263: cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
1.1 root 2264: do_postinc(dc, memsize);
1.1.1.2 ! root 2265: cris_alu_m_free_temps(t);
1.1 root 2266: return insn_len;
2267: }
2268:
2269: static unsigned int dec_subu_m(DisasContext *dc)
2270: {
1.1.1.2 ! root 2271: TCGv t[2];
1.1 root 2272: int memsize = memsize_z(dc);
2273: int insn_len;
1.1.1.2 ! root 2274: LOG_DIS("subu.%c [$r%u%s, $r%u\n",
1.1 root 2275: memsize_char(memsize),
2276: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2277: dc->op2);
1.1 root 2278:
1.1.1.2 ! root 2279: cris_alu_m_alloc_temps(t);
1.1 root 2280: /* sign extend. */
1.1.1.2 ! root 2281: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2282: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2283: cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
1.1 root 2284: do_postinc(dc, memsize);
1.1.1.2 ! root 2285: cris_alu_m_free_temps(t);
1.1 root 2286: return insn_len;
2287: }
2288:
2289: static unsigned int dec_subs_m(DisasContext *dc)
2290: {
1.1.1.2 ! root 2291: TCGv t[2];
1.1 root 2292: int memsize = memsize_z(dc);
2293: int insn_len;
1.1.1.2 ! root 2294: LOG_DIS("subs.%c [$r%u%s, $r%u\n",
1.1 root 2295: memsize_char(memsize),
2296: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2297: dc->op2);
1.1 root 2298:
1.1.1.2 ! root 2299: cris_alu_m_alloc_temps(t);
1.1 root 2300: /* sign extend. */
1.1.1.2 ! root 2301: insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
1.1 root 2302: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2303: cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
1.1 root 2304: do_postinc(dc, memsize);
1.1.1.2 ! root 2305: cris_alu_m_free_temps(t);
1.1 root 2306: return insn_len;
2307: }
2308:
2309: static unsigned int dec_movu_m(DisasContext *dc)
2310: {
1.1.1.2 ! root 2311: TCGv t[2];
1.1 root 2312: int memsize = memsize_z(dc);
2313: int insn_len;
2314:
1.1.1.2 ! root 2315: LOG_DIS("movu.%c [$r%u%s, $r%u\n",
1.1 root 2316: memsize_char(memsize),
2317: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2318: dc->op2);
1.1 root 2319:
1.1.1.2 ! root 2320: cris_alu_m_alloc_temps(t);
! 2321: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2322: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 2323: cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
1.1 root 2324: do_postinc(dc, memsize);
1.1.1.2 ! root 2325: cris_alu_m_free_temps(t);
1.1 root 2326: return insn_len;
2327: }
2328:
2329: static unsigned int dec_cmpu_m(DisasContext *dc)
2330: {
1.1.1.2 ! root 2331: TCGv t[2];
1.1 root 2332: int memsize = memsize_z(dc);
2333: int insn_len;
1.1.1.2 ! root 2334: LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
1.1 root 2335: memsize_char(memsize),
2336: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2337: dc->op2);
1.1 root 2338:
1.1.1.2 ! root 2339: cris_alu_m_alloc_temps(t);
! 2340: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2341: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2342: cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
1.1 root 2343: do_postinc(dc, memsize);
1.1.1.2 ! root 2344: cris_alu_m_free_temps(t);
1.1 root 2345: return insn_len;
2346: }
2347:
2348: static unsigned int dec_cmps_m(DisasContext *dc)
2349: {
1.1.1.2 ! root 2350: TCGv t[2];
1.1 root 2351: int memsize = memsize_z(dc);
2352: int insn_len;
1.1.1.2 ! root 2353: LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
1.1 root 2354: memsize_char(memsize),
2355: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2356: dc->op2);
1.1 root 2357:
1.1.1.2 ! root 2358: cris_alu_m_alloc_temps(t);
! 2359: insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
1.1 root 2360: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2361: cris_alu(dc, CC_OP_CMP,
! 2362: cpu_R[dc->op2], cpu_R[dc->op2], t[1],
! 2363: memsize_zz(dc));
1.1 root 2364: do_postinc(dc, memsize);
1.1.1.2 ! root 2365: cris_alu_m_free_temps(t);
1.1 root 2366: return insn_len;
2367: }
2368:
2369: static unsigned int dec_cmp_m(DisasContext *dc)
2370: {
1.1.1.2 ! root 2371: TCGv t[2];
1.1 root 2372: int memsize = memsize_zz(dc);
2373: int insn_len;
1.1.1.2 ! root 2374: LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
1.1 root 2375: memsize_char(memsize),
2376: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2377: dc->op2);
1.1 root 2378:
1.1.1.2 ! root 2379: cris_alu_m_alloc_temps(t);
! 2380: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2381: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2382: cris_alu(dc, CC_OP_CMP,
! 2383: cpu_R[dc->op2], cpu_R[dc->op2], t[1],
! 2384: memsize_zz(dc));
1.1 root 2385: do_postinc(dc, memsize);
1.1.1.2 ! root 2386: cris_alu_m_free_temps(t);
1.1 root 2387: return insn_len;
2388: }
2389:
2390: static unsigned int dec_test_m(DisasContext *dc)
2391: {
1.1.1.2 ! root 2392: TCGv t[2];
1.1 root 2393: int memsize = memsize_zz(dc);
2394: int insn_len;
1.1.1.2 ! root 2395: LOG_DIS("test.%d [$r%u%s] op2=%x\n",
1.1 root 2396: memsize_char(memsize),
2397: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2398: dc->op2);
1.1 root 2399:
1.1.1.2 ! root 2400: cris_evaluate_flags(dc);
! 2401:
! 2402: cris_alu_m_alloc_temps(t);
! 2403: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2404: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 2405: tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
! 2406:
! 2407: cris_alu(dc, CC_OP_CMP,
! 2408: cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
1.1 root 2409: do_postinc(dc, memsize);
1.1.1.2 ! root 2410: cris_alu_m_free_temps(t);
1.1 root 2411: return insn_len;
2412: }
2413:
2414: static unsigned int dec_and_m(DisasContext *dc)
2415: {
1.1.1.2 ! root 2416: TCGv t[2];
1.1 root 2417: int memsize = memsize_zz(dc);
2418: int insn_len;
1.1.1.2 ! root 2419: LOG_DIS("and.%d [$r%u%s, $r%u\n",
1.1 root 2420: memsize_char(memsize),
2421: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2422: dc->op2);
1.1 root 2423:
1.1.1.2 ! root 2424: cris_alu_m_alloc_temps(t);
! 2425: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2426: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 2427: cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
1.1 root 2428: do_postinc(dc, memsize);
1.1.1.2 ! root 2429: cris_alu_m_free_temps(t);
1.1 root 2430: return insn_len;
2431: }
2432:
2433: static unsigned int dec_add_m(DisasContext *dc)
2434: {
1.1.1.2 ! root 2435: TCGv t[2];
1.1 root 2436: int memsize = memsize_zz(dc);
2437: int insn_len;
1.1.1.2 ! root 2438: LOG_DIS("add.%d [$r%u%s, $r%u\n",
1.1 root 2439: memsize_char(memsize),
2440: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2441: dc->op2);
1.1 root 2442:
1.1.1.2 ! root 2443: cris_alu_m_alloc_temps(t);
! 2444: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2445: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2446: cris_alu(dc, CC_OP_ADD,
! 2447: cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
1.1 root 2448: do_postinc(dc, memsize);
1.1.1.2 ! root 2449: cris_alu_m_free_temps(t);
1.1 root 2450: return insn_len;
2451: }
2452:
2453: static unsigned int dec_addo_m(DisasContext *dc)
2454: {
1.1.1.2 ! root 2455: TCGv t[2];
1.1 root 2456: int memsize = memsize_zz(dc);
2457: int insn_len;
1.1.1.2 ! root 2458: LOG_DIS("add.%d [$r%u%s, $r%u\n",
1.1 root 2459: memsize_char(memsize),
2460: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2461: dc->op2);
1.1 root 2462:
1.1.1.2 ! root 2463: cris_alu_m_alloc_temps(t);
! 2464: insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
1.1 root 2465: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2466: cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
1.1 root 2467: do_postinc(dc, memsize);
1.1.1.2 ! root 2468: cris_alu_m_free_temps(t);
1.1 root 2469: return insn_len;
2470: }
2471:
2472: static unsigned int dec_bound_m(DisasContext *dc)
2473: {
1.1.1.2 ! root 2474: TCGv l[2];
1.1 root 2475: int memsize = memsize_zz(dc);
2476: int insn_len;
1.1.1.2 ! root 2477: LOG_DIS("bound.%d [$r%u%s, $r%u\n",
1.1 root 2478: memsize_char(memsize),
2479: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2480: dc->op2);
1.1 root 2481:
1.1.1.2 ! root 2482: l[0] = tcg_temp_local_new();
! 2483: l[1] = tcg_temp_local_new();
! 2484: insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
1.1 root 2485: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 2486: cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
1.1 root 2487: do_postinc(dc, memsize);
1.1.1.2 ! root 2488: tcg_temp_free(l[0]);
! 2489: tcg_temp_free(l[1]);
1.1 root 2490: return insn_len;
2491: }
2492:
2493: static unsigned int dec_addc_mr(DisasContext *dc)
2494: {
1.1.1.2 ! root 2495: TCGv t[2];
1.1 root 2496: int insn_len = 2;
1.1.1.2 ! root 2497: LOG_DIS("addc [$r%u%s, $r%u\n",
1.1 root 2498: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2499: dc->op2);
1.1 root 2500:
2501: cris_evaluate_flags(dc);
1.1.1.2 ! root 2502:
! 2503: /* Set for this insn. */
! 2504: dc->flagx_known = 1;
! 2505: dc->flags_x = X_FLAG;
! 2506:
! 2507: cris_alu_m_alloc_temps(t);
! 2508: insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
1.1 root 2509: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2510: cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
1.1 root 2511: do_postinc(dc, 4);
1.1.1.2 ! root 2512: cris_alu_m_free_temps(t);
1.1 root 2513: return insn_len;
2514: }
2515:
2516: static unsigned int dec_sub_m(DisasContext *dc)
2517: {
1.1.1.2 ! root 2518: TCGv t[2];
1.1 root 2519: int memsize = memsize_zz(dc);
2520: int insn_len;
1.1.1.2 ! root 2521: LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
1.1 root 2522: memsize_char(memsize),
2523: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2524: dc->op2, dc->ir, dc->zzsize);
1.1 root 2525:
1.1.1.2 ! root 2526: cris_alu_m_alloc_temps(t);
! 2527: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2528: cris_cc_mask(dc, CC_MASK_NZVC);
1.1.1.2 ! root 2529: cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
1.1 root 2530: do_postinc(dc, memsize);
1.1.1.2 ! root 2531: cris_alu_m_free_temps(t);
1.1 root 2532: return insn_len;
2533: }
2534:
2535: static unsigned int dec_or_m(DisasContext *dc)
2536: {
1.1.1.2 ! root 2537: TCGv t[2];
1.1 root 2538: int memsize = memsize_zz(dc);
2539: int insn_len;
1.1.1.2 ! root 2540: LOG_DIS("or.%d [$r%u%s, $r%u pc=%x\n",
1.1 root 2541: memsize_char(memsize),
2542: dc->op1, dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2543: dc->op2, dc->pc);
1.1 root 2544:
1.1.1.2 ! root 2545: cris_alu_m_alloc_temps(t);
! 2546: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2547: cris_cc_mask(dc, CC_MASK_NZ);
1.1.1.2 ! root 2548: cris_alu(dc, CC_OP_OR,
! 2549: cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
1.1 root 2550: do_postinc(dc, memsize);
1.1.1.2 ! root 2551: cris_alu_m_free_temps(t);
1.1 root 2552: return insn_len;
2553: }
2554:
2555: static unsigned int dec_move_mp(DisasContext *dc)
2556: {
1.1.1.2 ! root 2557: TCGv t[2];
1.1 root 2558: int memsize = memsize_zz(dc);
2559: int insn_len = 2;
2560:
1.1.1.2 ! root 2561: LOG_DIS("move.%c [$r%u%s, $p%u\n",
1.1 root 2562: memsize_char(memsize),
2563: dc->op1,
2564: dc->postinc ? "+]" : "]",
1.1.1.2 ! root 2565: dc->op2);
1.1 root 2566:
1.1.1.2 ! root 2567: cris_alu_m_alloc_temps(t);
! 2568: insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
1.1 root 2569: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2570: if (dc->op2 == PR_CCS) {
! 2571: cris_evaluate_flags(dc);
! 2572: if (dc->tb_flags & U_FLAG) {
! 2573: /* User space is not allowed to touch all flags. */
! 2574: tcg_gen_andi_tl(t[1], t[1], 0x39f);
! 2575: tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
! 2576: tcg_gen_or_tl(t[1], t[0], t[1]);
! 2577: }
! 2578: }
! 2579:
! 2580: t_gen_mov_preg_TN(dc, dc->op2, t[1]);
1.1 root 2581:
2582: do_postinc(dc, memsize);
1.1.1.2 ! root 2583: cris_alu_m_free_temps(t);
1.1 root 2584: return insn_len;
2585: }
2586:
2587: static unsigned int dec_move_pm(DisasContext *dc)
2588: {
1.1.1.2 ! root 2589: TCGv t0;
1.1 root 2590: int memsize;
2591:
2592: memsize = preg_sizes[dc->op2];
2593:
1.1.1.2 ! root 2594: LOG_DIS("move.%c $p%u, [$r%u%s\n",
! 2595: memsize_char(memsize),
! 2596: dc->op2, dc->op1, dc->postinc ? "+]" : "]");
! 2597:
! 2598: /* prepare store. Address in T0, value in T1. */
! 2599: if (dc->op2 == PR_CCS)
! 2600: cris_evaluate_flags(dc);
! 2601: t0 = tcg_temp_new();
! 2602: t_gen_mov_TN_preg(t0, dc->op2);
! 2603: cris_flush_cc_state(dc);
! 2604: gen_store(dc, cpu_R[dc->op1], t0, memsize);
! 2605: tcg_temp_free(t0);
1.1 root 2606:
2607: cris_cc_mask(dc, 0);
2608: if (dc->postinc)
1.1.1.2 ! root 2609: tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
1.1 root 2610: return 2;
2611: }
2612:
2613: static unsigned int dec_movem_mr(DisasContext *dc)
2614: {
1.1.1.2 ! root 2615: TCGv_i64 tmp[16];
! 2616: TCGv tmp32;
! 2617: TCGv addr;
1.1 root 2618: int i;
1.1.1.2 ! root 2619: int nr = dc->op2 + 1;
1.1 root 2620:
1.1.1.2 ! root 2621: LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
! 2622: dc->postinc ? "+]" : "]", dc->op2);
1.1 root 2623:
1.1.1.2 ! root 2624: addr = tcg_temp_new();
! 2625: /* There are probably better ways of doing this. */
! 2626: cris_flush_cc_state(dc);
! 2627: for (i = 0; i < (nr >> 1); i++) {
! 2628: tmp[i] = tcg_temp_new_i64();
! 2629: tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
! 2630: gen_load64(dc, tmp[i], addr);
! 2631: }
! 2632: if (nr & 1) {
! 2633: tmp32 = tcg_temp_new_i32();
! 2634: tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
! 2635: gen_load(dc, tmp32, addr, 4, 0);
! 2636: } else
! 2637: TCGV_UNUSED(tmp32);
! 2638: tcg_temp_free(addr);
! 2639:
! 2640: for (i = 0; i < (nr >> 1); i++) {
! 2641: tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
! 2642: tcg_gen_shri_i64(tmp[i], tmp[i], 32);
! 2643: tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
! 2644: tcg_temp_free_i64(tmp[i]);
! 2645: }
! 2646: if (nr & 1) {
! 2647: tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
! 2648: tcg_temp_free(tmp32);
1.1 root 2649: }
1.1.1.2 ! root 2650:
! 2651: /* writeback the updated pointer value. */
! 2652: if (dc->postinc)
! 2653: tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
! 2654:
! 2655: /* gen_load might want to evaluate the previous insns flags. */
! 2656: cris_cc_mask(dc, 0);
1.1 root 2657: return 2;
2658: }
2659:
2660: static unsigned int dec_movem_rm(DisasContext *dc)
2661: {
1.1.1.2 ! root 2662: TCGv tmp;
! 2663: TCGv addr;
1.1 root 2664: int i;
2665:
1.1.1.2 ! root 2666: LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
! 2667: dc->postinc ? "+]" : "]");
1.1 root 2668:
1.1.1.2 ! root 2669: cris_flush_cc_state(dc);
1.1 root 2670:
1.1.1.2 ! root 2671: tmp = tcg_temp_new();
! 2672: addr = tcg_temp_new();
! 2673: tcg_gen_movi_tl(tmp, 4);
! 2674: tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
! 2675: for (i = 0; i <= dc->op2; i++) {
! 2676: /* Displace addr. */
1.1 root 2677: /* Perform the store. */
1.1.1.2 ! root 2678: gen_store(dc, addr, cpu_R[i], 4);
! 2679: tcg_gen_add_tl(addr, addr, tmp);
1.1 root 2680: }
1.1.1.2 ! root 2681: if (dc->postinc)
! 2682: tcg_gen_mov_tl(cpu_R[dc->op1], addr);
! 2683: cris_cc_mask(dc, 0);
! 2684: tcg_temp_free(tmp);
! 2685: tcg_temp_free(addr);
1.1 root 2686: return 2;
2687: }
2688:
2689: static unsigned int dec_move_rm(DisasContext *dc)
2690: {
2691: int memsize;
2692:
2693: memsize = memsize_zz(dc);
2694:
1.1.1.2 ! root 2695: LOG_DIS("move.%d $r%u, [$r%u]\n",
! 2696: memsize, dc->op2, dc->op1);
1.1 root 2697:
2698: /* prepare store. */
1.1.1.2 ! root 2699: cris_flush_cc_state(dc);
! 2700: gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
! 2701:
1.1 root 2702: if (dc->postinc)
1.1.1.2 ! root 2703: tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
! 2704: cris_cc_mask(dc, 0);
1.1 root 2705: return 2;
2706: }
2707:
2708: static unsigned int dec_lapcq(DisasContext *dc)
2709: {
1.1.1.2 ! root 2710: LOG_DIS("lapcq %x, $r%u\n",
! 2711: dc->pc + dc->op1*2, dc->op2);
1.1 root 2712: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2713: tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
1.1 root 2714: return 2;
2715: }
2716:
2717: static unsigned int dec_lapc_im(DisasContext *dc)
2718: {
2719: unsigned int rd;
2720: int32_t imm;
1.1.1.2 ! root 2721: int32_t pc;
1.1 root 2722:
2723: rd = dc->op2;
2724:
2725: cris_cc_mask(dc, 0);
2726: imm = ldl_code(dc->pc + 2);
1.1.1.2 ! root 2727: LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
! 2728:
! 2729: pc = dc->pc;
! 2730: pc += imm;
! 2731: t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
! 2732: return 6;
1.1 root 2733: }
2734:
2735: /* Jump to special reg. */
2736: static unsigned int dec_jump_p(DisasContext *dc)
2737: {
1.1.1.2 ! root 2738: LOG_DIS("jump $p%u\n", dc->op2);
! 2739:
! 2740: if (dc->op2 == PR_CCS)
! 2741: cris_evaluate_flags(dc);
! 2742: t_gen_mov_TN_preg(env_btarget, dc->op2);
! 2743: /* rete will often have low bit set to indicate delayslot. */
! 2744: tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
1.1 root 2745: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2746: cris_prepare_jmp(dc, JMP_INDIRECT);
1.1 root 2747: return 2;
2748: }
2749:
2750: /* Jump and save. */
2751: static unsigned int dec_jas_r(DisasContext *dc)
2752: {
1.1.1.2 ! root 2753: LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
1.1 root 2754: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2755: /* Store the return address in Pd. */
! 2756: tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
! 2757: if (dc->op2 > 15)
! 2758: abort();
! 2759: t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
! 2760:
! 2761: cris_prepare_jmp(dc, JMP_INDIRECT);
1.1 root 2762: return 2;
2763: }
2764:
2765: static unsigned int dec_jas_im(DisasContext *dc)
2766: {
2767: uint32_t imm;
2768:
2769: imm = ldl_code(dc->pc + 2);
2770:
1.1.1.2 ! root 2771: LOG_DIS("jas 0x%x\n", imm);
1.1 root 2772: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2773: /* Store the return address in Pd. */
! 2774: t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
! 2775:
! 2776: dc->jmp_pc = imm;
! 2777: cris_prepare_jmp(dc, JMP_DIRECT);
1.1 root 2778: return 6;
2779: }
2780:
2781: static unsigned int dec_jasc_im(DisasContext *dc)
2782: {
2783: uint32_t imm;
2784:
2785: imm = ldl_code(dc->pc + 2);
2786:
1.1.1.2 ! root 2787: LOG_DIS("jasc 0x%x\n", imm);
1.1 root 2788: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2789: /* Store the return address in Pd. */
! 2790: t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
! 2791:
! 2792: dc->jmp_pc = imm;
! 2793: cris_prepare_jmp(dc, JMP_DIRECT);
1.1 root 2794: return 6;
2795: }
2796:
2797: static unsigned int dec_jasc_r(DisasContext *dc)
2798: {
1.1.1.2 ! root 2799: LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
1.1 root 2800: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2801: /* Store the return address in Pd. */
! 2802: tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
! 2803: t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
! 2804: cris_prepare_jmp(dc, JMP_INDIRECT);
1.1 root 2805: return 2;
2806: }
2807:
2808: static unsigned int dec_bcc_im(DisasContext *dc)
2809: {
2810: int32_t offset;
2811: uint32_t cond = dc->op2;
2812:
1.1.1.2 ! root 2813: offset = ldsw_code(dc->pc + 2);
1.1 root 2814:
1.1.1.2 ! root 2815: LOG_DIS("b%s %d pc=%x dst=%x\n",
1.1 root 2816: cc_name(cond), offset,
1.1.1.2 ! root 2817: dc->pc, dc->pc + offset);
1.1 root 2818:
2819: cris_cc_mask(dc, 0);
2820: /* op2 holds the condition-code. */
2821: cris_prepare_cc_branch (dc, offset, cond);
2822: return 4;
2823: }
2824:
2825: static unsigned int dec_bas_im(DisasContext *dc)
2826: {
2827: int32_t simm;
2828:
2829:
2830: simm = ldl_code(dc->pc + 2);
2831:
1.1.1.2 ! root 2832: LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
1.1 root 2833: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2834: /* Store the return address in Pd. */
! 2835: t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
! 2836:
! 2837: dc->jmp_pc = dc->pc + simm;
! 2838: cris_prepare_jmp(dc, JMP_DIRECT);
1.1 root 2839: return 6;
2840: }
2841:
2842: static unsigned int dec_basc_im(DisasContext *dc)
2843: {
2844: int32_t simm;
2845: simm = ldl_code(dc->pc + 2);
2846:
1.1.1.2 ! root 2847: LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
1.1 root 2848: cris_cc_mask(dc, 0);
1.1.1.2 ! root 2849: /* Store the return address in Pd. */
! 2850: t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
! 2851:
! 2852: dc->jmp_pc = dc->pc + simm;
! 2853: cris_prepare_jmp(dc, JMP_DIRECT);
1.1 root 2854: return 6;
2855: }
2856:
2857: static unsigned int dec_rfe_etc(DisasContext *dc)
2858: {
2859: cris_cc_mask(dc, 0);
2860:
1.1.1.2 ! root 2861: if (dc->op2 == 15) {
! 2862: t_gen_mov_env_TN(halted, tcg_const_tl(1));
! 2863: tcg_gen_movi_tl(env_pc, dc->pc + 2);
! 2864: t_gen_raise_exception(EXCP_HLT);
! 2865: return 2;
! 2866: }
1.1 root 2867:
2868: switch (dc->op2 & 7) {
2869: case 2:
2870: /* rfe. */
1.1.1.2 ! root 2871: LOG_DIS("rfe\n");
1.1 root 2872: cris_evaluate_flags(dc);
1.1.1.2 ! root 2873: gen_helper_rfe();
! 2874: dc->is_jmp = DISAS_UPDATE;
1.1 root 2875: break;
2876: case 5:
2877: /* rfn. */
1.1.1.2 ! root 2878: LOG_DIS("rfn\n");
! 2879: cris_evaluate_flags(dc);
! 2880: gen_helper_rfn();
! 2881: dc->is_jmp = DISAS_UPDATE;
1.1 root 2882: break;
2883: case 6:
1.1.1.2 ! root 2884: LOG_DIS("break %d\n", dc->op1);
! 2885: cris_evaluate_flags (dc);
1.1 root 2886: /* break. */
1.1.1.2 ! root 2887: tcg_gen_movi_tl(env_pc, dc->pc + 2);
! 2888:
1.1 root 2889: /* Breaks start at 16 in the exception vector. */
1.1.1.2 ! root 2890: t_gen_mov_env_TN(trap_vector,
! 2891: tcg_const_tl(dc->op1 + 16));
! 2892: t_gen_raise_exception(EXCP_BREAK);
! 2893: dc->is_jmp = DISAS_UPDATE;
1.1 root 2894: break;
2895: default:
2896: printf ("op2=%x\n", dc->op2);
2897: BUG();
2898: break;
2899:
2900: }
1.1.1.2 ! root 2901: return 2;
! 2902: }
! 2903:
! 2904: static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
! 2905: {
! 2906: return 2;
! 2907: }
! 2908:
! 2909: static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
! 2910: {
1.1 root 2911: return 2;
2912: }
2913:
2914: static unsigned int dec_null(DisasContext *dc)
2915: {
2916: printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2917: dc->pc, dc->opcode, dc->op1, dc->op2);
2918: fflush(NULL);
2919: BUG();
2920: return 2;
2921: }
2922:
1.1.1.2 ! root 2923: static struct decoder_info {
1.1 root 2924: struct {
2925: uint32_t bits;
2926: uint32_t mask;
2927: };
2928: unsigned int (*dec)(DisasContext *dc);
2929: } decinfo[] = {
2930: /* Order matters here. */
2931: {DEC_MOVEQ, dec_moveq},
2932: {DEC_BTSTQ, dec_btstq},
2933: {DEC_CMPQ, dec_cmpq},
2934: {DEC_ADDOQ, dec_addoq},
2935: {DEC_ADDQ, dec_addq},
2936: {DEC_SUBQ, dec_subq},
2937: {DEC_ANDQ, dec_andq},
2938: {DEC_ORQ, dec_orq},
2939: {DEC_ASRQ, dec_asrq},
2940: {DEC_LSLQ, dec_lslq},
2941: {DEC_LSRQ, dec_lsrq},
2942: {DEC_BCCQ, dec_bccq},
2943:
2944: {DEC_BCC_IM, dec_bcc_im},
2945: {DEC_JAS_IM, dec_jas_im},
2946: {DEC_JAS_R, dec_jas_r},
2947: {DEC_JASC_IM, dec_jasc_im},
2948: {DEC_JASC_R, dec_jasc_r},
2949: {DEC_BAS_IM, dec_bas_im},
2950: {DEC_BASC_IM, dec_basc_im},
2951: {DEC_JUMP_P, dec_jump_p},
2952: {DEC_LAPC_IM, dec_lapc_im},
2953: {DEC_LAPCQ, dec_lapcq},
2954:
2955: {DEC_RFE_ETC, dec_rfe_etc},
2956: {DEC_ADDC_MR, dec_addc_mr},
2957:
2958: {DEC_MOVE_MP, dec_move_mp},
2959: {DEC_MOVE_PM, dec_move_pm},
2960: {DEC_MOVEM_MR, dec_movem_mr},
2961: {DEC_MOVEM_RM, dec_movem_rm},
2962: {DEC_MOVE_PR, dec_move_pr},
2963: {DEC_SCC_R, dec_scc_r},
2964: {DEC_SETF, dec_setclrf},
2965: {DEC_CLEARF, dec_setclrf},
2966:
2967: {DEC_MOVE_SR, dec_move_sr},
2968: {DEC_MOVE_RP, dec_move_rp},
2969: {DEC_SWAP_R, dec_swap_r},
2970: {DEC_ABS_R, dec_abs_r},
2971: {DEC_LZ_R, dec_lz_r},
2972: {DEC_MOVE_RS, dec_move_rs},
2973: {DEC_BTST_R, dec_btst_r},
2974: {DEC_ADDC_R, dec_addc_r},
2975:
2976: {DEC_DSTEP_R, dec_dstep_r},
2977: {DEC_XOR_R, dec_xor_r},
2978: {DEC_MCP_R, dec_mcp_r},
2979: {DEC_CMP_R, dec_cmp_r},
2980:
2981: {DEC_ADDI_R, dec_addi_r},
2982: {DEC_ADDI_ACR, dec_addi_acr},
2983:
2984: {DEC_ADD_R, dec_add_r},
2985: {DEC_SUB_R, dec_sub_r},
2986:
2987: {DEC_ADDU_R, dec_addu_r},
2988: {DEC_ADDS_R, dec_adds_r},
2989: {DEC_SUBU_R, dec_subu_r},
2990: {DEC_SUBS_R, dec_subs_r},
2991: {DEC_LSL_R, dec_lsl_r},
2992:
2993: {DEC_AND_R, dec_and_r},
2994: {DEC_OR_R, dec_or_r},
2995: {DEC_BOUND_R, dec_bound_r},
2996: {DEC_ASR_R, dec_asr_r},
2997: {DEC_LSR_R, dec_lsr_r},
2998:
2999: {DEC_MOVU_R, dec_movu_r},
3000: {DEC_MOVS_R, dec_movs_r},
3001: {DEC_NEG_R, dec_neg_r},
3002: {DEC_MOVE_R, dec_move_r},
3003:
1.1.1.2 ! root 3004: {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
! 3005: {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
1.1 root 3006:
3007: {DEC_MULS_R, dec_muls_r},
3008: {DEC_MULU_R, dec_mulu_r},
3009:
3010: {DEC_ADDU_M, dec_addu_m},
3011: {DEC_ADDS_M, dec_adds_m},
3012: {DEC_SUBU_M, dec_subu_m},
3013: {DEC_SUBS_M, dec_subs_m},
3014:
3015: {DEC_CMPU_M, dec_cmpu_m},
3016: {DEC_CMPS_M, dec_cmps_m},
3017: {DEC_MOVU_M, dec_movu_m},
3018: {DEC_MOVS_M, dec_movs_m},
3019:
3020: {DEC_CMP_M, dec_cmp_m},
3021: {DEC_ADDO_M, dec_addo_m},
3022: {DEC_BOUND_M, dec_bound_m},
3023: {DEC_ADD_M, dec_add_m},
3024: {DEC_SUB_M, dec_sub_m},
3025: {DEC_AND_M, dec_and_m},
3026: {DEC_OR_M, dec_or_m},
3027: {DEC_MOVE_RM, dec_move_rm},
3028: {DEC_TEST_M, dec_test_m},
3029: {DEC_MOVE_MR, dec_move_mr},
3030:
3031: {{0, 0}, dec_null}
3032: };
3033:
3034: static inline unsigned int
3035: cris_decoder(DisasContext *dc)
3036: {
3037: unsigned int insn_len = 2;
3038: int i;
3039:
1.1.1.2 ! root 3040: if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
! 3041: tcg_gen_debug_insn_start(dc->pc);
! 3042:
1.1 root 3043: /* Load a halfword onto the instruction register. */
1.1.1.2 ! root 3044: dc->ir = lduw_code(dc->pc);
1.1 root 3045:
3046: /* Now decode it. */
3047: dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3048: dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3049: dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3050: dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3051: dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3052: dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3053:
3054: /* Large switch for all insns. */
1.1.1.2 ! root 3055: for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1.1 root 3056: if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3057: {
3058: insn_len = decinfo[i].dec(dc);
3059: break;
3060: }
3061: }
3062:
1.1.1.2 ! root 3063: #if !defined(CONFIG_USER_ONLY)
! 3064: /* Single-stepping ? */
! 3065: if (dc->tb_flags & S_FLAG) {
! 3066: int l1;
! 3067:
! 3068: l1 = gen_new_label();
! 3069: tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
! 3070: /* We treat SPC as a break with an odd trap vector. */
! 3071: cris_evaluate_flags (dc);
! 3072: t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
! 3073: tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
! 3074: tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
! 3075: t_gen_raise_exception(EXCP_BREAK);
! 3076: gen_set_label(l1);
! 3077: }
! 3078: #endif
1.1 root 3079: return insn_len;
3080: }
3081:
3082: static void check_breakpoint(CPUState *env, DisasContext *dc)
3083: {
1.1.1.2 ! root 3084: CPUBreakpoint *bp;
! 3085:
! 3086: if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
! 3087: TAILQ_FOREACH(bp, &env->breakpoints, entry) {
! 3088: if (bp->pc == dc->pc) {
1.1 root 3089: cris_evaluate_flags (dc);
1.1.1.2 ! root 3090: tcg_gen_movi_tl(env_pc, dc->pc);
! 3091: t_gen_raise_exception(EXCP_DEBUG);
1.1 root 3092: dc->is_jmp = DISAS_UPDATE;
3093: }
3094: }
3095: }
3096: }
3097:
3098:
1.1.1.2 ! root 3099: /*
! 3100: * Delay slots on QEMU/CRIS.
! 3101: *
! 3102: * If an exception hits on a delayslot, the core will let ERP (the Exception
! 3103: * Return Pointer) point to the branch (the previous) insn and set the lsb to
! 3104: * to give SW a hint that the exception actually hit on the dslot.
! 3105: *
! 3106: * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
! 3107: * the core and any jmp to an odd addresses will mask off that lsb. It is
! 3108: * simply there to let sw know there was an exception on a dslot.
! 3109: *
! 3110: * When the software returns from an exception, the branch will re-execute.
! 3111: * On QEMU care needs to be taken when a branch+delayslot sequence is broken
! 3112: * and the branch and delayslot dont share pages.
! 3113: *
! 3114: * The TB contaning the branch insn will set up env->btarget and evaluate
! 3115: * env->btaken. When the translation loop exits we will note that the branch
! 3116: * sequence is broken and let env->dslot be the size of the branch insn (those
! 3117: * vary in length).
! 3118: *
! 3119: * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
! 3120: * set). It will also expect to have env->dslot setup with the size of the
! 3121: * delay slot so that env->pc - env->dslot point to the branch insn. This TB
! 3122: * will execute the dslot and take the branch, either to btarget or just one
! 3123: * insn ahead.
! 3124: *
! 3125: * When exceptions occur, we check for env->dslot in do_interrupt to detect
! 3126: * broken branch sequences and setup $erp accordingly (i.e let it point to the
! 3127: * branch and set lsb). Then env->dslot gets cleared so that the exception
! 3128: * handler can enter. When returning from exceptions (jump $erp) the lsb gets
! 3129: * masked off and we will reexecute the branch insn.
! 3130: *
! 3131: */
! 3132:
1.1 root 3133: /* generate intermediate code for basic block 'tb'. */
1.1.1.2 ! root 3134: static void
1.1 root 3135: gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3136: int search_pc)
3137: {
3138: uint16_t *gen_opc_end;
3139: uint32_t pc_start;
3140: unsigned int insn_len;
3141: int j, lj;
1.1.1.2 ! root 3142: struct DisasContext ctx;
1.1 root 3143: struct DisasContext *dc = &ctx;
3144: uint32_t next_page_start;
1.1.1.2 ! root 3145: target_ulong npc;
! 3146: int num_insns;
! 3147: int max_insns;
! 3148:
! 3149: qemu_log_try_set_file(stderr);
! 3150:
! 3151: /* Odd PC indicates that branch is rexecuting due to exception in the
! 3152: * delayslot, like in real hw.
! 3153: */
! 3154: pc_start = tb->pc & ~1;
1.1 root 3155: dc->env = env;
3156: dc->tb = tb;
3157:
3158: gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3159:
3160: dc->is_jmp = DISAS_NEXT;
1.1.1.2 ! root 3161: dc->ppc = pc_start;
1.1 root 3162: dc->pc = pc_start;
3163: dc->singlestep_enabled = env->singlestep_enabled;
1.1.1.2 ! root 3164: dc->flags_uptodate = 1;
! 3165: dc->flagx_known = 1;
! 3166: dc->flags_x = tb->flags & X_FLAG;
! 3167: dc->cc_x_uptodate = 0;
! 3168: dc->cc_mask = 0;
! 3169: dc->update_cc = 0;
! 3170:
! 3171: cris_update_cc_op(dc, CC_OP_FLAGS, 4);
! 3172: dc->cc_size_uptodate = -1;
! 3173:
! 3174: /* Decode TB flags. */
! 3175: dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
! 3176: dc->delayed_branch = !!(tb->flags & 7);
! 3177: if (dc->delayed_branch)
! 3178: dc->jmp = JMP_INDIRECT;
! 3179: else
! 3180: dc->jmp = JMP_NOJMP;
! 3181:
! 3182: dc->cpustate_changed = 0;
! 3183:
! 3184: if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
! 3185: qemu_log(
! 3186: "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
! 3187: "pid=%x usp=%x\n"
! 3188: "%x.%x.%x.%x\n"
! 3189: "%x.%x.%x.%x\n"
! 3190: "%x.%x.%x.%x\n"
! 3191: "%x.%x.%x.%x\n",
! 3192: search_pc, dc->pc, dc->ppc,
! 3193: (unsigned long long)tb->flags,
! 3194: env->btarget, (unsigned)tb->flags & 7,
! 3195: env->pregs[PR_CCS],
! 3196: env->pregs[PR_PID], env->pregs[PR_USP],
! 3197: env->regs[0], env->regs[1], env->regs[2], env->regs[3],
! 3198: env->regs[4], env->regs[5], env->regs[6], env->regs[7],
! 3199: env->regs[8], env->regs[9],
! 3200: env->regs[10], env->regs[11],
! 3201: env->regs[12], env->regs[13],
! 3202: env->regs[14], env->regs[15]);
! 3203: qemu_log("--------------\n");
! 3204: qemu_log("IN: %s\n", lookup_symbol(pc_start));
! 3205: }
! 3206:
1.1 root 3207: next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3208: lj = -1;
1.1.1.2 ! root 3209: num_insns = 0;
! 3210: max_insns = tb->cflags & CF_COUNT_MASK;
! 3211: if (max_insns == 0)
! 3212: max_insns = CF_COUNT_MASK;
! 3213:
! 3214: gen_icount_start();
1.1 root 3215: do
3216: {
3217: check_breakpoint(env, dc);
3218:
3219: if (search_pc) {
3220: j = gen_opc_ptr - gen_opc_buf;
3221: if (lj < j) {
3222: lj++;
3223: while (lj < j)
3224: gen_opc_instr_start[lj++] = 0;
3225: }
1.1.1.2 ! root 3226: if (dc->delayed_branch == 1)
! 3227: gen_opc_pc[lj] = dc->ppc | 1;
! 3228: else
! 3229: gen_opc_pc[lj] = dc->pc;
1.1 root 3230: gen_opc_instr_start[lj] = 1;
1.1.1.2 ! root 3231: gen_opc_icount[lj] = num_insns;
1.1 root 3232: }
3233:
1.1.1.2 ! root 3234: /* Pretty disas. */
! 3235: LOG_DIS("%8.8x:\t", dc->pc);
! 3236:
! 3237: if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
! 3238: gen_io_start();
! 3239: dc->clear_x = 1;
! 3240:
! 3241: insn_len = cris_decoder(dc);
! 3242: dc->ppc = dc->pc;
1.1 root 3243: dc->pc += insn_len;
1.1.1.2 ! root 3244: if (dc->clear_x)
! 3245: cris_clear_x_flag(dc);
1.1 root 3246:
1.1.1.2 ! root 3247: num_insns++;
1.1 root 3248: /* Check for delayed branches here. If we do it before
1.1.1.2 ! root 3249: actually generating any host code, the simulator will just
1.1 root 3250: loop doing nothing for on this program location. */
3251: if (dc->delayed_branch) {
3252: dc->delayed_branch--;
3253: if (dc->delayed_branch == 0)
3254: {
1.1.1.2 ! root 3255: if (tb->flags & 7)
! 3256: t_gen_mov_env_TN(dslot,
! 3257: tcg_const_tl(0));
! 3258: if (dc->jmp == JMP_DIRECT) {
! 3259: dc->is_jmp = DISAS_NEXT;
! 3260: } else {
! 3261: t_gen_cc_jmp(env_btarget,
! 3262: tcg_const_tl(dc->pc));
! 3263: dc->is_jmp = DISAS_JUMP;
1.1 root 3264: }
1.1.1.2 ! root 3265: break;
1.1 root 3266: }
3267: }
3268:
1.1.1.2 ! root 3269: /* If we are rexecuting a branch due to exceptions on
! 3270: delay slots dont break. */
! 3271: if (!(tb->pc & 1) && env->singlestep_enabled)
! 3272: break;
! 3273: } while (!dc->is_jmp && !dc->cpustate_changed
! 3274: && gen_opc_ptr < gen_opc_end
! 3275: && (dc->pc < next_page_start)
! 3276: && num_insns < max_insns);
! 3277:
! 3278: npc = dc->pc;
! 3279: if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
! 3280: npc = dc->jmp_pc;
! 3281:
! 3282: if (tb->cflags & CF_LAST_IO)
! 3283: gen_io_end();
! 3284: /* Force an update if the per-tb cpu state has changed. */
! 3285: if (dc->is_jmp == DISAS_NEXT
! 3286: && (dc->cpustate_changed || !dc->flagx_known
! 3287: || (dc->flags_x != (tb->flags & X_FLAG)))) {
! 3288: dc->is_jmp = DISAS_UPDATE;
! 3289: tcg_gen_movi_tl(env_pc, npc);
! 3290: }
! 3291: /* Broken branch+delayslot sequence. */
! 3292: if (dc->delayed_branch == 1) {
! 3293: /* Set env->dslot to the size of the branch insn. */
! 3294: t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
! 3295: cris_store_direct_jmp(dc);
1.1 root 3296: }
3297:
3298: cris_evaluate_flags (dc);
1.1.1.2 ! root 3299:
! 3300: if (unlikely(env->singlestep_enabled)) {
! 3301: if (dc->is_jmp == DISAS_NEXT)
! 3302: tcg_gen_movi_tl(env_pc, npc);
! 3303: t_gen_raise_exception(EXCP_DEBUG);
1.1 root 3304: } else {
3305: switch(dc->is_jmp) {
3306: case DISAS_NEXT:
1.1.1.2 ! root 3307: gen_goto_tb(dc, 1, npc);
1.1 root 3308: break;
3309: default:
3310: case DISAS_JUMP:
3311: case DISAS_UPDATE:
3312: /* indicate that the hash table must be used
3313: to find the next TB */
1.1.1.2 ! root 3314: tcg_gen_exit_tb(0);
1.1 root 3315: break;
1.1.1.2 ! root 3316: case DISAS_SWI:
1.1 root 3317: case DISAS_TB_JUMP:
3318: /* nothing more to generate */
3319: break;
3320: }
3321: }
1.1.1.2 ! root 3322: gen_icount_end(tb, num_insns);
1.1 root 3323: *gen_opc_ptr = INDEX_op_end;
3324: if (search_pc) {
3325: j = gen_opc_ptr - gen_opc_buf;
3326: lj++;
3327: while (lj <= j)
3328: gen_opc_instr_start[lj++] = 0;
3329: } else {
3330: tb->size = dc->pc - pc_start;
1.1.1.2 ! root 3331: tb->icount = num_insns;
1.1 root 3332: }
3333:
3334: #ifdef DEBUG_DISAS
1.1.1.2 ! root 3335: #if !DISAS_CRIS
! 3336: if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
! 3337: log_target_disas(pc_start, dc->pc - pc_start, 0);
! 3338: qemu_log("\nisize=%d osize=%zd\n",
! 3339: dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1.1 root 3340: }
3341: #endif
1.1.1.2 ! root 3342: #endif
1.1 root 3343: }
3344:
1.1.1.2 ! root 3345: void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1.1 root 3346: {
1.1.1.2 ! root 3347: gen_intermediate_code_internal(env, tb, 0);
1.1 root 3348: }
3349:
1.1.1.2 ! root 3350: void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1.1 root 3351: {
1.1.1.2 ! root 3352: gen_intermediate_code_internal(env, tb, 1);
1.1 root 3353: }
3354:
3355: void cpu_dump_state (CPUState *env, FILE *f,
3356: int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3357: int flags)
3358: {
3359: int i;
3360: uint32_t srs;
3361:
3362: if (!env || !f)
3363: return;
3364:
3365: cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
1.1.1.2 ! root 3366: "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
! 3367: env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
1.1 root 3368: env->cc_op,
1.1.1.2 ! root 3369: env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
! 3370:
1.1 root 3371:
3372: for (i = 0; i < 16; i++) {
3373: cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3374: if ((i + 1) % 4 == 0)
3375: cpu_fprintf(f, "\n");
3376: }
3377: cpu_fprintf(f, "\nspecial regs:\n");
3378: for (i = 0; i < 16; i++) {
3379: cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3380: if ((i + 1) % 4 == 0)
3381: cpu_fprintf(f, "\n");
3382: }
1.1.1.2 ! root 3383: srs = env->pregs[PR_SRS];
! 3384: cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
1.1 root 3385: if (srs < 256) {
3386: for (i = 0; i < 16; i++) {
3387: cpu_fprintf(f, "s%2.2d=%8.8x ",
3388: i, env->sregs[srs][i]);
3389: if ((i + 1) % 4 == 0)
3390: cpu_fprintf(f, "\n");
3391: }
3392: }
3393: cpu_fprintf(f, "\n\n");
3394:
3395: }
3396:
3397: CPUCRISState *cpu_cris_init (const char *cpu_model)
3398: {
3399: CPUCRISState *env;
1.1.1.2 ! root 3400: static int tcg_initialized = 0;
! 3401: int i;
1.1 root 3402:
3403: env = qemu_mallocz(sizeof(CPUCRISState));
1.1.1.2 ! root 3404:
1.1 root 3405: cpu_exec_init(env);
3406: cpu_reset(env);
1.1.1.2 ! root 3407:
! 3408: if (tcg_initialized)
! 3409: return env;
! 3410:
! 3411: tcg_initialized = 1;
! 3412:
! 3413: cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
! 3414: cc_x = tcg_global_mem_new(TCG_AREG0,
! 3415: offsetof(CPUState, cc_x), "cc_x");
! 3416: cc_src = tcg_global_mem_new(TCG_AREG0,
! 3417: offsetof(CPUState, cc_src), "cc_src");
! 3418: cc_dest = tcg_global_mem_new(TCG_AREG0,
! 3419: offsetof(CPUState, cc_dest),
! 3420: "cc_dest");
! 3421: cc_result = tcg_global_mem_new(TCG_AREG0,
! 3422: offsetof(CPUState, cc_result),
! 3423: "cc_result");
! 3424: cc_op = tcg_global_mem_new(TCG_AREG0,
! 3425: offsetof(CPUState, cc_op), "cc_op");
! 3426: cc_size = tcg_global_mem_new(TCG_AREG0,
! 3427: offsetof(CPUState, cc_size),
! 3428: "cc_size");
! 3429: cc_mask = tcg_global_mem_new(TCG_AREG0,
! 3430: offsetof(CPUState, cc_mask),
! 3431: "cc_mask");
! 3432:
! 3433: env_pc = tcg_global_mem_new(TCG_AREG0,
! 3434: offsetof(CPUState, pc),
! 3435: "pc");
! 3436: env_btarget = tcg_global_mem_new(TCG_AREG0,
! 3437: offsetof(CPUState, btarget),
! 3438: "btarget");
! 3439: env_btaken = tcg_global_mem_new(TCG_AREG0,
! 3440: offsetof(CPUState, btaken),
! 3441: "btaken");
! 3442: for (i = 0; i < 16; i++) {
! 3443: cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
! 3444: offsetof(CPUState, regs[i]),
! 3445: regnames[i]);
! 3446: }
! 3447: for (i = 0; i < 16; i++) {
! 3448: cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
! 3449: offsetof(CPUState, pregs[i]),
! 3450: pregnames[i]);
! 3451: }
! 3452:
! 3453: #define GEN_HELPER 2
! 3454: #include "helper.h"
! 3455:
1.1 root 3456: return env;
3457: }
3458:
3459: void cpu_reset (CPUCRISState *env)
3460: {
1.1.1.2 ! root 3461: if (qemu_loglevel_mask(CPU_LOG_RESET)) {
! 3462: qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
! 3463: log_cpu_state(env, 0);
! 3464: }
! 3465:
1.1 root 3466: memset(env, 0, offsetof(CPUCRISState, breakpoints));
3467: tlb_flush(env, 1);
1.1.1.2 ! root 3468:
! 3469: env->pregs[PR_VR] = 32;
! 3470: #if defined(CONFIG_USER_ONLY)
! 3471: /* start in user mode with interrupts enabled. */
! 3472: env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
! 3473: #else
! 3474: cris_mmu_init(env);
! 3475: env->pregs[PR_CCS] = 0;
! 3476: #endif
! 3477: }
! 3478:
! 3479: void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
! 3480: unsigned long searched_pc, int pc_pos, void *puc)
! 3481: {
! 3482: env->pc = gen_opc_pc[pc_pos];
1.1 root 3483: }
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