Diff for /qemu/target-i386/cpu.h between versions 1.1.1.11 and 1.1.1.12

version 1.1.1.11, 2018/04/24 19:02:54 version 1.1.1.12, 2018/04/24 19:31:12
Line 283 Line 283
 #define MSR_IA32_APICBASE_BSP           (1<<8)  #define MSR_IA32_APICBASE_BSP           (1<<8)
 #define MSR_IA32_APICBASE_ENABLE        (1<<11)  #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)  #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
   #define MSR_IA32_TSCDEADLINE            0x6e0
   
 #define MSR_MTRRcap                     0xfe  #define MSR_MTRRcap                     0xfe
 #define MSR_MTRRcap_VCNT                8  #define MSR_MTRRcap_VCNT                8
Line 299 Line 300
   
 #define MSR_IA32_PERF_STATUS            0x198  #define MSR_IA32_PERF_STATUS            0x198
   
   #define MSR_IA32_MISC_ENABLE            0x1a0
   /* Indicates good rep/movs microcode on some processors: */
   #define MSR_IA32_MISC_ENABLE_DEFAULT    1
   
 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))  #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)  #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
   
Line 687  typedef struct CPUX86State { Line 692  typedef struct CPUX86State {
     uint64_t async_pf_en_msr;      uint64_t async_pf_en_msr;
   
     uint64_t tsc;      uint64_t tsc;
       uint64_t tsc_deadline;
   
     uint64_t mcg_status;      uint64_t mcg_status;
       uint64_t msr_ia32_misc_enable;
   
     /* exception/interrupt handling */      /* exception/interrupt handling */
     int error_code;      int error_code;
Line 743  typedef struct CPUX86State { Line 750  typedef struct CPUX86State {
     uint32_t cpuid_kvm_features;      uint32_t cpuid_kvm_features;
     uint32_t cpuid_svm_features;      uint32_t cpuid_svm_features;
     bool tsc_valid;      bool tsc_valid;
       int tsc_khz;
           
     /* in order to simplify APIC support, we leave this pointer to the      /* in order to simplify APIC support, we leave this pointer to the
        user */         user */
Line 889  void host_cpuid(uint32_t function, uint3 Line 897  void host_cpuid(uint32_t function, uint3
   
 /* helper.c */  /* helper.c */
 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,  int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                              int is_write, int mmu_idx, int is_softmmu);                               int is_write, int mmu_idx);
 #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault  #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
 void cpu_x86_set_a20(CPUX86State *env, int a20_state);  void cpu_x86_set_a20(CPUX86State *env, int a20_state);
   
Line 990  static inline int cpu_mmu_index (CPUStat Line 998  static inline int cpu_mmu_index (CPUStat
 /* translate.c */  /* translate.c */
 void optimize_flags_init(void);  void optimize_flags_init(void);
   
 typedef struct CCTable {  
     int (*compute_all)(void); /* return all the flags */  
     int (*compute_c)(void);  /* return the C flag */  
 } CCTable;  
   
 #if defined(CONFIG_USER_ONLY)  #if defined(CONFIG_USER_ONLY)
 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)  static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 {  {
Line 1050  void cpu_x86_inject_mce(Monitor *mon, CP Line 1053  void cpu_x86_inject_mce(Monitor *mon, CP
 /* op_helper.c */  /* op_helper.c */
 void do_interrupt(CPUState *env);  void do_interrupt(CPUState *env);
 void do_interrupt_x86_hardirq(CPUState *env, int intno, int is_hw);  void do_interrupt_x86_hardirq(CPUState *env, int intno, int is_hw);
   void QEMU_NORETURN raise_exception_env(int exception_index, CPUState *nenv);
   void QEMU_NORETURN raise_exception_err_env(CPUState *nenv, int exception_index,
                                              int error_code);
   
 void do_smm_enter(CPUState *env1);  void do_smm_enter(CPUState *env1);
   

Removed from v.1.1.1.11  
changed lines
  Added in v.1.1.1.12


unix.superglobalmegacorp.com