File:  [Qemu by Fabrice Bellard] / qemu / target-i386 / cpu.h
Revision 1.1.1.6 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 16:54:56 2018 UTC (3 years, 9 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0105, qemu0104, qemu0103, qemu0102, qemu0101, qemu0100, HEAD
qemu 0.10.0

    1: /*
    2:  * i386 virtual CPU header
    3:  *
    4:  *  Copyright (c) 2003 Fabrice Bellard
    5:  *
    6:  * This library is free software; you can redistribute it and/or
    7:  * modify it under the terms of the GNU Lesser General Public
    8:  * License as published by the Free Software Foundation; either
    9:  * version 2 of the License, or (at your option) any later version.
   10:  *
   11:  * This library is distributed in the hope that it will be useful,
   12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   14:  * Lesser General Public License for more details.
   15:  *
   16:  * You should have received a copy of the GNU Lesser General Public
   17:  * License along with this library; if not, write to the Free Software
   18:  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
   19:  */
   20: #ifndef CPU_I386_H
   21: #define CPU_I386_H
   22: 
   23: #include "config.h"
   24: 
   25: #ifdef TARGET_X86_64
   26: #define TARGET_LONG_BITS 64
   27: #else
   28: #define TARGET_LONG_BITS 32
   29: #endif
   30: 
   31: /* target supports implicit self modifying code */
   32: #define TARGET_HAS_SMC
   33: /* support for self modifying code even if the modified instruction is
   34:    close to the modifying instruction */
   35: #define TARGET_HAS_PRECISE_SMC
   36: 
   37: #define TARGET_HAS_ICE 1
   38: 
   39: #ifdef TARGET_X86_64
   40: #define ELF_MACHINE	EM_X86_64
   41: #else
   42: #define ELF_MACHINE	EM_386
   43: #endif
   44: 
   45: #include "cpu-defs.h"
   46: 
   47: #include "softfloat.h"
   48: 
   49: #define R_EAX 0
   50: #define R_ECX 1
   51: #define R_EDX 2
   52: #define R_EBX 3
   53: #define R_ESP 4
   54: #define R_EBP 5
   55: #define R_ESI 6
   56: #define R_EDI 7
   57: 
   58: #define R_AL 0
   59: #define R_CL 1
   60: #define R_DL 2
   61: #define R_BL 3
   62: #define R_AH 4
   63: #define R_CH 5
   64: #define R_DH 6
   65: #define R_BH 7
   66: 
   67: #define R_ES 0
   68: #define R_CS 1
   69: #define R_SS 2
   70: #define R_DS 3
   71: #define R_FS 4
   72: #define R_GS 5
   73: 
   74: /* segment descriptor fields */
   75: #define DESC_G_MASK     (1 << 23)
   76: #define DESC_B_SHIFT    22
   77: #define DESC_B_MASK     (1 << DESC_B_SHIFT)
   78: #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
   79: #define DESC_L_MASK     (1 << DESC_L_SHIFT)
   80: #define DESC_AVL_MASK   (1 << 20)
   81: #define DESC_P_MASK     (1 << 15)
   82: #define DESC_DPL_SHIFT  13
   83: #define DESC_DPL_MASK   (1 << DESC_DPL_SHIFT)
   84: #define DESC_S_MASK     (1 << 12)
   85: #define DESC_TYPE_SHIFT 8
   86: #define DESC_A_MASK     (1 << 8)
   87: 
   88: #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
   89: #define DESC_C_MASK     (1 << 10) /* code: conforming */
   90: #define DESC_R_MASK     (1 << 9)  /* code: readable */
   91: 
   92: #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
   93: #define DESC_W_MASK     (1 << 9)  /* data: writable */
   94: 
   95: #define DESC_TSS_BUSY_MASK (1 << 9)
   96: 
   97: /* eflags masks */
   98: #define CC_C   	0x0001
   99: #define CC_P 	0x0004
  100: #define CC_A	0x0010
  101: #define CC_Z	0x0040
  102: #define CC_S    0x0080
  103: #define CC_O    0x0800
  104: 
  105: #define TF_SHIFT   8
  106: #define IOPL_SHIFT 12
  107: #define VM_SHIFT   17
  108: 
  109: #define TF_MASK 		0x00000100
  110: #define IF_MASK 		0x00000200
  111: #define DF_MASK 		0x00000400
  112: #define IOPL_MASK		0x00003000
  113: #define NT_MASK	         	0x00004000
  114: #define RF_MASK			0x00010000
  115: #define VM_MASK			0x00020000
  116: #define AC_MASK			0x00040000
  117: #define VIF_MASK                0x00080000
  118: #define VIP_MASK                0x00100000
  119: #define ID_MASK                 0x00200000
  120: 
  121: /* hidden flags - used internally by qemu to represent additional cpu
  122:    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
  123:    redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
  124:    position to ease oring with eflags. */
  125: /* current cpl */
  126: #define HF_CPL_SHIFT         0
  127: /* true if soft mmu is being used */
  128: #define HF_SOFTMMU_SHIFT     2
  129: /* true if hardware interrupts must be disabled for next instruction */
  130: #define HF_INHIBIT_IRQ_SHIFT 3
  131: /* 16 or 32 segments */
  132: #define HF_CS32_SHIFT        4
  133: #define HF_SS32_SHIFT        5
  134: /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
  135: #define HF_ADDSEG_SHIFT      6
  136: /* copy of CR0.PE (protected mode) */
  137: #define HF_PE_SHIFT          7
  138: #define HF_TF_SHIFT          8 /* must be same as eflags */
  139: #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
  140: #define HF_EM_SHIFT         10
  141: #define HF_TS_SHIFT         11
  142: #define HF_IOPL_SHIFT       12 /* must be same as eflags */
  143: #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
  144: #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
  145: #define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
  146: #define HF_VM_SHIFT         17 /* must be same as eflags */
  147: #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
  148: #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
  149: #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
  150: 
  151: #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
  152: #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
  153: #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
  154: #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
  155: #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
  156: #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
  157: #define HF_PE_MASK           (1 << HF_PE_SHIFT)
  158: #define HF_TF_MASK           (1 << HF_TF_SHIFT)
  159: #define HF_MP_MASK           (1 << HF_MP_SHIFT)
  160: #define HF_EM_MASK           (1 << HF_EM_SHIFT)
  161: #define HF_TS_MASK           (1 << HF_TS_SHIFT)
  162: #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
  163: #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
  164: #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
  165: #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
  166: #define HF_VM_MASK           (1 << HF_VM_SHIFT)
  167: #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
  168: #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
  169: #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
  170: 
  171: /* hflags2 */
  172: 
  173: #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
  174: #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
  175: #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
  176: #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
  177: 
  178: #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
  179: #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT) 
  180: #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
  181: #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
  182: 
  183: #define CR0_PE_SHIFT 0
  184: #define CR0_MP_SHIFT 1
  185: 
  186: #define CR0_PE_MASK  (1 << 0)
  187: #define CR0_MP_MASK  (1 << 1)
  188: #define CR0_EM_MASK  (1 << 2)
  189: #define CR0_TS_MASK  (1 << 3)
  190: #define CR0_ET_MASK  (1 << 4)
  191: #define CR0_NE_MASK  (1 << 5)
  192: #define CR0_WP_MASK  (1 << 16)
  193: #define CR0_AM_MASK  (1 << 18)
  194: #define CR0_PG_MASK  (1 << 31)
  195: 
  196: #define CR4_VME_MASK  (1 << 0)
  197: #define CR4_PVI_MASK  (1 << 1)
  198: #define CR4_TSD_MASK  (1 << 2)
  199: #define CR4_DE_MASK   (1 << 3)
  200: #define CR4_PSE_MASK  (1 << 4)
  201: #define CR4_PAE_MASK  (1 << 5)
  202: #define CR4_PGE_MASK  (1 << 7)
  203: #define CR4_PCE_MASK  (1 << 8)
  204: #define CR4_OSFXSR_SHIFT 9
  205: #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
  206: #define CR4_OSXMMEXCPT_MASK  (1 << 10)
  207: 
  208: #define DR6_BD          (1 << 13)
  209: #define DR6_BS          (1 << 14)
  210: #define DR6_BT          (1 << 15)
  211: #define DR6_FIXED_1     0xffff0ff0
  212: 
  213: #define DR7_GD          (1 << 13)
  214: #define DR7_TYPE_SHIFT  16
  215: #define DR7_LEN_SHIFT   18
  216: #define DR7_FIXED_1     0x00000400
  217: 
  218: #define PG_PRESENT_BIT	0
  219: #define PG_RW_BIT	1
  220: #define PG_USER_BIT	2
  221: #define PG_PWT_BIT	3
  222: #define PG_PCD_BIT	4
  223: #define PG_ACCESSED_BIT	5
  224: #define PG_DIRTY_BIT	6
  225: #define PG_PSE_BIT	7
  226: #define PG_GLOBAL_BIT	8
  227: #define PG_NX_BIT	63
  228: 
  229: #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
  230: #define PG_RW_MASK	 (1 << PG_RW_BIT)
  231: #define PG_USER_MASK	 (1 << PG_USER_BIT)
  232: #define PG_PWT_MASK	 (1 << PG_PWT_BIT)
  233: #define PG_PCD_MASK	 (1 << PG_PCD_BIT)
  234: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
  235: #define PG_DIRTY_MASK	 (1 << PG_DIRTY_BIT)
  236: #define PG_PSE_MASK	 (1 << PG_PSE_BIT)
  237: #define PG_GLOBAL_MASK	 (1 << PG_GLOBAL_BIT)
  238: #define PG_NX_MASK	 (1LL << PG_NX_BIT)
  239: 
  240: #define PG_ERROR_W_BIT     1
  241: 
  242: #define PG_ERROR_P_MASK    0x01
  243: #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
  244: #define PG_ERROR_U_MASK    0x04
  245: #define PG_ERROR_RSVD_MASK 0x08
  246: #define PG_ERROR_I_D_MASK  0x10
  247: 
  248: #define MSR_IA32_TSC                    0x10
  249: #define MSR_IA32_APICBASE               0x1b
  250: #define MSR_IA32_APICBASE_BSP           (1<<8)
  251: #define MSR_IA32_APICBASE_ENABLE        (1<<11)
  252: #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
  253: 
  254: #define MSR_MTRRcap			0xfe
  255: #define MSR_MTRRcap_VCNT		8
  256: #define MSR_MTRRcap_FIXRANGE_SUPPORT	(1 << 8)
  257: #define MSR_MTRRcap_WC_SUPPORTED	(1 << 10)
  258: 
  259: #define MSR_IA32_SYSENTER_CS            0x174
  260: #define MSR_IA32_SYSENTER_ESP           0x175
  261: #define MSR_IA32_SYSENTER_EIP           0x176
  262: 
  263: #define MSR_MCG_CAP                     0x179
  264: #define MSR_MCG_STATUS                  0x17a
  265: #define MSR_MCG_CTL                     0x17b
  266: 
  267: #define MSR_IA32_PERF_STATUS            0x198
  268: 
  269: #define MSR_MTRRphysBase(reg)		(0x200 + 2 * (reg))
  270: #define MSR_MTRRphysMask(reg)		(0x200 + 2 * (reg) + 1)
  271: 
  272: #define MSR_MTRRfix64K_00000		0x250
  273: #define MSR_MTRRfix16K_80000		0x258
  274: #define MSR_MTRRfix16K_A0000		0x259
  275: #define MSR_MTRRfix4K_C0000		0x268
  276: #define MSR_MTRRfix4K_C8000		0x269
  277: #define MSR_MTRRfix4K_D0000		0x26a
  278: #define MSR_MTRRfix4K_D8000		0x26b
  279: #define MSR_MTRRfix4K_E0000		0x26c
  280: #define MSR_MTRRfix4K_E8000		0x26d
  281: #define MSR_MTRRfix4K_F0000		0x26e
  282: #define MSR_MTRRfix4K_F8000		0x26f
  283: 
  284: #define MSR_PAT                         0x277
  285: 
  286: #define MSR_MTRRdefType			0x2ff
  287: 
  288: #define MSR_EFER                        0xc0000080
  289: 
  290: #define MSR_EFER_SCE   (1 << 0)
  291: #define MSR_EFER_LME   (1 << 8)
  292: #define MSR_EFER_LMA   (1 << 10)
  293: #define MSR_EFER_NXE   (1 << 11)
  294: #define MSR_EFER_SVME  (1 << 12)
  295: #define MSR_EFER_FFXSR (1 << 14)
  296: 
  297: #define MSR_STAR                        0xc0000081
  298: #define MSR_LSTAR                       0xc0000082
  299: #define MSR_CSTAR                       0xc0000083
  300: #define MSR_FMASK                       0xc0000084
  301: #define MSR_FSBASE                      0xc0000100
  302: #define MSR_GSBASE                      0xc0000101
  303: #define MSR_KERNELGSBASE                0xc0000102
  304: 
  305: #define MSR_VM_HSAVE_PA                 0xc0010117
  306: 
  307: /* cpuid_features bits */
  308: #define CPUID_FP87 (1 << 0)
  309: #define CPUID_VME  (1 << 1)
  310: #define CPUID_DE   (1 << 2)
  311: #define CPUID_PSE  (1 << 3)
  312: #define CPUID_TSC  (1 << 4)
  313: #define CPUID_MSR  (1 << 5)
  314: #define CPUID_PAE  (1 << 6)
  315: #define CPUID_MCE  (1 << 7)
  316: #define CPUID_CX8  (1 << 8)
  317: #define CPUID_APIC (1 << 9)
  318: #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
  319: #define CPUID_MTRR (1 << 12)
  320: #define CPUID_PGE  (1 << 13)
  321: #define CPUID_MCA  (1 << 14)
  322: #define CPUID_CMOV (1 << 15)
  323: #define CPUID_PAT  (1 << 16)
  324: #define CPUID_PSE36   (1 << 17)
  325: #define CPUID_PN   (1 << 18)
  326: #define CPUID_CLFLUSH (1 << 19)
  327: #define CPUID_DTS (1 << 21)
  328: #define CPUID_ACPI (1 << 22)
  329: #define CPUID_MMX  (1 << 23)
  330: #define CPUID_FXSR (1 << 24)
  331: #define CPUID_SSE  (1 << 25)
  332: #define CPUID_SSE2 (1 << 26)
  333: #define CPUID_SS (1 << 27)
  334: #define CPUID_HT (1 << 28)
  335: #define CPUID_TM (1 << 29)
  336: #define CPUID_IA64 (1 << 30)
  337: #define CPUID_PBE (1 << 31)
  338: 
  339: #define CPUID_EXT_SSE3     (1 << 0)
  340: #define CPUID_EXT_DTES64   (1 << 2)
  341: #define CPUID_EXT_MONITOR  (1 << 3)
  342: #define CPUID_EXT_DSCPL    (1 << 4)
  343: #define CPUID_EXT_VMX      (1 << 5)
  344: #define CPUID_EXT_SMX      (1 << 6)
  345: #define CPUID_EXT_EST      (1 << 7)
  346: #define CPUID_EXT_TM2      (1 << 8)
  347: #define CPUID_EXT_SSSE3    (1 << 9)
  348: #define CPUID_EXT_CID      (1 << 10)
  349: #define CPUID_EXT_CX16     (1 << 13)
  350: #define CPUID_EXT_XTPR     (1 << 14)
  351: #define CPUID_EXT_PDCM     (1 << 15)
  352: #define CPUID_EXT_DCA      (1 << 18)
  353: #define CPUID_EXT_SSE41    (1 << 19)
  354: #define CPUID_EXT_SSE42    (1 << 20)
  355: #define CPUID_EXT_X2APIC   (1 << 21)
  356: #define CPUID_EXT_MOVBE    (1 << 22)
  357: #define CPUID_EXT_POPCNT   (1 << 23)
  358: #define CPUID_EXT_XSAVE    (1 << 26)
  359: #define CPUID_EXT_OSXSAVE  (1 << 27)
  360: 
  361: #define CPUID_EXT2_SYSCALL (1 << 11)
  362: #define CPUID_EXT2_MP      (1 << 19)
  363: #define CPUID_EXT2_NX      (1 << 20)
  364: #define CPUID_EXT2_MMXEXT  (1 << 22)
  365: #define CPUID_EXT2_FFXSR   (1 << 25)
  366: #define CPUID_EXT2_PDPE1GB (1 << 26)
  367: #define CPUID_EXT2_RDTSCP  (1 << 27)
  368: #define CPUID_EXT2_LM      (1 << 29)
  369: #define CPUID_EXT2_3DNOWEXT (1 << 30)
  370: #define CPUID_EXT2_3DNOW   (1 << 31)
  371: 
  372: #define CPUID_EXT3_LAHF_LM (1 << 0)
  373: #define CPUID_EXT3_CMP_LEG (1 << 1)
  374: #define CPUID_EXT3_SVM     (1 << 2)
  375: #define CPUID_EXT3_EXTAPIC (1 << 3)
  376: #define CPUID_EXT3_CR8LEG  (1 << 4)
  377: #define CPUID_EXT3_ABM     (1 << 5)
  378: #define CPUID_EXT3_SSE4A   (1 << 6)
  379: #define CPUID_EXT3_MISALIGNSSE (1 << 7)
  380: #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
  381: #define CPUID_EXT3_OSVW    (1 << 9)
  382: #define CPUID_EXT3_IBS     (1 << 10)
  383: #define CPUID_EXT3_SKINIT  (1 << 12)
  384: 
  385: #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
  386: #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
  387: #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
  388: 
  389: #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
  390: #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */ 
  391: #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
  392: 
  393: #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
  394: #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
  395: 
  396: #define EXCP00_DIVZ	0
  397: #define EXCP01_DB	1
  398: #define EXCP02_NMI	2
  399: #define EXCP03_INT3	3
  400: #define EXCP04_INTO	4
  401: #define EXCP05_BOUND	5
  402: #define EXCP06_ILLOP	6
  403: #define EXCP07_PREX	7
  404: #define EXCP08_DBLE	8
  405: #define EXCP09_XERR	9
  406: #define EXCP0A_TSS	10
  407: #define EXCP0B_NOSEG	11
  408: #define EXCP0C_STACK	12
  409: #define EXCP0D_GPF	13
  410: #define EXCP0E_PAGE	14
  411: #define EXCP10_COPR	16
  412: #define EXCP11_ALGN	17
  413: #define EXCP12_MCHK	18
  414: 
  415: #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
  416:                                  for syscall instruction */
  417: 
  418: enum {
  419:     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
  420:     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
  421: 
  422:     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
  423:     CC_OP_MULW,
  424:     CC_OP_MULL,
  425:     CC_OP_MULQ,
  426: 
  427:     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
  428:     CC_OP_ADDW,
  429:     CC_OP_ADDL,
  430:     CC_OP_ADDQ,
  431: 
  432:     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
  433:     CC_OP_ADCW,
  434:     CC_OP_ADCL,
  435:     CC_OP_ADCQ,
  436: 
  437:     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
  438:     CC_OP_SUBW,
  439:     CC_OP_SUBL,
  440:     CC_OP_SUBQ,
  441: 
  442:     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
  443:     CC_OP_SBBW,
  444:     CC_OP_SBBL,
  445:     CC_OP_SBBQ,
  446: 
  447:     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
  448:     CC_OP_LOGICW,
  449:     CC_OP_LOGICL,
  450:     CC_OP_LOGICQ,
  451: 
  452:     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
  453:     CC_OP_INCW,
  454:     CC_OP_INCL,
  455:     CC_OP_INCQ,
  456: 
  457:     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
  458:     CC_OP_DECW,
  459:     CC_OP_DECL,
  460:     CC_OP_DECQ,
  461: 
  462:     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
  463:     CC_OP_SHLW,
  464:     CC_OP_SHLL,
  465:     CC_OP_SHLQ,
  466: 
  467:     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
  468:     CC_OP_SARW,
  469:     CC_OP_SARL,
  470:     CC_OP_SARQ,
  471: 
  472:     CC_OP_NB,
  473: };
  474: 
  475: #ifdef FLOATX80
  476: #define USE_X86LDOUBLE
  477: #endif
  478: 
  479: #ifdef USE_X86LDOUBLE
  480: typedef floatx80 CPU86_LDouble;
  481: #else
  482: typedef float64 CPU86_LDouble;
  483: #endif
  484: 
  485: typedef struct SegmentCache {
  486:     uint32_t selector;
  487:     target_ulong base;
  488:     uint32_t limit;
  489:     uint32_t flags;
  490: } SegmentCache;
  491: 
  492: typedef union {
  493:     uint8_t _b[16];
  494:     uint16_t _w[8];
  495:     uint32_t _l[4];
  496:     uint64_t _q[2];
  497:     float32 _s[4];
  498:     float64 _d[2];
  499: } XMMReg;
  500: 
  501: typedef union {
  502:     uint8_t _b[8];
  503:     uint16_t _w[4];
  504:     uint32_t _l[2];
  505:     float32 _s[2];
  506:     uint64_t q;
  507: } MMXReg;
  508: 
  509: #ifdef WORDS_BIGENDIAN
  510: #define XMM_B(n) _b[15 - (n)]
  511: #define XMM_W(n) _w[7 - (n)]
  512: #define XMM_L(n) _l[3 - (n)]
  513: #define XMM_S(n) _s[3 - (n)]
  514: #define XMM_Q(n) _q[1 - (n)]
  515: #define XMM_D(n) _d[1 - (n)]
  516: 
  517: #define MMX_B(n) _b[7 - (n)]
  518: #define MMX_W(n) _w[3 - (n)]
  519: #define MMX_L(n) _l[1 - (n)]
  520: #define MMX_S(n) _s[1 - (n)]
  521: #else
  522: #define XMM_B(n) _b[n]
  523: #define XMM_W(n) _w[n]
  524: #define XMM_L(n) _l[n]
  525: #define XMM_S(n) _s[n]
  526: #define XMM_Q(n) _q[n]
  527: #define XMM_D(n) _d[n]
  528: 
  529: #define MMX_B(n) _b[n]
  530: #define MMX_W(n) _w[n]
  531: #define MMX_L(n) _l[n]
  532: #define MMX_S(n) _s[n]
  533: #endif
  534: #define MMX_Q(n) q
  535: 
  536: #ifdef TARGET_X86_64
  537: #define CPU_NB_REGS 16
  538: #else
  539: #define CPU_NB_REGS 8
  540: #endif
  541: 
  542: #define NB_MMU_MODES 2
  543: 
  544: typedef struct CPUX86State {
  545:     /* standard registers */
  546:     target_ulong regs[CPU_NB_REGS];
  547:     target_ulong eip;
  548:     target_ulong eflags; /* eflags register. During CPU emulation, CC
  549:                         flags and DF are set to zero because they are
  550:                         stored elsewhere */
  551: 
  552:     /* emulator internal eflags handling */
  553:     target_ulong cc_src;
  554:     target_ulong cc_dst;
  555:     uint32_t cc_op;
  556:     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
  557:     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
  558:                         are known at translation time. */
  559:     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
  560: 
  561:     /* segments */
  562:     SegmentCache segs[6]; /* selector values */
  563:     SegmentCache ldt;
  564:     SegmentCache tr;
  565:     SegmentCache gdt; /* only base and limit are used */
  566:     SegmentCache idt; /* only base and limit are used */
  567: 
  568:     target_ulong cr[5]; /* NOTE: cr1 is unused */
  569:     uint64_t a20_mask;
  570: 
  571:     /* FPU state */
  572:     unsigned int fpstt; /* top of stack index */
  573:     unsigned int fpus;
  574:     unsigned int fpuc;
  575:     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
  576:     union {
  577: #ifdef USE_X86LDOUBLE
  578:         CPU86_LDouble d __attribute__((aligned(16)));
  579: #else
  580:         CPU86_LDouble d;
  581: #endif
  582:         MMXReg mmx;
  583:     } fpregs[8];
  584: 
  585:     /* emulator internal variables */
  586:     float_status fp_status;
  587:     CPU86_LDouble ft0;
  588: 
  589:     float_status mmx_status; /* for 3DNow! float ops */
  590:     float_status sse_status;
  591:     uint32_t mxcsr;
  592:     XMMReg xmm_regs[CPU_NB_REGS];
  593:     XMMReg xmm_t0;
  594:     MMXReg mmx_t0;
  595:     target_ulong cc_tmp; /* temporary for rcr/rcl */
  596: 
  597:     /* sysenter registers */
  598:     uint32_t sysenter_cs;
  599:     target_ulong sysenter_esp;
  600:     target_ulong sysenter_eip;
  601:     uint64_t efer;
  602:     uint64_t star;
  603: 
  604:     uint64_t vm_hsave;
  605:     uint64_t vm_vmcb;
  606:     uint64_t tsc_offset;
  607:     uint64_t intercept;
  608:     uint16_t intercept_cr_read;
  609:     uint16_t intercept_cr_write;
  610:     uint16_t intercept_dr_read;
  611:     uint16_t intercept_dr_write;
  612:     uint32_t intercept_exceptions;
  613:     uint8_t v_tpr;
  614: 
  615: #ifdef TARGET_X86_64
  616:     target_ulong lstar;
  617:     target_ulong cstar;
  618:     target_ulong fmask;
  619:     target_ulong kernelgsbase;
  620: #endif
  621: 
  622:     uint64_t tsc;
  623: 
  624:     uint64_t pat;
  625: 
  626:     /* exception/interrupt handling */
  627:     int error_code;
  628:     int exception_is_int;
  629:     target_ulong exception_next_eip;
  630:     target_ulong dr[8]; /* debug registers */
  631:     union {
  632:         CPUBreakpoint *cpu_breakpoint[4];
  633:         CPUWatchpoint *cpu_watchpoint[4];
  634:     }; /* break/watchpoints for dr[0..3] */
  635:     uint32_t smbase;
  636:     int old_exception;  /* exception in flight */
  637: 
  638:     CPU_COMMON
  639: 
  640:     /* processor features (e.g. for CPUID insn) */
  641:     uint32_t cpuid_level;
  642:     uint32_t cpuid_vendor1;
  643:     uint32_t cpuid_vendor2;
  644:     uint32_t cpuid_vendor3;
  645:     uint32_t cpuid_version;
  646:     uint32_t cpuid_features;
  647:     uint32_t cpuid_ext_features;
  648:     uint32_t cpuid_xlevel;
  649:     uint32_t cpuid_model[12];
  650:     uint32_t cpuid_ext2_features;
  651:     uint32_t cpuid_ext3_features;
  652:     uint32_t cpuid_apic_id;
  653: 
  654:     /* MTRRs */
  655:     uint64_t mtrr_fixed[11];
  656:     uint64_t mtrr_deftype;
  657:     struct {
  658:         uint64_t base;
  659:         uint64_t mask;
  660:     } mtrr_var[8];
  661: 
  662: #ifdef USE_KQEMU
  663:     int kqemu_enabled;
  664:     int last_io_time;
  665: #endif
  666: 
  667:     /* For KVM */
  668:     uint64_t interrupt_bitmap[256 / 64];
  669: 
  670:     /* in order to simplify APIC support, we leave this pointer to the
  671:        user */
  672:     struct APICState *apic_state;
  673: } CPUX86State;
  674: 
  675: CPUX86State *cpu_x86_init(const char *cpu_model);
  676: int cpu_x86_exec(CPUX86State *s);
  677: void cpu_x86_close(CPUX86State *s);
  678: void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
  679:                                                  ...));
  680: int cpu_get_pic_interrupt(CPUX86State *s);
  681: /* MSDOS compatibility mode FPU exception support */
  682: void cpu_set_ferr(CPUX86State *s);
  683: 
  684: /* this function must always be used to load data in the segment
  685:    cache: it synchronizes the hflags with the segment cache values */
  686: static inline void cpu_x86_load_seg_cache(CPUX86State *env,
  687:                                           int seg_reg, unsigned int selector,
  688:                                           target_ulong base,
  689:                                           unsigned int limit,
  690:                                           unsigned int flags)
  691: {
  692:     SegmentCache *sc;
  693:     unsigned int new_hflags;
  694: 
  695:     sc = &env->segs[seg_reg];
  696:     sc->selector = selector;
  697:     sc->base = base;
  698:     sc->limit = limit;
  699:     sc->flags = flags;
  700: 
  701:     /* update the hidden flags */
  702:     {
  703:         if (seg_reg == R_CS) {
  704: #ifdef TARGET_X86_64
  705:             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
  706:                 /* long mode */
  707:                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
  708:                 env->hflags &= ~(HF_ADDSEG_MASK);
  709:             } else
  710: #endif
  711:             {
  712:                 /* legacy / compatibility case */
  713:                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
  714:                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
  715:                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
  716:                     new_hflags;
  717:             }
  718:         }
  719:         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
  720:             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
  721:         if (env->hflags & HF_CS64_MASK) {
  722:             /* zero base assumed for DS, ES and SS in long mode */
  723:         } else if (!(env->cr[0] & CR0_PE_MASK) ||
  724:                    (env->eflags & VM_MASK) ||
  725:                    !(env->hflags & HF_CS32_MASK)) {
  726:             /* XXX: try to avoid this test. The problem comes from the
  727:                fact that is real mode or vm86 mode we only modify the
  728:                'base' and 'selector' fields of the segment cache to go
  729:                faster. A solution may be to force addseg to one in
  730:                translate-i386.c. */
  731:             new_hflags |= HF_ADDSEG_MASK;
  732:         } else {
  733:             new_hflags |= ((env->segs[R_DS].base |
  734:                             env->segs[R_ES].base |
  735:                             env->segs[R_SS].base) != 0) <<
  736:                 HF_ADDSEG_SHIFT;
  737:         }
  738:         env->hflags = (env->hflags &
  739:                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
  740:     }
  741: }
  742: 
  743: /* wrapper, just in case memory mappings must be changed */
  744: static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
  745: {
  746: #if HF_CPL_MASK == 3
  747:     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
  748: #else
  749: #error HF_CPL_MASK is hardcoded
  750: #endif
  751: }
  752: 
  753: /* op_helper.c */
  754: /* used for debug or cpu save/restore */
  755: void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
  756: CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
  757: 
  758: /* cpu-exec.c */
  759: /* the following helpers are only usable in user mode simulation as
  760:    they can trigger unexpected exceptions */
  761: void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
  762: void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
  763: void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
  764: 
  765: /* you can call this signal handler from your SIGBUS and SIGSEGV
  766:    signal handlers to inform the virtual CPU of exceptions. non zero
  767:    is returned if the signal was handled by the virtual CPU.  */
  768: int cpu_x86_signal_handler(int host_signum, void *pinfo,
  769:                            void *puc);
  770: 
  771: /* helper.c */
  772: int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
  773:                              int is_write, int mmu_idx, int is_softmmu);
  774: void cpu_x86_set_a20(CPUX86State *env, int a20_state);
  775: void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
  776:                    uint32_t *eax, uint32_t *ebx,
  777:                    uint32_t *ecx, uint32_t *edx);
  778: 
  779: static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
  780: {
  781:     return (dr7 >> (index * 2)) & 3;
  782: }
  783: 
  784: static inline int hw_breakpoint_type(unsigned long dr7, int index)
  785: {
  786:     return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3;
  787: }
  788: 
  789: static inline int hw_breakpoint_len(unsigned long dr7, int index)
  790: {
  791:     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3);
  792:     return (len == 2) ? 8 : len + 1;
  793: }
  794: 
  795: void hw_breakpoint_insert(CPUX86State *env, int index);
  796: void hw_breakpoint_remove(CPUX86State *env, int index);
  797: int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
  798: 
  799: /* will be suppressed */
  800: void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
  801: void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
  802: void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
  803: 
  804: /* hw/apic.c */
  805: void cpu_set_apic_base(CPUX86State *env, uint64_t val);
  806: uint64_t cpu_get_apic_base(CPUX86State *env);
  807: void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
  808: #ifndef NO_CPU_IO_DEFS
  809: uint8_t cpu_get_apic_tpr(CPUX86State *env);
  810: #endif
  811: 
  812: /* hw/pc.c */
  813: void cpu_smm_update(CPUX86State *env);
  814: uint64_t cpu_get_tsc(CPUX86State *env);
  815: 
  816: /* used to debug */
  817: #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
  818: #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
  819: 
  820: #ifdef USE_KQEMU
  821: static inline int cpu_get_time_fast(void)
  822: {
  823:     int low, high;
  824:     asm volatile("rdtsc" : "=a" (low), "=d" (high));
  825:     return low;
  826: }
  827: #endif
  828: 
  829: #define TARGET_PAGE_BITS 12
  830: 
  831: #define CPUState CPUX86State
  832: #define cpu_init cpu_x86_init
  833: #define cpu_exec cpu_x86_exec
  834: #define cpu_gen_code cpu_x86_gen_code
  835: #define cpu_signal_handler cpu_x86_signal_handler
  836: #define cpu_list x86_cpu_list
  837: 
  838: #define CPU_SAVE_VERSION 8
  839: 
  840: /* MMU modes definitions */
  841: #define MMU_MODE0_SUFFIX _kernel
  842: #define MMU_MODE1_SUFFIX _user
  843: #define MMU_USER_IDX 1
  844: static inline int cpu_mmu_index (CPUState *env)
  845: {
  846:     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
  847: }
  848: 
  849: /* translate.c */
  850: void optimize_flags_init(void);
  851: 
  852: typedef struct CCTable {
  853:     int (*compute_all)(void); /* return all the flags */
  854:     int (*compute_c)(void);  /* return the C flag */
  855: } CCTable;
  856: 
  857: #if defined(CONFIG_USER_ONLY)
  858: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
  859: {
  860:     if (newsp)
  861:         env->regs[R_ESP] = newsp;
  862:     env->regs[R_EAX] = 0;
  863: }
  864: #endif
  865: 
  866: #include "cpu-all.h"
  867: #include "exec-all.h"
  868: 
  869: #include "svm.h"
  870: 
  871: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
  872: {
  873:     env->eip = tb->pc - tb->cs_base;
  874: }
  875: 
  876: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
  877:                                         target_ulong *cs_base, int *flags)
  878: {
  879:     *cs_base = env->segs[R_CS].base;
  880:     *pc = *cs_base + env->eip;
  881:     *flags = env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
  882: }
  883: 
  884: #endif /* CPU_I386_H */

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