![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to translate.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / target-i386|
Return to translate.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / target-i386 |
1.1 root 1: /*
2: * i386 translation
1.1.1.6 root 3: *
1.1 root 4: * Copyright (c) 2003 Fabrice Bellard
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.8 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #include <stdarg.h>
20: #include <stdlib.h>
21: #include <stdio.h>
22: #include <string.h>
23: #include <inttypes.h>
24: #include <signal.h>
25:
26: #include "cpu.h"
27: #include "exec-all.h"
28: #include "disas.h"
1.1.1.7 root 29: #include "tcg-op.h"
1.1 root 30:
1.1.1.7 root 31: #include "helper.h"
32: #define GEN_HELPER 1
33: #include "helper.h"
1.1 root 34:
35: #define PREFIX_REPZ 0x01
36: #define PREFIX_REPNZ 0x02
37: #define PREFIX_LOCK 0x04
38: #define PREFIX_DATA 0x08
39: #define PREFIX_ADR 0x10
40:
41: #ifdef TARGET_X86_64
42: #define X86_64_ONLY(x) x
1.1.1.8 root 43: #define X86_64_DEF(...) __VA_ARGS__
1.1 root 44: #define CODE64(s) ((s)->code64)
45: #define REX_X(s) ((s)->rex_x)
46: #define REX_B(s) ((s)->rex_b)
47: /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
48: #if 1
49: #define BUGGY_64(x) NULL
50: #endif
51: #else
52: #define X86_64_ONLY(x) NULL
1.1.1.8 root 53: #define X86_64_DEF(...)
1.1 root 54: #define CODE64(s) 0
55: #define REX_X(s) 0
56: #define REX_B(s) 0
57: #endif
58:
1.1.1.7 root 59: //#define MACRO_TEST 1
60:
61: /* global register indexes */
62: static TCGv_ptr cpu_env;
63: static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
64: static TCGv_i32 cpu_cc_op;
1.1.1.9 root 65: static TCGv cpu_regs[CPU_NB_REGS];
1.1.1.7 root 66: /* local temps */
67: static TCGv cpu_T[2], cpu_T3;
68: /* local register indexes (only used inside old micro ops) */
69: static TCGv cpu_tmp0, cpu_tmp4;
70: static TCGv_ptr cpu_ptr0, cpu_ptr1;
71: static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
72: static TCGv_i64 cpu_tmp1_i64;
1.1.1.9 root 73: static TCGv cpu_tmp5;
1.1.1.7 root 74:
75: #include "gen-icount.h"
76:
1.1 root 77: #ifdef TARGET_X86_64
78: static int x86_64_hregs;
79: #endif
80:
81: typedef struct DisasContext {
82: /* current insn context */
83: int override; /* -1 if no override */
84: int prefix;
85: int aflag, dflag;
86: target_ulong pc; /* pc = eip + cs_base */
87: int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
88: static state change (stop translation) */
89: /* current block context */
90: target_ulong cs_base; /* base of CS segment */
91: int pe; /* protected mode */
92: int code32; /* 32 bit code segment */
93: #ifdef TARGET_X86_64
94: int lma; /* long mode active */
95: int code64; /* 64 bit code segment */
96: int rex_x, rex_b;
97: #endif
98: int ss32; /* 32 bit stack segment */
99: int cc_op; /* current CC operation */
100: int addseg; /* non zero if either DS/ES/SS have a non zero base */
101: int f_st; /* currently unused */
102: int vm86; /* vm86 mode */
103: int cpl;
104: int iopl;
105: int tf; /* TF cpu flag */
106: int singlestep_enabled; /* "hardware" single step enabled */
107: int jmp_opt; /* use direct block chaining for direct jumps */
108: int mem_index; /* select memory access functions */
1.1.1.6 root 109: uint64_t flags; /* all execution flags */
1.1 root 110: struct TranslationBlock *tb;
111: int popl_esp_hack; /* for correct popl with esp base handling */
112: int rip_offset; /* only used in x86_64, but left for simplicity */
113: int cpuid_features;
1.1.1.4 root 114: int cpuid_ext_features;
1.1.1.7 root 115: int cpuid_ext2_features;
116: int cpuid_ext3_features;
1.1 root 117: } DisasContext;
118:
119: static void gen_eob(DisasContext *s);
120: static void gen_jmp(DisasContext *s, target_ulong eip);
121: static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
122:
123: /* i386 arith/logic operations */
124: enum {
1.1.1.6 root 125: OP_ADDL,
126: OP_ORL,
127: OP_ADCL,
1.1 root 128: OP_SBBL,
1.1.1.6 root 129: OP_ANDL,
130: OP_SUBL,
131: OP_XORL,
1.1 root 132: OP_CMPL,
133: };
134:
135: /* i386 shift ops */
136: enum {
1.1.1.6 root 137: OP_ROL,
138: OP_ROR,
139: OP_RCL,
140: OP_RCR,
141: OP_SHL,
142: OP_SHR,
1.1 root 143: OP_SHL1, /* undocumented */
144: OP_SAR = 7,
145: };
146:
147: enum {
1.1.1.7 root 148: JCC_O,
149: JCC_B,
150: JCC_Z,
151: JCC_BE,
152: JCC_S,
153: JCC_P,
154: JCC_L,
155: JCC_LE,
1.1 root 156: };
157:
158: /* operand size */
159: enum {
160: OT_BYTE = 0,
161: OT_WORD,
1.1.1.6 root 162: OT_LONG,
1.1 root 163: OT_QUAD,
164: };
165:
166: enum {
167: /* I386 int registers */
168: OR_EAX, /* MUST be even numbered */
169: OR_ECX,
170: OR_EDX,
171: OR_EBX,
172: OR_ESP,
173: OR_EBP,
174: OR_ESI,
175: OR_EDI,
176:
177: OR_TMP0 = 16, /* temporary operand register */
178: OR_TMP1,
179: OR_A0, /* temporary register used when doing address evaluation */
180: };
181:
1.1.1.7 root 182: static inline void gen_op_movl_T0_0(void)
183: {
184: tcg_gen_movi_tl(cpu_T[0], 0);
185: }
186:
187: static inline void gen_op_movl_T0_im(int32_t val)
188: {
189: tcg_gen_movi_tl(cpu_T[0], val);
190: }
191:
192: static inline void gen_op_movl_T0_imu(uint32_t val)
193: {
194: tcg_gen_movi_tl(cpu_T[0], val);
195: }
196:
197: static inline void gen_op_movl_T1_im(int32_t val)
198: {
199: tcg_gen_movi_tl(cpu_T[1], val);
200: }
201:
202: static inline void gen_op_movl_T1_imu(uint32_t val)
203: {
204: tcg_gen_movi_tl(cpu_T[1], val);
205: }
206:
207: static inline void gen_op_movl_A0_im(uint32_t val)
208: {
209: tcg_gen_movi_tl(cpu_A0, val);
210: }
211:
1.1 root 212: #ifdef TARGET_X86_64
1.1.1.7 root 213: static inline void gen_op_movq_A0_im(int64_t val)
214: {
215: tcg_gen_movi_tl(cpu_A0, val);
216: }
217: #endif
1.1 root 218:
1.1.1.7 root 219: static inline void gen_movtl_T0_im(target_ulong val)
220: {
221: tcg_gen_movi_tl(cpu_T[0], val);
222: }
223:
224: static inline void gen_movtl_T1_im(target_ulong val)
225: {
226: tcg_gen_movi_tl(cpu_T[1], val);
227: }
228:
229: static inline void gen_op_andl_T0_ffff(void)
230: {
231: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
232: }
233:
234: static inline void gen_op_andl_T0_im(uint32_t val)
235: {
236: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
237: }
1.1 root 238:
1.1.1.7 root 239: static inline void gen_op_movl_T0_T1(void)
240: {
241: tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
242: }
243:
244: static inline void gen_op_andl_A0_ffff(void)
245: {
246: tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
247: }
248:
249: #ifdef TARGET_X86_64
250:
251: #define NB_OP_SIZES 4
1.1 root 252:
253: #else /* !TARGET_X86_64 */
254:
255: #define NB_OP_SIZES 3
256:
257: #endif /* !TARGET_X86_64 */
258:
1.1.1.9 root 259: #if defined(HOST_WORDS_BIGENDIAN)
1.1.1.7 root 260: #define REG_B_OFFSET (sizeof(target_ulong) - 1)
261: #define REG_H_OFFSET (sizeof(target_ulong) - 2)
262: #define REG_W_OFFSET (sizeof(target_ulong) - 2)
263: #define REG_L_OFFSET (sizeof(target_ulong) - 4)
264: #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
1.1 root 265: #else
1.1.1.7 root 266: #define REG_B_OFFSET 0
267: #define REG_H_OFFSET 1
268: #define REG_W_OFFSET 0
269: #define REG_L_OFFSET 0
270: #define REG_LH_OFFSET 4
1.1 root 271: #endif
272:
1.1.1.7 root 273: static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
274: {
1.1.1.9 root 275: TCGv tmp;
276:
1.1.1.7 root 277: switch(ot) {
278: case OT_BYTE:
1.1.1.9 root 279: tmp = tcg_temp_new();
280: tcg_gen_ext8u_tl(tmp, t0);
1.1.1.7 root 281: if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
1.1.1.9 root 282: tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xff);
283: tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
1.1.1.7 root 284: } else {
1.1.1.9 root 285: tcg_gen_shli_tl(tmp, tmp, 8);
286: tcg_gen_andi_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], ~0xff00);
287: tcg_gen_or_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], tmp);
1.1.1.7 root 288: }
1.1.1.9 root 289: tcg_temp_free(tmp);
1.1.1.7 root 290: break;
291: case OT_WORD:
1.1.1.9 root 292: tmp = tcg_temp_new();
293: tcg_gen_ext16u_tl(tmp, t0);
294: tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
295: tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
296: tcg_temp_free(tmp);
1.1.1.7 root 297: break;
1.1.1.9 root 298: default: /* XXX this shouldn't be reached; abort? */
1.1.1.7 root 299: case OT_LONG:
1.1.1.9 root 300: /* For x86_64, this sets the higher half of register to zero.
301: For i386, this is equivalent to a mov. */
302: tcg_gen_ext32u_tl(cpu_regs[reg], t0);
1.1.1.7 root 303: break;
1.1.1.9 root 304: #ifdef TARGET_X86_64
1.1.1.7 root 305: case OT_QUAD:
1.1.1.9 root 306: tcg_gen_mov_tl(cpu_regs[reg], t0);
1.1.1.7 root 307: break;
1.1 root 308: #endif
1.1.1.7 root 309: }
310: }
1.1 root 311:
1.1.1.7 root 312: static inline void gen_op_mov_reg_T0(int ot, int reg)
313: {
314: gen_op_mov_reg_v(ot, reg, cpu_T[0]);
315: }
1.1 root 316:
1.1.1.7 root 317: static inline void gen_op_mov_reg_T1(int ot, int reg)
1.1 root 318: {
1.1.1.7 root 319: gen_op_mov_reg_v(ot, reg, cpu_T[1]);
320: }
321:
322: static inline void gen_op_mov_reg_A0(int size, int reg)
323: {
1.1.1.9 root 324: TCGv tmp;
325:
1.1.1.7 root 326: switch(size) {
327: case 0:
1.1.1.9 root 328: tmp = tcg_temp_new();
329: tcg_gen_ext16u_tl(tmp, cpu_A0);
330: tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
331: tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
332: tcg_temp_free(tmp);
1.1.1.7 root 333: break;
1.1.1.9 root 334: default: /* XXX this shouldn't be reached; abort? */
1.1.1.7 root 335: case 1:
1.1.1.9 root 336: /* For x86_64, this sets the higher half of register to zero.
337: For i386, this is equivalent to a mov. */
338: tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
1.1.1.7 root 339: break;
1.1.1.9 root 340: #ifdef TARGET_X86_64
1.1.1.7 root 341: case 2:
1.1.1.9 root 342: tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
1.1.1.7 root 343: break;
1.1 root 344: #endif
1.1.1.7 root 345: }
346: }
1.1 root 347:
1.1.1.7 root 348: static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
349: {
350: switch(ot) {
351: case OT_BYTE:
352: if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
353: goto std_case;
354: } else {
1.1.1.9 root 355: tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
356: tcg_gen_ext8u_tl(t0, t0);
1.1.1.7 root 357: }
358: break;
359: default:
360: std_case:
1.1.1.9 root 361: tcg_gen_mov_tl(t0, cpu_regs[reg]);
1.1.1.7 root 362: break;
363: }
364: }
1.1 root 365:
1.1.1.7 root 366: static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
367: {
368: gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
369: }
1.1 root 370:
1.1.1.7 root 371: static inline void gen_op_movl_A0_reg(int reg)
372: {
1.1.1.9 root 373: tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
1.1.1.7 root 374: }
1.1 root 375:
1.1.1.7 root 376: static inline void gen_op_addl_A0_im(int32_t val)
377: {
378: tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
379: #ifdef TARGET_X86_64
380: tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
1.1 root 381: #endif
1.1.1.7 root 382: }
1.1 root 383:
1.1.1.7 root 384: #ifdef TARGET_X86_64
385: static inline void gen_op_addq_A0_im(int64_t val)
386: {
387: tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
388: }
1.1 root 389: #endif
1.1.1.7 root 390:
391: static void gen_add_A0_im(DisasContext *s, int val)
392: {
393: #ifdef TARGET_X86_64
394: if (CODE64(s))
395: gen_op_addq_A0_im(val);
396: else
1.1 root 397: #endif
1.1.1.7 root 398: gen_op_addl_A0_im(val);
399: }
1.1 root 400:
1.1.1.7 root 401: static inline void gen_op_addl_T0_T1(void)
402: {
403: tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
404: }
1.1 root 405:
1.1.1.7 root 406: static inline void gen_op_jmp_T0(void)
407: {
408: tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
409: }
1.1 root 410:
1.1.1.7 root 411: static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
412: {
413: switch(size) {
414: case 0:
1.1.1.9 root 415: tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
416: tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
417: tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
418: tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
1.1.1.7 root 419: break;
420: case 1:
1.1.1.9 root 421: tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
422: /* For x86_64, this sets the higher half of register to zero.
423: For i386, this is equivalent to a nop. */
424: tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
425: tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
1.1.1.7 root 426: break;
427: #ifdef TARGET_X86_64
428: case 2:
1.1.1.9 root 429: tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
1.1.1.7 root 430: break;
431: #endif
432: }
433: }
1.1 root 434:
1.1.1.7 root 435: static inline void gen_op_add_reg_T0(int size, int reg)
436: {
437: switch(size) {
438: case 0:
1.1.1.9 root 439: tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
440: tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
441: tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
442: tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
1.1.1.7 root 443: break;
444: case 1:
1.1.1.9 root 445: tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
446: /* For x86_64, this sets the higher half of register to zero.
447: For i386, this is equivalent to a nop. */
448: tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
449: tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
1.1.1.7 root 450: break;
451: #ifdef TARGET_X86_64
452: case 2:
1.1.1.9 root 453: tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
1.1.1.7 root 454: break;
455: #endif
456: }
457: }
1.1 root 458:
1.1.1.7 root 459: static inline void gen_op_set_cc_op(int32_t val)
460: {
461: tcg_gen_movi_i32(cpu_cc_op, val);
462: }
1.1 root 463:
1.1.1.7 root 464: static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
465: {
1.1.1.9 root 466: tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
467: if (shift != 0)
1.1.1.7 root 468: tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
469: tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
1.1.1.9 root 470: /* For x86_64, this sets the higher half of register to zero.
471: For i386, this is equivalent to a nop. */
472: tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
1.1.1.7 root 473: }
1.1 root 474:
1.1.1.7 root 475: static inline void gen_op_movl_A0_seg(int reg)
476: {
477: tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
478: }
1.1 root 479:
1.1.1.7 root 480: static inline void gen_op_addl_A0_seg(int reg)
481: {
482: tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
483: tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
484: #ifdef TARGET_X86_64
485: tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
486: #endif
487: }
1.1 root 488:
1.1.1.7 root 489: #ifdef TARGET_X86_64
490: static inline void gen_op_movq_A0_seg(int reg)
491: {
492: tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
493: }
1.1 root 494:
1.1.1.7 root 495: static inline void gen_op_addq_A0_seg(int reg)
496: {
497: tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
498: tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
499: }
1.1 root 500:
1.1.1.7 root 501: static inline void gen_op_movq_A0_reg(int reg)
502: {
1.1.1.9 root 503: tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
1.1.1.7 root 504: }
1.1 root 505:
1.1.1.7 root 506: static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
507: {
1.1.1.9 root 508: tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
509: if (shift != 0)
1.1.1.7 root 510: tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
511: tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
512: }
1.1 root 513: #endif
514:
1.1.1.7 root 515: static inline void gen_op_lds_T0_A0(int idx)
516: {
517: int mem_index = (idx >> 2) - 1;
518: switch(idx & 3) {
519: case 0:
520: tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
521: break;
522: case 1:
523: tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
524: break;
525: default:
526: case 2:
527: tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
528: break;
529: }
530: }
1.1 root 531:
1.1.1.7 root 532: static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
533: {
534: int mem_index = (idx >> 2) - 1;
535: switch(idx & 3) {
536: case 0:
537: tcg_gen_qemu_ld8u(t0, a0, mem_index);
538: break;
539: case 1:
540: tcg_gen_qemu_ld16u(t0, a0, mem_index);
541: break;
542: case 2:
543: tcg_gen_qemu_ld32u(t0, a0, mem_index);
544: break;
545: default:
546: case 3:
547: /* Should never happen on 32-bit targets. */
548: #ifdef TARGET_X86_64
549: tcg_gen_qemu_ld64(t0, a0, mem_index);
1.1 root 550: #endif
1.1.1.7 root 551: break;
552: }
553: }
1.1 root 554:
1.1.1.7 root 555: /* XXX: always use ldu or lds */
556: static inline void gen_op_ld_T0_A0(int idx)
557: {
558: gen_op_ld_v(idx, cpu_T[0], cpu_A0);
559: }
1.1 root 560:
1.1.1.7 root 561: static inline void gen_op_ldu_T0_A0(int idx)
562: {
563: gen_op_ld_v(idx, cpu_T[0], cpu_A0);
564: }
1.1 root 565:
1.1.1.7 root 566: static inline void gen_op_ld_T1_A0(int idx)
567: {
568: gen_op_ld_v(idx, cpu_T[1], cpu_A0);
569: }
1.1 root 570:
1.1.1.7 root 571: static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
572: {
573: int mem_index = (idx >> 2) - 1;
574: switch(idx & 3) {
575: case 0:
576: tcg_gen_qemu_st8(t0, a0, mem_index);
577: break;
578: case 1:
579: tcg_gen_qemu_st16(t0, a0, mem_index);
580: break;
581: case 2:
582: tcg_gen_qemu_st32(t0, a0, mem_index);
583: break;
584: default:
585: case 3:
586: /* Should never happen on 32-bit targets. */
587: #ifdef TARGET_X86_64
588: tcg_gen_qemu_st64(t0, a0, mem_index);
1.1 root 589: #endif
1.1.1.7 root 590: break;
591: }
592: }
1.1 root 593:
1.1.1.7 root 594: static inline void gen_op_st_T0_A0(int idx)
595: {
596: gen_op_st_v(idx, cpu_T[0], cpu_A0);
597: }
1.1 root 598:
1.1.1.7 root 599: static inline void gen_op_st_T1_A0(int idx)
600: {
601: gen_op_st_v(idx, cpu_T[1], cpu_A0);
602: }
1.1 root 603:
604: static inline void gen_jmp_im(target_ulong pc)
605: {
1.1.1.7 root 606: tcg_gen_movi_tl(cpu_tmp0, pc);
607: tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
1.1 root 608: }
609:
610: static inline void gen_string_movl_A0_ESI(DisasContext *s)
611: {
612: int override;
613:
614: override = s->override;
615: #ifdef TARGET_X86_64
616: if (s->aflag == 2) {
617: if (override >= 0) {
1.1.1.7 root 618: gen_op_movq_A0_seg(override);
619: gen_op_addq_A0_reg_sN(0, R_ESI);
1.1 root 620: } else {
1.1.1.7 root 621: gen_op_movq_A0_reg(R_ESI);
1.1 root 622: }
623: } else
624: #endif
625: if (s->aflag) {
626: /* 32 bit address */
627: if (s->addseg && override < 0)
628: override = R_DS;
629: if (override >= 0) {
1.1.1.7 root 630: gen_op_movl_A0_seg(override);
631: gen_op_addl_A0_reg_sN(0, R_ESI);
1.1 root 632: } else {
1.1.1.7 root 633: gen_op_movl_A0_reg(R_ESI);
1.1 root 634: }
635: } else {
636: /* 16 address, always override */
637: if (override < 0)
638: override = R_DS;
1.1.1.7 root 639: gen_op_movl_A0_reg(R_ESI);
1.1 root 640: gen_op_andl_A0_ffff();
1.1.1.7 root 641: gen_op_addl_A0_seg(override);
1.1 root 642: }
643: }
644:
645: static inline void gen_string_movl_A0_EDI(DisasContext *s)
646: {
647: #ifdef TARGET_X86_64
648: if (s->aflag == 2) {
1.1.1.7 root 649: gen_op_movq_A0_reg(R_EDI);
1.1 root 650: } else
651: #endif
652: if (s->aflag) {
653: if (s->addseg) {
1.1.1.7 root 654: gen_op_movl_A0_seg(R_ES);
655: gen_op_addl_A0_reg_sN(0, R_EDI);
1.1 root 656: } else {
1.1.1.7 root 657: gen_op_movl_A0_reg(R_EDI);
1.1 root 658: }
659: } else {
1.1.1.7 root 660: gen_op_movl_A0_reg(R_EDI);
1.1 root 661: gen_op_andl_A0_ffff();
1.1.1.7 root 662: gen_op_addl_A0_seg(R_ES);
1.1 root 663: }
664: }
665:
1.1.1.7 root 666: static inline void gen_op_movl_T0_Dshift(int ot)
667: {
668: tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
669: tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
1.1 root 670: };
671:
1.1.1.7 root 672: static void gen_extu(int ot, TCGv reg)
673: {
674: switch(ot) {
675: case OT_BYTE:
676: tcg_gen_ext8u_tl(reg, reg);
677: break;
678: case OT_WORD:
679: tcg_gen_ext16u_tl(reg, reg);
680: break;
681: case OT_LONG:
682: tcg_gen_ext32u_tl(reg, reg);
683: break;
684: default:
685: break;
686: }
687: }
1.1 root 688:
1.1.1.7 root 689: static void gen_exts(int ot, TCGv reg)
690: {
691: switch(ot) {
692: case OT_BYTE:
693: tcg_gen_ext8s_tl(reg, reg);
694: break;
695: case OT_WORD:
696: tcg_gen_ext16s_tl(reg, reg);
697: break;
698: case OT_LONG:
699: tcg_gen_ext32s_tl(reg, reg);
700: break;
701: default:
702: break;
703: }
704: }
1.1 root 705:
1.1.1.7 root 706: static inline void gen_op_jnz_ecx(int size, int label1)
707: {
1.1.1.9 root 708: tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
1.1.1.7 root 709: gen_extu(size + 1, cpu_tmp0);
710: tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
711: }
1.1 root 712:
1.1.1.7 root 713: static inline void gen_op_jz_ecx(int size, int label1)
714: {
1.1.1.9 root 715: tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
1.1.1.7 root 716: gen_extu(size + 1, cpu_tmp0);
717: tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
718: }
1.1 root 719:
1.1.1.7 root 720: static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
721: {
722: switch (ot) {
723: case 0: gen_helper_inb(v, n); break;
724: case 1: gen_helper_inw(v, n); break;
725: case 2: gen_helper_inl(v, n); break;
726: }
1.1 root 727:
1.1.1.7 root 728: }
1.1 root 729:
1.1.1.7 root 730: static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
731: {
732: switch (ot) {
733: case 0: gen_helper_outb(v, n); break;
734: case 1: gen_helper_outw(v, n); break;
735: case 2: gen_helper_outl(v, n); break;
736: }
1.1 root 737:
1.1.1.7 root 738: }
1.1 root 739:
1.1.1.7 root 740: static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
741: uint32_t svm_flags)
1.1 root 742: {
1.1.1.7 root 743: int state_saved;
744: target_ulong next_eip;
745:
746: state_saved = 0;
1.1 root 747: if (s->pe && (s->cpl > s->iopl || s->vm86)) {
748: if (s->cc_op != CC_OP_DYNAMIC)
749: gen_op_set_cc_op(s->cc_op);
750: gen_jmp_im(cur_eip);
1.1.1.7 root 751: state_saved = 1;
752: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
753: switch (ot) {
754: case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
755: case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
756: case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
757: }
758: }
759: if(s->flags & HF_SVMI_MASK) {
760: if (!state_saved) {
761: if (s->cc_op != CC_OP_DYNAMIC)
762: gen_op_set_cc_op(s->cc_op);
763: gen_jmp_im(cur_eip);
764: state_saved = 1;
765: }
766: svm_flags |= (1 << (4 + ot));
767: next_eip = s->pc - s->cs_base;
768: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
769: gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
770: tcg_const_i32(next_eip - cur_eip));
1.1 root 771: }
772: }
773:
774: static inline void gen_movs(DisasContext *s, int ot)
775: {
776: gen_string_movl_A0_ESI(s);
1.1.1.7 root 777: gen_op_ld_T0_A0(ot + s->mem_index);
1.1 root 778: gen_string_movl_A0_EDI(s);
1.1.1.7 root 779: gen_op_st_T0_A0(ot + s->mem_index);
780: gen_op_movl_T0_Dshift(ot);
781: gen_op_add_reg_T0(s->aflag, R_ESI);
782: gen_op_add_reg_T0(s->aflag, R_EDI);
1.1 root 783: }
784:
785: static inline void gen_update_cc_op(DisasContext *s)
786: {
787: if (s->cc_op != CC_OP_DYNAMIC) {
788: gen_op_set_cc_op(s->cc_op);
789: s->cc_op = CC_OP_DYNAMIC;
790: }
791: }
792:
1.1.1.7 root 793: static void gen_op_update1_cc(void)
794: {
795: tcg_gen_discard_tl(cpu_cc_src);
796: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
797: }
798:
799: static void gen_op_update2_cc(void)
800: {
801: tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
802: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
803: }
804:
805: static inline void gen_op_cmpl_T0_T1_cc(void)
806: {
807: tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
808: tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
809: }
810:
811: static inline void gen_op_testl_T0_T1_cc(void)
812: {
813: tcg_gen_discard_tl(cpu_cc_src);
814: tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
815: }
816:
817: static void gen_op_update_neg_cc(void)
818: {
819: tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
820: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
821: }
822:
823: /* compute eflags.C to reg */
824: static void gen_compute_eflags_c(TCGv reg)
825: {
826: gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
827: tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
828: }
829:
830: /* compute all eflags to cc_src */
831: static void gen_compute_eflags(TCGv reg)
832: {
833: gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
834: tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
835: }
836:
837: static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
838: {
839: if (s->cc_op != CC_OP_DYNAMIC)
840: gen_op_set_cc_op(s->cc_op);
841: switch(jcc_op) {
842: case JCC_O:
843: gen_compute_eflags(cpu_T[0]);
844: tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
845: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
846: break;
847: case JCC_B:
848: gen_compute_eflags_c(cpu_T[0]);
849: break;
850: case JCC_Z:
851: gen_compute_eflags(cpu_T[0]);
852: tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
853: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
854: break;
855: case JCC_BE:
856: gen_compute_eflags(cpu_tmp0);
857: tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
858: tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
859: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
860: break;
861: case JCC_S:
862: gen_compute_eflags(cpu_T[0]);
863: tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
864: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
865: break;
866: case JCC_P:
867: gen_compute_eflags(cpu_T[0]);
868: tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
869: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
870: break;
871: case JCC_L:
872: gen_compute_eflags(cpu_tmp0);
873: tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
874: tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
875: tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
876: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
877: break;
878: default:
879: case JCC_LE:
880: gen_compute_eflags(cpu_tmp0);
881: tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
882: tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
883: tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
884: tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
885: tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
886: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
887: break;
888: }
889: }
890:
891: /* return true if setcc_slow is not needed (WARNING: must be kept in
892: sync with gen_jcc1) */
893: static int is_fast_jcc_case(DisasContext *s, int b)
894: {
895: int jcc_op;
896: jcc_op = (b >> 1) & 7;
897: switch(s->cc_op) {
898: /* we optimize the cmp/jcc case */
899: case CC_OP_SUBB:
900: case CC_OP_SUBW:
901: case CC_OP_SUBL:
902: case CC_OP_SUBQ:
903: if (jcc_op == JCC_O || jcc_op == JCC_P)
904: goto slow_jcc;
905: break;
906:
907: /* some jumps are easy to compute */
908: case CC_OP_ADDB:
909: case CC_OP_ADDW:
910: case CC_OP_ADDL:
911: case CC_OP_ADDQ:
912:
913: case CC_OP_LOGICB:
914: case CC_OP_LOGICW:
915: case CC_OP_LOGICL:
916: case CC_OP_LOGICQ:
917:
918: case CC_OP_INCB:
919: case CC_OP_INCW:
920: case CC_OP_INCL:
921: case CC_OP_INCQ:
922:
923: case CC_OP_DECB:
924: case CC_OP_DECW:
925: case CC_OP_DECL:
926: case CC_OP_DECQ:
927:
928: case CC_OP_SHLB:
929: case CC_OP_SHLW:
930: case CC_OP_SHLL:
931: case CC_OP_SHLQ:
932: if (jcc_op != JCC_Z && jcc_op != JCC_S)
933: goto slow_jcc;
934: break;
935: default:
936: slow_jcc:
937: return 0;
938: }
939: return 1;
940: }
941:
942: /* generate a conditional jump to label 'l1' according to jump opcode
943: value 'b'. In the fast case, T0 is guaranted not to be used. */
944: static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
945: {
946: int inv, jcc_op, size, cond;
947: TCGv t0;
948:
949: inv = b & 1;
950: jcc_op = (b >> 1) & 7;
951:
952: switch(cc_op) {
953: /* we optimize the cmp/jcc case */
954: case CC_OP_SUBB:
955: case CC_OP_SUBW:
956: case CC_OP_SUBL:
957: case CC_OP_SUBQ:
958:
959: size = cc_op - CC_OP_SUBB;
960: switch(jcc_op) {
961: case JCC_Z:
962: fast_jcc_z:
963: switch(size) {
964: case 0:
965: tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
966: t0 = cpu_tmp0;
967: break;
968: case 1:
969: tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
970: t0 = cpu_tmp0;
971: break;
972: #ifdef TARGET_X86_64
973: case 2:
974: tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
975: t0 = cpu_tmp0;
976: break;
977: #endif
978: default:
979: t0 = cpu_cc_dst;
980: break;
981: }
982: tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
983: break;
984: case JCC_S:
985: fast_jcc_s:
986: switch(size) {
987: case 0:
988: tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
989: tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
990: 0, l1);
991: break;
992: case 1:
993: tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
994: tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
995: 0, l1);
996: break;
997: #ifdef TARGET_X86_64
998: case 2:
999: tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1000: tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1001: 0, l1);
1002: break;
1003: #endif
1004: default:
1005: tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1006: 0, l1);
1007: break;
1008: }
1009: break;
1010:
1011: case JCC_B:
1012: cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1013: goto fast_jcc_b;
1014: case JCC_BE:
1015: cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1016: fast_jcc_b:
1017: tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1018: switch(size) {
1019: case 0:
1020: t0 = cpu_tmp0;
1021: tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1022: tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1023: break;
1024: case 1:
1025: t0 = cpu_tmp0;
1026: tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1027: tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1028: break;
1029: #ifdef TARGET_X86_64
1030: case 2:
1031: t0 = cpu_tmp0;
1032: tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1033: tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1034: break;
1035: #endif
1036: default:
1037: t0 = cpu_cc_src;
1038: break;
1039: }
1040: tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1041: break;
1042:
1043: case JCC_L:
1044: cond = inv ? TCG_COND_GE : TCG_COND_LT;
1045: goto fast_jcc_l;
1046: case JCC_LE:
1047: cond = inv ? TCG_COND_GT : TCG_COND_LE;
1048: fast_jcc_l:
1049: tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1050: switch(size) {
1051: case 0:
1052: t0 = cpu_tmp0;
1053: tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1054: tcg_gen_ext8s_tl(t0, cpu_cc_src);
1055: break;
1056: case 1:
1057: t0 = cpu_tmp0;
1058: tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1059: tcg_gen_ext16s_tl(t0, cpu_cc_src);
1060: break;
1061: #ifdef TARGET_X86_64
1062: case 2:
1063: t0 = cpu_tmp0;
1064: tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1065: tcg_gen_ext32s_tl(t0, cpu_cc_src);
1066: break;
1067: #endif
1068: default:
1069: t0 = cpu_cc_src;
1070: break;
1071: }
1072: tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1073: break;
1074:
1075: default:
1076: goto slow_jcc;
1077: }
1078: break;
1079:
1080: /* some jumps are easy to compute */
1081: case CC_OP_ADDB:
1082: case CC_OP_ADDW:
1083: case CC_OP_ADDL:
1084: case CC_OP_ADDQ:
1085:
1086: case CC_OP_ADCB:
1087: case CC_OP_ADCW:
1088: case CC_OP_ADCL:
1089: case CC_OP_ADCQ:
1090:
1091: case CC_OP_SBBB:
1092: case CC_OP_SBBW:
1093: case CC_OP_SBBL:
1094: case CC_OP_SBBQ:
1095:
1096: case CC_OP_LOGICB:
1097: case CC_OP_LOGICW:
1098: case CC_OP_LOGICL:
1099: case CC_OP_LOGICQ:
1100:
1101: case CC_OP_INCB:
1102: case CC_OP_INCW:
1103: case CC_OP_INCL:
1104: case CC_OP_INCQ:
1105:
1106: case CC_OP_DECB:
1107: case CC_OP_DECW:
1108: case CC_OP_DECL:
1109: case CC_OP_DECQ:
1110:
1111: case CC_OP_SHLB:
1112: case CC_OP_SHLW:
1113: case CC_OP_SHLL:
1114: case CC_OP_SHLQ:
1115:
1116: case CC_OP_SARB:
1117: case CC_OP_SARW:
1118: case CC_OP_SARL:
1119: case CC_OP_SARQ:
1120: switch(jcc_op) {
1121: case JCC_Z:
1122: size = (cc_op - CC_OP_ADDB) & 3;
1123: goto fast_jcc_z;
1124: case JCC_S:
1125: size = (cc_op - CC_OP_ADDB) & 3;
1126: goto fast_jcc_s;
1127: default:
1128: goto slow_jcc;
1129: }
1130: break;
1131: default:
1132: slow_jcc:
1133: gen_setcc_slow_T0(s, jcc_op);
1134: tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1135: cpu_T[0], 0, l1);
1136: break;
1137: }
1138: }
1139:
1.1 root 1140: /* XXX: does not work with gdbstub "ice" single step - not a
1141: serious problem */
1142: static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1143: {
1144: int l1, l2;
1145:
1146: l1 = gen_new_label();
1147: l2 = gen_new_label();
1.1.1.7 root 1148: gen_op_jnz_ecx(s->aflag, l1);
1.1 root 1149: gen_set_label(l2);
1150: gen_jmp_tb(s, next_eip, 1);
1151: gen_set_label(l1);
1152: return l2;
1153: }
1154:
1155: static inline void gen_stos(DisasContext *s, int ot)
1156: {
1.1.1.7 root 1157: gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1.1 root 1158: gen_string_movl_A0_EDI(s);
1.1.1.7 root 1159: gen_op_st_T0_A0(ot + s->mem_index);
1160: gen_op_movl_T0_Dshift(ot);
1161: gen_op_add_reg_T0(s->aflag, R_EDI);
1.1 root 1162: }
1163:
1164: static inline void gen_lods(DisasContext *s, int ot)
1165: {
1166: gen_string_movl_A0_ESI(s);
1.1.1.7 root 1167: gen_op_ld_T0_A0(ot + s->mem_index);
1168: gen_op_mov_reg_T0(ot, R_EAX);
1169: gen_op_movl_T0_Dshift(ot);
1170: gen_op_add_reg_T0(s->aflag, R_ESI);
1.1 root 1171: }
1172:
1173: static inline void gen_scas(DisasContext *s, int ot)
1174: {
1.1.1.7 root 1175: gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1.1 root 1176: gen_string_movl_A0_EDI(s);
1.1.1.7 root 1177: gen_op_ld_T1_A0(ot + s->mem_index);
1.1 root 1178: gen_op_cmpl_T0_T1_cc();
1.1.1.7 root 1179: gen_op_movl_T0_Dshift(ot);
1180: gen_op_add_reg_T0(s->aflag, R_EDI);
1.1 root 1181: }
1182:
1183: static inline void gen_cmps(DisasContext *s, int ot)
1184: {
1185: gen_string_movl_A0_ESI(s);
1.1.1.7 root 1186: gen_op_ld_T0_A0(ot + s->mem_index);
1.1 root 1187: gen_string_movl_A0_EDI(s);
1.1.1.7 root 1188: gen_op_ld_T1_A0(ot + s->mem_index);
1.1 root 1189: gen_op_cmpl_T0_T1_cc();
1.1.1.7 root 1190: gen_op_movl_T0_Dshift(ot);
1191: gen_op_add_reg_T0(s->aflag, R_ESI);
1192: gen_op_add_reg_T0(s->aflag, R_EDI);
1.1 root 1193: }
1194:
1195: static inline void gen_ins(DisasContext *s, int ot)
1196: {
1.1.1.7 root 1197: if (use_icount)
1198: gen_io_start();
1.1 root 1199: gen_string_movl_A0_EDI(s);
1.1.1.7 root 1200: /* Note: we must do this dummy write first to be restartable in
1201: case of page fault. */
1.1 root 1202: gen_op_movl_T0_0();
1.1.1.7 root 1203: gen_op_st_T0_A0(ot + s->mem_index);
1204: gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1205: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1206: tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1207: gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1208: gen_op_st_T0_A0(ot + s->mem_index);
1209: gen_op_movl_T0_Dshift(ot);
1210: gen_op_add_reg_T0(s->aflag, R_EDI);
1211: if (use_icount)
1212: gen_io_end();
1.1 root 1213: }
1214:
1215: static inline void gen_outs(DisasContext *s, int ot)
1216: {
1.1.1.7 root 1217: if (use_icount)
1218: gen_io_start();
1.1 root 1219: gen_string_movl_A0_ESI(s);
1.1.1.7 root 1220: gen_op_ld_T0_A0(ot + s->mem_index);
1221:
1222: gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1223: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1224: tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1225: tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1226: gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1227:
1228: gen_op_movl_T0_Dshift(ot);
1229: gen_op_add_reg_T0(s->aflag, R_ESI);
1230: if (use_icount)
1231: gen_io_end();
1.1 root 1232: }
1233:
1234: /* same method as Valgrind : we generate jumps to current or next
1235: instruction */
1236: #define GEN_REPZ(op) \
1237: static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1238: target_ulong cur_eip, target_ulong next_eip) \
1239: { \
1240: int l2;\
1241: gen_update_cc_op(s); \
1242: l2 = gen_jz_ecx_string(s, next_eip); \
1243: gen_ ## op(s, ot); \
1.1.1.7 root 1244: gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1.1 root 1245: /* a loop would cause two single step exceptions if ECX = 1 \
1246: before rep string_insn */ \
1247: if (!s->jmp_opt) \
1.1.1.7 root 1248: gen_op_jz_ecx(s->aflag, l2); \
1.1 root 1249: gen_jmp(s, cur_eip); \
1250: }
1251:
1252: #define GEN_REPZ2(op) \
1253: static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1254: target_ulong cur_eip, \
1255: target_ulong next_eip, \
1256: int nz) \
1257: { \
1258: int l2;\
1259: gen_update_cc_op(s); \
1260: l2 = gen_jz_ecx_string(s, next_eip); \
1261: gen_ ## op(s, ot); \
1.1.1.7 root 1262: gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1.1 root 1263: gen_op_set_cc_op(CC_OP_SUBB + ot); \
1.1.1.7 root 1264: gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1.1 root 1265: if (!s->jmp_opt) \
1.1.1.7 root 1266: gen_op_jz_ecx(s->aflag, l2); \
1.1 root 1267: gen_jmp(s, cur_eip); \
1268: }
1269:
1270: GEN_REPZ(movs)
1271: GEN_REPZ(stos)
1272: GEN_REPZ(lods)
1273: GEN_REPZ(ins)
1274: GEN_REPZ(outs)
1275: GEN_REPZ2(scas)
1276: GEN_REPZ2(cmps)
1277:
1.1.1.7 root 1278: static void gen_helper_fp_arith_ST0_FT0(int op)
1279: {
1280: switch (op) {
1281: case 0: gen_helper_fadd_ST0_FT0(); break;
1282: case 1: gen_helper_fmul_ST0_FT0(); break;
1283: case 2: gen_helper_fcom_ST0_FT0(); break;
1284: case 3: gen_helper_fcom_ST0_FT0(); break;
1285: case 4: gen_helper_fsub_ST0_FT0(); break;
1286: case 5: gen_helper_fsubr_ST0_FT0(); break;
1287: case 6: gen_helper_fdiv_ST0_FT0(); break;
1288: case 7: gen_helper_fdivr_ST0_FT0(); break;
1289: }
1290: }
1.1 root 1291:
1292: /* NOTE the exception in "r" op ordering */
1.1.1.7 root 1293: static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1294: {
1295: TCGv_i32 tmp = tcg_const_i32(opreg);
1296: switch (op) {
1297: case 0: gen_helper_fadd_STN_ST0(tmp); break;
1298: case 1: gen_helper_fmul_STN_ST0(tmp); break;
1299: case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1300: case 5: gen_helper_fsub_STN_ST0(tmp); break;
1301: case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1302: case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1303: }
1304: }
1.1 root 1305:
1306: /* if d == OR_TMP0, it means memory operand (address in A0) */
1307: static void gen_op(DisasContext *s1, int op, int ot, int d)
1308: {
1309: if (d != OR_TMP0) {
1.1.1.7 root 1310: gen_op_mov_TN_reg(ot, 0, d);
1.1 root 1311: } else {
1.1.1.7 root 1312: gen_op_ld_T0_A0(ot + s1->mem_index);
1.1 root 1313: }
1314: switch(op) {
1315: case OP_ADCL:
1.1.1.7 root 1316: if (s1->cc_op != CC_OP_DYNAMIC)
1317: gen_op_set_cc_op(s1->cc_op);
1318: gen_compute_eflags_c(cpu_tmp4);
1319: tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1320: tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1321: if (d != OR_TMP0)
1322: gen_op_mov_reg_T0(ot, d);
1323: else
1324: gen_op_st_T0_A0(ot + s1->mem_index);
1325: tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1326: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1327: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1328: tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1329: tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1330: s1->cc_op = CC_OP_DYNAMIC;
1331: break;
1.1 root 1332: case OP_SBBL:
1333: if (s1->cc_op != CC_OP_DYNAMIC)
1334: gen_op_set_cc_op(s1->cc_op);
1.1.1.7 root 1335: gen_compute_eflags_c(cpu_tmp4);
1336: tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1337: tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1338: if (d != OR_TMP0)
1339: gen_op_mov_reg_T0(ot, d);
1340: else
1341: gen_op_st_T0_A0(ot + s1->mem_index);
1342: tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1343: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1344: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1345: tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1346: tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1.1 root 1347: s1->cc_op = CC_OP_DYNAMIC;
1.1.1.7 root 1348: break;
1.1 root 1349: case OP_ADDL:
1350: gen_op_addl_T0_T1();
1.1.1.7 root 1351: if (d != OR_TMP0)
1352: gen_op_mov_reg_T0(ot, d);
1353: else
1354: gen_op_st_T0_A0(ot + s1->mem_index);
1355: gen_op_update2_cc();
1.1 root 1356: s1->cc_op = CC_OP_ADDB + ot;
1357: break;
1358: case OP_SUBL:
1.1.1.7 root 1359: tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1360: if (d != OR_TMP0)
1361: gen_op_mov_reg_T0(ot, d);
1362: else
1363: gen_op_st_T0_A0(ot + s1->mem_index);
1364: gen_op_update2_cc();
1.1 root 1365: s1->cc_op = CC_OP_SUBB + ot;
1366: break;
1367: default:
1368: case OP_ANDL:
1.1.1.7 root 1369: tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1370: if (d != OR_TMP0)
1371: gen_op_mov_reg_T0(ot, d);
1372: else
1373: gen_op_st_T0_A0(ot + s1->mem_index);
1374: gen_op_update1_cc();
1375: s1->cc_op = CC_OP_LOGICB + ot;
1376: break;
1.1 root 1377: case OP_ORL:
1.1.1.7 root 1378: tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1379: if (d != OR_TMP0)
1380: gen_op_mov_reg_T0(ot, d);
1381: else
1382: gen_op_st_T0_A0(ot + s1->mem_index);
1383: gen_op_update1_cc();
1384: s1->cc_op = CC_OP_LOGICB + ot;
1385: break;
1.1 root 1386: case OP_XORL:
1.1.1.7 root 1387: tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1388: if (d != OR_TMP0)
1389: gen_op_mov_reg_T0(ot, d);
1390: else
1391: gen_op_st_T0_A0(ot + s1->mem_index);
1392: gen_op_update1_cc();
1.1 root 1393: s1->cc_op = CC_OP_LOGICB + ot;
1394: break;
1395: case OP_CMPL:
1396: gen_op_cmpl_T0_T1_cc();
1397: s1->cc_op = CC_OP_SUBB + ot;
1398: break;
1399: }
1.1.1.7 root 1400: }
1401:
1402: /* if d == OR_TMP0, it means memory operand (address in A0) */
1403: static void gen_inc(DisasContext *s1, int ot, int d, int c)
1404: {
1405: if (d != OR_TMP0)
1406: gen_op_mov_TN_reg(ot, 0, d);
1407: else
1408: gen_op_ld_T0_A0(ot + s1->mem_index);
1409: if (s1->cc_op != CC_OP_DYNAMIC)
1410: gen_op_set_cc_op(s1->cc_op);
1411: if (c > 0) {
1412: tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1413: s1->cc_op = CC_OP_INCB + ot;
1414: } else {
1415: tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1416: s1->cc_op = CC_OP_DECB + ot;
1417: }
1418: if (d != OR_TMP0)
1419: gen_op_mov_reg_T0(ot, d);
1420: else
1421: gen_op_st_T0_A0(ot + s1->mem_index);
1422: gen_compute_eflags_c(cpu_cc_src);
1423: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1424: }
1425:
1426: static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1427: int is_right, int is_arith)
1428: {
1429: target_ulong mask;
1430: int shift_label;
1431: TCGv t0, t1;
1432:
1433: if (ot == OT_QUAD)
1434: mask = 0x3f;
1435: else
1436: mask = 0x1f;
1437:
1438: /* load */
1439: if (op1 == OR_TMP0)
1440: gen_op_ld_T0_A0(ot + s->mem_index);
1441: else
1442: gen_op_mov_TN_reg(ot, 0, op1);
1443:
1444: tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1445:
1446: tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1447:
1448: if (is_right) {
1449: if (is_arith) {
1450: gen_exts(ot, cpu_T[0]);
1451: tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1452: tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1453: } else {
1454: gen_extu(ot, cpu_T[0]);
1455: tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1456: tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1457: }
1458: } else {
1459: tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1460: tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1461: }
1462:
1463: /* store */
1464: if (op1 == OR_TMP0)
1465: gen_op_st_T0_A0(ot + s->mem_index);
1466: else
1467: gen_op_mov_reg_T0(ot, op1);
1468:
1469: /* update eflags if non zero shift */
1470: if (s->cc_op != CC_OP_DYNAMIC)
1471: gen_op_set_cc_op(s->cc_op);
1472:
1473: /* XXX: inefficient */
1474: t0 = tcg_temp_local_new();
1475: t1 = tcg_temp_local_new();
1476:
1477: tcg_gen_mov_tl(t0, cpu_T[0]);
1478: tcg_gen_mov_tl(t1, cpu_T3);
1479:
1480: shift_label = gen_new_label();
1481: tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
1482:
1483: tcg_gen_mov_tl(cpu_cc_src, t1);
1484: tcg_gen_mov_tl(cpu_cc_dst, t0);
1485: if (is_right)
1486: tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1487: else
1488: tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1489:
1490: gen_set_label(shift_label);
1491: s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1492:
1493: tcg_temp_free(t0);
1494: tcg_temp_free(t1);
1495: }
1496:
1497: static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1498: int is_right, int is_arith)
1499: {
1500: int mask;
1501:
1502: if (ot == OT_QUAD)
1503: mask = 0x3f;
1504: else
1505: mask = 0x1f;
1506:
1507: /* load */
1508: if (op1 == OR_TMP0)
1509: gen_op_ld_T0_A0(ot + s->mem_index);
1510: else
1511: gen_op_mov_TN_reg(ot, 0, op1);
1512:
1513: op2 &= mask;
1514: if (op2 != 0) {
1515: if (is_right) {
1516: if (is_arith) {
1517: gen_exts(ot, cpu_T[0]);
1518: tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1519: tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1520: } else {
1521: gen_extu(ot, cpu_T[0]);
1522: tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1523: tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1524: }
1525: } else {
1526: tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1527: tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1528: }
1529: }
1530:
1531: /* store */
1532: if (op1 == OR_TMP0)
1533: gen_op_st_T0_A0(ot + s->mem_index);
1534: else
1535: gen_op_mov_reg_T0(ot, op1);
1536:
1537: /* update eflags if non zero shift */
1538: if (op2 != 0) {
1539: tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1540: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1541: if (is_right)
1542: s->cc_op = CC_OP_SARB + ot;
1543: else
1544: s->cc_op = CC_OP_SHLB + ot;
1545: }
1546: }
1547:
1548: static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1549: {
1550: if (arg2 >= 0)
1551: tcg_gen_shli_tl(ret, arg1, arg2);
1552: else
1553: tcg_gen_shri_tl(ret, arg1, -arg2);
1554: }
1555:
1556: static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1557: int is_right)
1558: {
1559: target_ulong mask;
1560: int label1, label2, data_bits;
1561: TCGv t0, t1, t2, a0;
1562:
1563: /* XXX: inefficient, but we must use local temps */
1564: t0 = tcg_temp_local_new();
1565: t1 = tcg_temp_local_new();
1566: t2 = tcg_temp_local_new();
1567: a0 = tcg_temp_local_new();
1568:
1569: if (ot == OT_QUAD)
1570: mask = 0x3f;
1571: else
1572: mask = 0x1f;
1573:
1574: /* load */
1575: if (op1 == OR_TMP0) {
1576: tcg_gen_mov_tl(a0, cpu_A0);
1577: gen_op_ld_v(ot + s->mem_index, t0, a0);
1578: } else {
1579: gen_op_mov_v_reg(ot, t0, op1);
1580: }
1581:
1582: tcg_gen_mov_tl(t1, cpu_T[1]);
1583:
1584: tcg_gen_andi_tl(t1, t1, mask);
1585:
1586: /* Must test zero case to avoid using undefined behaviour in TCG
1587: shifts. */
1588: label1 = gen_new_label();
1589: tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1590:
1591: if (ot <= OT_WORD)
1592: tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1593: else
1594: tcg_gen_mov_tl(cpu_tmp0, t1);
1595:
1596: gen_extu(ot, t0);
1597: tcg_gen_mov_tl(t2, t0);
1598:
1599: data_bits = 8 << ot;
1600: /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1601: fix TCG definition) */
1602: if (is_right) {
1603: tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1.1.1.9 root 1604: tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1.1.1.7 root 1605: tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1606: } else {
1607: tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1.1.1.9 root 1608: tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1.1.1.7 root 1609: tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1610: }
1611: tcg_gen_or_tl(t0, t0, cpu_tmp4);
1612:
1613: gen_set_label(label1);
1614: /* store */
1615: if (op1 == OR_TMP0) {
1616: gen_op_st_v(ot + s->mem_index, t0, a0);
1617: } else {
1618: gen_op_mov_reg_v(ot, op1, t0);
1.1 root 1619: }
1.1.1.7 root 1620:
1621: /* update eflags */
1622: if (s->cc_op != CC_OP_DYNAMIC)
1623: gen_op_set_cc_op(s->cc_op);
1.1 root 1624:
1.1.1.7 root 1625: label2 = gen_new_label();
1626: tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1627:
1628: gen_compute_eflags(cpu_cc_src);
1629: tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1630: tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1631: tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1632: tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1633: tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1634: if (is_right) {
1635: tcg_gen_shri_tl(t0, t0, data_bits - 1);
1636: }
1637: tcg_gen_andi_tl(t0, t0, CC_C);
1638: tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1639:
1640: tcg_gen_discard_tl(cpu_cc_dst);
1641: tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1642:
1643: gen_set_label(label2);
1644: s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1645:
1646: tcg_temp_free(t0);
1647: tcg_temp_free(t1);
1648: tcg_temp_free(t2);
1649: tcg_temp_free(a0);
1650: }
1651:
1.1.1.8 root 1652: static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1653: int is_right)
1654: {
1655: int mask;
1656: int data_bits;
1657: TCGv t0, t1, a0;
1658:
1659: /* XXX: inefficient, but we must use local temps */
1660: t0 = tcg_temp_local_new();
1661: t1 = tcg_temp_local_new();
1662: a0 = tcg_temp_local_new();
1663:
1664: if (ot == OT_QUAD)
1665: mask = 0x3f;
1666: else
1667: mask = 0x1f;
1668:
1669: /* load */
1670: if (op1 == OR_TMP0) {
1671: tcg_gen_mov_tl(a0, cpu_A0);
1672: gen_op_ld_v(ot + s->mem_index, t0, a0);
1673: } else {
1674: gen_op_mov_v_reg(ot, t0, op1);
1675: }
1676:
1677: gen_extu(ot, t0);
1678: tcg_gen_mov_tl(t1, t0);
1679:
1680: op2 &= mask;
1681: data_bits = 8 << ot;
1682: if (op2 != 0) {
1683: int shift = op2 & ((1 << (3 + ot)) - 1);
1684: if (is_right) {
1685: tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1686: tcg_gen_shli_tl(t0, t0, data_bits - shift);
1687: }
1688: else {
1689: tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1690: tcg_gen_shri_tl(t0, t0, data_bits - shift);
1691: }
1692: tcg_gen_or_tl(t0, t0, cpu_tmp4);
1693: }
1694:
1695: /* store */
1696: if (op1 == OR_TMP0) {
1697: gen_op_st_v(ot + s->mem_index, t0, a0);
1698: } else {
1699: gen_op_mov_reg_v(ot, op1, t0);
1700: }
1701:
1702: if (op2 != 0) {
1703: /* update eflags */
1704: if (s->cc_op != CC_OP_DYNAMIC)
1705: gen_op_set_cc_op(s->cc_op);
1706:
1707: gen_compute_eflags(cpu_cc_src);
1708: tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1709: tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1710: tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1711: tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1712: tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1713: if (is_right) {
1714: tcg_gen_shri_tl(t0, t0, data_bits - 1);
1715: }
1716: tcg_gen_andi_tl(t0, t0, CC_C);
1717: tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1718:
1719: tcg_gen_discard_tl(cpu_cc_dst);
1720: tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1721: s->cc_op = CC_OP_EFLAGS;
1722: }
1723:
1724: tcg_temp_free(t0);
1725: tcg_temp_free(t1);
1726: tcg_temp_free(a0);
1727: }
1728:
1.1.1.7 root 1729: /* XXX: add faster immediate = 1 case */
1730: static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1731: int is_right)
1.1 root 1732: {
1.1.1.7 root 1733: int label1;
1734:
1735: if (s->cc_op != CC_OP_DYNAMIC)
1736: gen_op_set_cc_op(s->cc_op);
1737:
1738: /* load */
1739: if (op1 == OR_TMP0)
1740: gen_op_ld_T0_A0(ot + s->mem_index);
1.1 root 1741: else
1.1.1.7 root 1742: gen_op_mov_TN_reg(ot, 0, op1);
1743:
1744: if (is_right) {
1745: switch (ot) {
1746: case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1747: case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1748: case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1749: #ifdef TARGET_X86_64
1750: case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1751: #endif
1752: }
1.1 root 1753: } else {
1.1.1.7 root 1754: switch (ot) {
1755: case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1756: case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1757: case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1758: #ifdef TARGET_X86_64
1759: case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1760: #endif
1761: }
1.1 root 1762: }
1.1.1.7 root 1763: /* store */
1764: if (op1 == OR_TMP0)
1765: gen_op_st_T0_A0(ot + s->mem_index);
1766: else
1767: gen_op_mov_reg_T0(ot, op1);
1768:
1769: /* update eflags */
1770: label1 = gen_new_label();
1771: tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1772:
1773: tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1774: tcg_gen_discard_tl(cpu_cc_dst);
1775: tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1776:
1777: gen_set_label(label1);
1778: s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1779: }
1780:
1781: /* XXX: add faster immediate case */
1782: static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1783: int is_right)
1784: {
1785: int label1, label2, data_bits;
1786: target_ulong mask;
1787: TCGv t0, t1, t2, a0;
1788:
1789: t0 = tcg_temp_local_new();
1790: t1 = tcg_temp_local_new();
1791: t2 = tcg_temp_local_new();
1792: a0 = tcg_temp_local_new();
1793:
1794: if (ot == OT_QUAD)
1795: mask = 0x3f;
1.1 root 1796: else
1.1.1.7 root 1797: mask = 0x1f;
1798:
1799: /* load */
1800: if (op1 == OR_TMP0) {
1801: tcg_gen_mov_tl(a0, cpu_A0);
1802: gen_op_ld_v(ot + s->mem_index, t0, a0);
1803: } else {
1804: gen_op_mov_v_reg(ot, t0, op1);
1805: }
1806:
1807: tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1808:
1809: tcg_gen_mov_tl(t1, cpu_T[1]);
1810: tcg_gen_mov_tl(t2, cpu_T3);
1811:
1812: /* Must test zero case to avoid using undefined behaviour in TCG
1813: shifts. */
1814: label1 = gen_new_label();
1815: tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1816:
1817: tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1818: if (ot == OT_WORD) {
1819: /* Note: we implement the Intel behaviour for shift count > 16 */
1820: if (is_right) {
1821: tcg_gen_andi_tl(t0, t0, 0xffff);
1822: tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1823: tcg_gen_or_tl(t0, t0, cpu_tmp0);
1824: tcg_gen_ext32u_tl(t0, t0);
1825:
1826: tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1827:
1828: /* only needed if count > 16, but a test would complicate */
1.1.1.9 root 1829: tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1.1.1.7 root 1830: tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1831:
1832: tcg_gen_shr_tl(t0, t0, t2);
1833:
1834: tcg_gen_or_tl(t0, t0, cpu_tmp0);
1835: } else {
1836: /* XXX: not optimal */
1837: tcg_gen_andi_tl(t0, t0, 0xffff);
1838: tcg_gen_shli_tl(t1, t1, 16);
1839: tcg_gen_or_tl(t1, t1, t0);
1840: tcg_gen_ext32u_tl(t1, t1);
1841:
1842: tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1.1.1.9 root 1843: tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1844: tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1845: tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1.1.1.7 root 1846:
1847: tcg_gen_shl_tl(t0, t0, t2);
1.1.1.9 root 1848: tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1.1.1.7 root 1849: tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1850: tcg_gen_or_tl(t0, t0, t1);
1851: }
1852: } else {
1853: data_bits = 8 << ot;
1854: if (is_right) {
1855: if (ot == OT_LONG)
1856: tcg_gen_ext32u_tl(t0, t0);
1857:
1858: tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1859:
1860: tcg_gen_shr_tl(t0, t0, t2);
1.1.1.9 root 1861: tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1.1.1.7 root 1862: tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1863: tcg_gen_or_tl(t0, t0, t1);
1864:
1865: } else {
1866: if (ot == OT_LONG)
1867: tcg_gen_ext32u_tl(t1, t1);
1868:
1869: tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1870:
1871: tcg_gen_shl_tl(t0, t0, t2);
1.1.1.9 root 1872: tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1.1.1.7 root 1873: tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1874: tcg_gen_or_tl(t0, t0, t1);
1875: }
1876: }
1877: tcg_gen_mov_tl(t1, cpu_tmp4);
1878:
1879: gen_set_label(label1);
1880: /* store */
1881: if (op1 == OR_TMP0) {
1882: gen_op_st_v(ot + s->mem_index, t0, a0);
1883: } else {
1884: gen_op_mov_reg_v(ot, op1, t0);
1885: }
1886:
1887: /* update eflags */
1888: if (s->cc_op != CC_OP_DYNAMIC)
1889: gen_op_set_cc_op(s->cc_op);
1890:
1891: label2 = gen_new_label();
1892: tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1893:
1894: tcg_gen_mov_tl(cpu_cc_src, t1);
1895: tcg_gen_mov_tl(cpu_cc_dst, t0);
1896: if (is_right) {
1897: tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1898: } else {
1899: tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1900: }
1901: gen_set_label(label2);
1902: s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1903:
1904: tcg_temp_free(t0);
1905: tcg_temp_free(t1);
1906: tcg_temp_free(t2);
1907: tcg_temp_free(a0);
1.1 root 1908: }
1909:
1910: static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1911: {
1912: if (s != OR_TMP1)
1.1.1.7 root 1913: gen_op_mov_TN_reg(ot, 1, s);
1914: switch(op) {
1915: case OP_ROL:
1916: gen_rot_rm_T1(s1, ot, d, 0);
1917: break;
1918: case OP_ROR:
1919: gen_rot_rm_T1(s1, ot, d, 1);
1920: break;
1921: case OP_SHL:
1922: case OP_SHL1:
1923: gen_shift_rm_T1(s1, ot, d, 0, 0);
1924: break;
1925: case OP_SHR:
1926: gen_shift_rm_T1(s1, ot, d, 1, 0);
1927: break;
1928: case OP_SAR:
1929: gen_shift_rm_T1(s1, ot, d, 1, 1);
1930: break;
1931: case OP_RCL:
1932: gen_rotc_rm_T1(s1, ot, d, 0);
1933: break;
1934: case OP_RCR:
1935: gen_rotc_rm_T1(s1, ot, d, 1);
1936: break;
1937: }
1.1 root 1938: }
1939:
1940: static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1941: {
1.1.1.7 root 1942: switch(op) {
1.1.1.8 root 1943: case OP_ROL:
1944: gen_rot_rm_im(s1, ot, d, c, 0);
1945: break;
1946: case OP_ROR:
1947: gen_rot_rm_im(s1, ot, d, c, 1);
1948: break;
1.1.1.7 root 1949: case OP_SHL:
1950: case OP_SHL1:
1951: gen_shift_rm_im(s1, ot, d, c, 0, 0);
1952: break;
1953: case OP_SHR:
1954: gen_shift_rm_im(s1, ot, d, c, 1, 0);
1955: break;
1956: case OP_SAR:
1957: gen_shift_rm_im(s1, ot, d, c, 1, 1);
1958: break;
1959: default:
1960: /* currently not optimized */
1961: gen_op_movl_T1_im(c);
1962: gen_shift(s1, op, ot, d, OR_TMP1);
1963: break;
1964: }
1.1 root 1965: }
1966:
1967: static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1968: {
1969: target_long disp;
1970: int havesib;
1971: int base;
1972: int index;
1973: int scale;
1974: int opreg;
1975: int mod, rm, code, override, must_add_seg;
1976:
1977: override = s->override;
1978: must_add_seg = s->addseg;
1979: if (override >= 0)
1980: must_add_seg = 1;
1981: mod = (modrm >> 6) & 3;
1982: rm = modrm & 7;
1983:
1984: if (s->aflag) {
1985:
1986: havesib = 0;
1987: base = rm;
1988: index = 0;
1989: scale = 0;
1.1.1.6 root 1990:
1.1 root 1991: if (base == 4) {
1992: havesib = 1;
1993: code = ldub_code(s->pc++);
1994: scale = (code >> 6) & 3;
1995: index = ((code >> 3) & 7) | REX_X(s);
1996: base = (code & 7);
1997: }
1998: base |= REX_B(s);
1999:
2000: switch (mod) {
2001: case 0:
2002: if ((base & 7) == 5) {
2003: base = -1;
2004: disp = (int32_t)ldl_code(s->pc);
2005: s->pc += 4;
2006: if (CODE64(s) && !havesib) {
2007: disp += s->pc + s->rip_offset;
2008: }
2009: } else {
2010: disp = 0;
2011: }
2012: break;
2013: case 1:
2014: disp = (int8_t)ldub_code(s->pc++);
2015: break;
2016: default:
2017: case 2:
2018: disp = ldl_code(s->pc);
2019: s->pc += 4;
2020: break;
2021: }
1.1.1.6 root 2022:
1.1 root 2023: if (base >= 0) {
2024: /* for correct popl handling with esp */
2025: if (base == 4 && s->popl_esp_hack)
2026: disp += s->popl_esp_hack;
2027: #ifdef TARGET_X86_64
2028: if (s->aflag == 2) {
1.1.1.7 root 2029: gen_op_movq_A0_reg(base);
1.1 root 2030: if (disp != 0) {
1.1.1.7 root 2031: gen_op_addq_A0_im(disp);
1.1 root 2032: }
1.1.1.6 root 2033: } else
1.1 root 2034: #endif
2035: {
1.1.1.7 root 2036: gen_op_movl_A0_reg(base);
1.1 root 2037: if (disp != 0)
2038: gen_op_addl_A0_im(disp);
2039: }
2040: } else {
2041: #ifdef TARGET_X86_64
2042: if (s->aflag == 2) {
1.1.1.7 root 2043: gen_op_movq_A0_im(disp);
1.1.1.6 root 2044: } else
1.1 root 2045: #endif
2046: {
2047: gen_op_movl_A0_im(disp);
2048: }
2049: }
1.1.1.11 root 2050: /* index == 4 means no index */
2051: if (havesib && (index != 4)) {
1.1 root 2052: #ifdef TARGET_X86_64
2053: if (s->aflag == 2) {
1.1.1.7 root 2054: gen_op_addq_A0_reg_sN(scale, index);
1.1.1.6 root 2055: } else
1.1 root 2056: #endif
2057: {
1.1.1.7 root 2058: gen_op_addl_A0_reg_sN(scale, index);
1.1 root 2059: }
2060: }
2061: if (must_add_seg) {
2062: if (override < 0) {
2063: if (base == R_EBP || base == R_ESP)
2064: override = R_SS;
2065: else
2066: override = R_DS;
2067: }
2068: #ifdef TARGET_X86_64
2069: if (s->aflag == 2) {
1.1.1.7 root 2070: gen_op_addq_A0_seg(override);
1.1.1.6 root 2071: } else
1.1 root 2072: #endif
2073: {
1.1.1.7 root 2074: gen_op_addl_A0_seg(override);
1.1 root 2075: }
2076: }
2077: } else {
2078: switch (mod) {
2079: case 0:
2080: if (rm == 6) {
2081: disp = lduw_code(s->pc);
2082: s->pc += 2;
2083: gen_op_movl_A0_im(disp);
2084: rm = 0; /* avoid SS override */
2085: goto no_rm;
2086: } else {
2087: disp = 0;
2088: }
2089: break;
2090: case 1:
2091: disp = (int8_t)ldub_code(s->pc++);
2092: break;
2093: default:
2094: case 2:
2095: disp = lduw_code(s->pc);
2096: s->pc += 2;
2097: break;
2098: }
2099: switch(rm) {
2100: case 0:
1.1.1.7 root 2101: gen_op_movl_A0_reg(R_EBX);
2102: gen_op_addl_A0_reg_sN(0, R_ESI);
1.1 root 2103: break;
2104: case 1:
1.1.1.7 root 2105: gen_op_movl_A0_reg(R_EBX);
2106: gen_op_addl_A0_reg_sN(0, R_EDI);
1.1 root 2107: break;
2108: case 2:
1.1.1.7 root 2109: gen_op_movl_A0_reg(R_EBP);
2110: gen_op_addl_A0_reg_sN(0, R_ESI);
1.1 root 2111: break;
2112: case 3:
1.1.1.7 root 2113: gen_op_movl_A0_reg(R_EBP);
2114: gen_op_addl_A0_reg_sN(0, R_EDI);
1.1 root 2115: break;
2116: case 4:
1.1.1.7 root 2117: gen_op_movl_A0_reg(R_ESI);
1.1 root 2118: break;
2119: case 5:
1.1.1.7 root 2120: gen_op_movl_A0_reg(R_EDI);
1.1 root 2121: break;
2122: case 6:
1.1.1.7 root 2123: gen_op_movl_A0_reg(R_EBP);
1.1 root 2124: break;
2125: default:
2126: case 7:
1.1.1.7 root 2127: gen_op_movl_A0_reg(R_EBX);
1.1 root 2128: break;
2129: }
2130: if (disp != 0)
2131: gen_op_addl_A0_im(disp);
2132: gen_op_andl_A0_ffff();
2133: no_rm:
2134: if (must_add_seg) {
2135: if (override < 0) {
2136: if (rm == 2 || rm == 3 || rm == 6)
2137: override = R_SS;
2138: else
2139: override = R_DS;
2140: }
1.1.1.7 root 2141: gen_op_addl_A0_seg(override);
1.1 root 2142: }
2143: }
2144:
2145: opreg = OR_A0;
2146: disp = 0;
2147: *reg_ptr = opreg;
2148: *offset_ptr = disp;
2149: }
2150:
1.1.1.5 root 2151: static void gen_nop_modrm(DisasContext *s, int modrm)
2152: {
2153: int mod, rm, base, code;
2154:
2155: mod = (modrm >> 6) & 3;
2156: if (mod == 3)
2157: return;
2158: rm = modrm & 7;
2159:
2160: if (s->aflag) {
2161:
2162: base = rm;
1.1.1.6 root 2163:
1.1.1.5 root 2164: if (base == 4) {
2165: code = ldub_code(s->pc++);
2166: base = (code & 7);
2167: }
1.1.1.6 root 2168:
1.1.1.5 root 2169: switch (mod) {
2170: case 0:
2171: if (base == 5) {
2172: s->pc += 4;
2173: }
2174: break;
2175: case 1:
2176: s->pc++;
2177: break;
2178: default:
2179: case 2:
2180: s->pc += 4;
2181: break;
2182: }
2183: } else {
2184: switch (mod) {
2185: case 0:
2186: if (rm == 6) {
2187: s->pc += 2;
2188: }
2189: break;
2190: case 1:
2191: s->pc++;
2192: break;
2193: default:
2194: case 2:
2195: s->pc += 2;
2196: break;
2197: }
2198: }
2199: }
2200:
1.1 root 2201: /* used for LEA and MOV AX, mem */
2202: static void gen_add_A0_ds_seg(DisasContext *s)
2203: {
2204: int override, must_add_seg;
2205: must_add_seg = s->addseg;
2206: override = R_DS;
2207: if (s->override >= 0) {
2208: override = s->override;
2209: must_add_seg = 1;
2210: } else {
2211: override = R_DS;
2212: }
2213: if (must_add_seg) {
2214: #ifdef TARGET_X86_64
2215: if (CODE64(s)) {
1.1.1.7 root 2216: gen_op_addq_A0_seg(override);
1.1.1.6 root 2217: } else
1.1 root 2218: #endif
2219: {
1.1.1.7 root 2220: gen_op_addl_A0_seg(override);
1.1 root 2221: }
2222: }
2223: }
2224:
1.1.1.7 root 2225: /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
1.1 root 2226: OR_TMP0 */
2227: static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2228: {
2229: int mod, rm, opreg, disp;
2230:
2231: mod = (modrm >> 6) & 3;
2232: rm = (modrm & 7) | REX_B(s);
2233: if (mod == 3) {
2234: if (is_store) {
2235: if (reg != OR_TMP0)
1.1.1.7 root 2236: gen_op_mov_TN_reg(ot, 0, reg);
2237: gen_op_mov_reg_T0(ot, rm);
1.1 root 2238: } else {
1.1.1.7 root 2239: gen_op_mov_TN_reg(ot, 0, rm);
1.1 root 2240: if (reg != OR_TMP0)
1.1.1.7 root 2241: gen_op_mov_reg_T0(ot, reg);
1.1 root 2242: }
2243: } else {
2244: gen_lea_modrm(s, modrm, &opreg, &disp);
2245: if (is_store) {
2246: if (reg != OR_TMP0)
1.1.1.7 root 2247: gen_op_mov_TN_reg(ot, 0, reg);
2248: gen_op_st_T0_A0(ot + s->mem_index);
1.1 root 2249: } else {
1.1.1.7 root 2250: gen_op_ld_T0_A0(ot + s->mem_index);
1.1 root 2251: if (reg != OR_TMP0)
1.1.1.7 root 2252: gen_op_mov_reg_T0(ot, reg);
1.1 root 2253: }
2254: }
2255: }
2256:
2257: static inline uint32_t insn_get(DisasContext *s, int ot)
2258: {
2259: uint32_t ret;
2260:
2261: switch(ot) {
2262: case OT_BYTE:
2263: ret = ldub_code(s->pc);
2264: s->pc++;
2265: break;
2266: case OT_WORD:
2267: ret = lduw_code(s->pc);
2268: s->pc += 2;
2269: break;
2270: default:
2271: case OT_LONG:
2272: ret = ldl_code(s->pc);
2273: s->pc += 4;
2274: break;
2275: }
2276: return ret;
2277: }
2278:
2279: static inline int insn_const_size(unsigned int ot)
2280: {
2281: if (ot <= OT_LONG)
2282: return 1 << ot;
2283: else
2284: return 4;
2285: }
2286:
1.1.1.2 root 2287: static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2288: {
2289: TranslationBlock *tb;
2290: target_ulong pc;
2291:
2292: pc = s->cs_base + eip;
2293: tb = s->tb;
2294: /* NOTE: we handle the case where the TB spans two pages here */
2295: if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2296: (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2297: /* jump to same page: we can use a direct jump */
1.1.1.7 root 2298: tcg_gen_goto_tb(tb_num);
1.1.1.2 root 2299: gen_jmp_im(eip);
1.1.1.7 root 2300: tcg_gen_exit_tb((long)tb + tb_num);
1.1.1.2 root 2301: } else {
2302: /* jump to another page: currently not optimized */
2303: gen_jmp_im(eip);
2304: gen_eob(s);
2305: }
2306: }
2307:
1.1.1.6 root 2308: static inline void gen_jcc(DisasContext *s, int b,
1.1 root 2309: target_ulong val, target_ulong next_eip)
2310: {
1.1.1.7 root 2311: int l1, l2, cc_op;
1.1.1.6 root 2312:
1.1.1.7 root 2313: cc_op = s->cc_op;
2314: if (s->cc_op != CC_OP_DYNAMIC) {
2315: gen_op_set_cc_op(s->cc_op);
2316: s->cc_op = CC_OP_DYNAMIC;
2317: }
1.1 root 2318: if (s->jmp_opt) {
2319: l1 = gen_new_label();
1.1.1.7 root 2320: gen_jcc1(s, cc_op, b, l1);
2321:
1.1.1.2 root 2322: gen_goto_tb(s, 0, next_eip);
1.1 root 2323:
2324: gen_set_label(l1);
1.1.1.2 root 2325: gen_goto_tb(s, 1, val);
1.1 root 2326: s->is_jmp = 3;
2327: } else {
2328:
2329: l1 = gen_new_label();
2330: l2 = gen_new_label();
1.1.1.7 root 2331: gen_jcc1(s, cc_op, b, l1);
2332:
1.1 root 2333: gen_jmp_im(next_eip);
1.1.1.7 root 2334: tcg_gen_br(l2);
2335:
1.1 root 2336: gen_set_label(l1);
2337: gen_jmp_im(val);
2338: gen_set_label(l2);
2339: gen_eob(s);
2340: }
2341: }
2342:
2343: static void gen_setcc(DisasContext *s, int b)
2344: {
1.1.1.7 root 2345: int inv, jcc_op, l1;
2346: TCGv t0;
1.1.1.6 root 2347:
1.1.1.7 root 2348: if (is_fast_jcc_case(s, b)) {
2349: /* nominal case: we use a jump */
2350: /* XXX: make it faster by adding new instructions in TCG */
2351: t0 = tcg_temp_local_new();
2352: tcg_gen_movi_tl(t0, 0);
2353: l1 = gen_new_label();
2354: gen_jcc1(s, s->cc_op, b ^ 1, l1);
2355: tcg_gen_movi_tl(t0, 1);
2356: gen_set_label(l1);
2357: tcg_gen_mov_tl(cpu_T[0], t0);
2358: tcg_temp_free(t0);
2359: } else {
2360: /* slow case: it is more efficient not to generate a jump,
2361: although it is questionnable whether this optimization is
2362: worth to */
2363: inv = b & 1;
2364: jcc_op = (b >> 1) & 7;
2365: gen_setcc_slow_T0(s, jcc_op);
2366: if (inv) {
2367: tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
1.1 root 2368: }
2369: }
2370: }
2371:
1.1.1.7 root 2372: static inline void gen_op_movl_T0_seg(int seg_reg)
2373: {
2374: tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2375: offsetof(CPUX86State,segs[seg_reg].selector));
2376: }
2377:
2378: static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2379: {
2380: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2381: tcg_gen_st32_tl(cpu_T[0], cpu_env,
2382: offsetof(CPUX86State,segs[seg_reg].selector));
2383: tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2384: tcg_gen_st_tl(cpu_T[0], cpu_env,
2385: offsetof(CPUX86State,segs[seg_reg].base));
2386: }
2387:
1.1 root 2388: /* move T0 to seg_reg and compute if the CPU state may change. Never
2389: call this function with seg_reg == R_CS */
2390: static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2391: {
2392: if (s->pe && !s->vm86) {
2393: /* XXX: optimize by finding processor state dynamically */
2394: if (s->cc_op != CC_OP_DYNAMIC)
2395: gen_op_set_cc_op(s->cc_op);
2396: gen_jmp_im(cur_eip);
1.1.1.7 root 2397: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2398: gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
1.1 root 2399: /* abort translation because the addseg value may change or
2400: because ss32 may change. For R_SS, translation must always
2401: stop as a special handling must be done to disable hardware
2402: interrupts for the next instruction */
2403: if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2404: s->is_jmp = 3;
2405: } else {
1.1.1.7 root 2406: gen_op_movl_seg_T0_vm(seg_reg);
1.1 root 2407: if (seg_reg == R_SS)
2408: s->is_jmp = 3;
2409: }
2410: }
2411:
1.1.1.6 root 2412: static inline int svm_is_rep(int prefixes)
2413: {
2414: return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2415: }
2416:
1.1.1.7 root 2417: static inline void
1.1.1.6 root 2418: gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
1.1.1.7 root 2419: uint32_t type, uint64_t param)
1.1.1.6 root 2420: {
1.1.1.7 root 2421: /* no SVM activated; fast case */
2422: if (likely(!(s->flags & HF_SVMI_MASK)))
2423: return;
2424: if (s->cc_op != CC_OP_DYNAMIC)
2425: gen_op_set_cc_op(s->cc_op);
2426: gen_jmp_im(pc_start - s->cs_base);
2427: gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2428: tcg_const_i64(param));
1.1.1.6 root 2429: }
2430:
1.1.1.7 root 2431: static inline void
1.1.1.6 root 2432: gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2433: {
1.1.1.7 root 2434: gen_svm_check_intercept_param(s, pc_start, type, 0);
1.1.1.6 root 2435: }
2436:
1.1 root 2437: static inline void gen_stack_update(DisasContext *s, int addend)
2438: {
2439: #ifdef TARGET_X86_64
2440: if (CODE64(s)) {
1.1.1.7 root 2441: gen_op_add_reg_im(2, R_ESP, addend);
1.1 root 2442: } else
2443: #endif
2444: if (s->ss32) {
1.1.1.7 root 2445: gen_op_add_reg_im(1, R_ESP, addend);
1.1 root 2446: } else {
1.1.1.7 root 2447: gen_op_add_reg_im(0, R_ESP, addend);
1.1 root 2448: }
2449: }
2450:
2451: /* generate a push. It depends on ss32, addseg and dflag */
2452: static void gen_push_T0(DisasContext *s)
2453: {
2454: #ifdef TARGET_X86_64
2455: if (CODE64(s)) {
1.1.1.7 root 2456: gen_op_movq_A0_reg(R_ESP);
1.1 root 2457: if (s->dflag) {
1.1.1.7 root 2458: gen_op_addq_A0_im(-8);
2459: gen_op_st_T0_A0(OT_QUAD + s->mem_index);
1.1 root 2460: } else {
1.1.1.7 root 2461: gen_op_addq_A0_im(-2);
2462: gen_op_st_T0_A0(OT_WORD + s->mem_index);
1.1 root 2463: }
1.1.1.7 root 2464: gen_op_mov_reg_A0(2, R_ESP);
1.1.1.6 root 2465: } else
1.1 root 2466: #endif
2467: {
1.1.1.7 root 2468: gen_op_movl_A0_reg(R_ESP);
1.1 root 2469: if (!s->dflag)
1.1.1.7 root 2470: gen_op_addl_A0_im(-2);
1.1 root 2471: else
1.1.1.7 root 2472: gen_op_addl_A0_im(-4);
1.1 root 2473: if (s->ss32) {
2474: if (s->addseg) {
1.1.1.7 root 2475: tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2476: gen_op_addl_A0_seg(R_SS);
1.1 root 2477: }
2478: } else {
2479: gen_op_andl_A0_ffff();
1.1.1.7 root 2480: tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2481: gen_op_addl_A0_seg(R_SS);
1.1 root 2482: }
1.1.1.7 root 2483: gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
1.1 root 2484: if (s->ss32 && !s->addseg)
1.1.1.7 root 2485: gen_op_mov_reg_A0(1, R_ESP);
1.1 root 2486: else
1.1.1.7 root 2487: gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
1.1 root 2488: }
2489: }
2490:
2491: /* generate a push. It depends on ss32, addseg and dflag */
2492: /* slower version for T1, only used for call Ev */
2493: static void gen_push_T1(DisasContext *s)
2494: {
2495: #ifdef TARGET_X86_64
2496: if (CODE64(s)) {
1.1.1.7 root 2497: gen_op_movq_A0_reg(R_ESP);
1.1 root 2498: if (s->dflag) {
1.1.1.7 root 2499: gen_op_addq_A0_im(-8);
2500: gen_op_st_T1_A0(OT_QUAD + s->mem_index);
1.1 root 2501: } else {
1.1.1.7 root 2502: gen_op_addq_A0_im(-2);
2503: gen_op_st_T0_A0(OT_WORD + s->mem_index);
1.1 root 2504: }
1.1.1.7 root 2505: gen_op_mov_reg_A0(2, R_ESP);
1.1.1.6 root 2506: } else
1.1 root 2507: #endif
2508: {
1.1.1.7 root 2509: gen_op_movl_A0_reg(R_ESP);
1.1 root 2510: if (!s->dflag)
1.1.1.7 root 2511: gen_op_addl_A0_im(-2);
1.1 root 2512: else
1.1.1.7 root 2513: gen_op_addl_A0_im(-4);
1.1 root 2514: if (s->ss32) {
2515: if (s->addseg) {
1.1.1.7 root 2516: gen_op_addl_A0_seg(R_SS);
1.1 root 2517: }
2518: } else {
2519: gen_op_andl_A0_ffff();
1.1.1.7 root 2520: gen_op_addl_A0_seg(R_SS);
1.1 root 2521: }
1.1.1.7 root 2522: gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
1.1.1.6 root 2523:
1.1 root 2524: if (s->ss32 && !s->addseg)
1.1.1.7 root 2525: gen_op_mov_reg_A0(1, R_ESP);
1.1 root 2526: else
2527: gen_stack_update(s, (-2) << s->dflag);
2528: }
2529: }
2530:
2531: /* two step pop is necessary for precise exceptions */
2532: static void gen_pop_T0(DisasContext *s)
2533: {
2534: #ifdef TARGET_X86_64
2535: if (CODE64(s)) {
1.1.1.7 root 2536: gen_op_movq_A0_reg(R_ESP);
2537: gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
1.1.1.6 root 2538: } else
1.1 root 2539: #endif
2540: {
1.1.1.7 root 2541: gen_op_movl_A0_reg(R_ESP);
1.1 root 2542: if (s->ss32) {
2543: if (s->addseg)
1.1.1.7 root 2544: gen_op_addl_A0_seg(R_SS);
1.1 root 2545: } else {
2546: gen_op_andl_A0_ffff();
1.1.1.7 root 2547: gen_op_addl_A0_seg(R_SS);
1.1 root 2548: }
1.1.1.7 root 2549: gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
1.1 root 2550: }
2551: }
2552:
2553: static void gen_pop_update(DisasContext *s)
2554: {
2555: #ifdef TARGET_X86_64
2556: if (CODE64(s) && s->dflag) {
2557: gen_stack_update(s, 8);
2558: } else
2559: #endif
2560: {
2561: gen_stack_update(s, 2 << s->dflag);
2562: }
2563: }
2564:
2565: static void gen_stack_A0(DisasContext *s)
2566: {
1.1.1.7 root 2567: gen_op_movl_A0_reg(R_ESP);
1.1 root 2568: if (!s->ss32)
2569: gen_op_andl_A0_ffff();
1.1.1.7 root 2570: tcg_gen_mov_tl(cpu_T[1], cpu_A0);
1.1 root 2571: if (s->addseg)
1.1.1.7 root 2572: gen_op_addl_A0_seg(R_SS);
1.1 root 2573: }
2574:
2575: /* NOTE: wrap around in 16 bit not fully handled */
2576: static void gen_pusha(DisasContext *s)
2577: {
2578: int i;
1.1.1.7 root 2579: gen_op_movl_A0_reg(R_ESP);
1.1 root 2580: gen_op_addl_A0_im(-16 << s->dflag);
2581: if (!s->ss32)
2582: gen_op_andl_A0_ffff();
1.1.1.7 root 2583: tcg_gen_mov_tl(cpu_T[1], cpu_A0);
1.1 root 2584: if (s->addseg)
1.1.1.7 root 2585: gen_op_addl_A0_seg(R_SS);
1.1 root 2586: for(i = 0;i < 8; i++) {
1.1.1.7 root 2587: gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2588: gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
1.1 root 2589: gen_op_addl_A0_im(2 << s->dflag);
2590: }
1.1.1.7 root 2591: gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
1.1 root 2592: }
2593:
2594: /* NOTE: wrap around in 16 bit not fully handled */
2595: static void gen_popa(DisasContext *s)
2596: {
2597: int i;
1.1.1.7 root 2598: gen_op_movl_A0_reg(R_ESP);
1.1 root 2599: if (!s->ss32)
2600: gen_op_andl_A0_ffff();
1.1.1.7 root 2601: tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2602: tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
1.1 root 2603: if (s->addseg)
1.1.1.7 root 2604: gen_op_addl_A0_seg(R_SS);
1.1 root 2605: for(i = 0;i < 8; i++) {
2606: /* ESP is not reloaded */
2607: if (i != 3) {
1.1.1.7 root 2608: gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2609: gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
1.1 root 2610: }
2611: gen_op_addl_A0_im(2 << s->dflag);
2612: }
1.1.1.7 root 2613: gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
1.1 root 2614: }
2615:
2616: static void gen_enter(DisasContext *s, int esp_addend, int level)
2617: {
2618: int ot, opsize;
2619:
2620: level &= 0x1f;
2621: #ifdef TARGET_X86_64
2622: if (CODE64(s)) {
2623: ot = s->dflag ? OT_QUAD : OT_WORD;
2624: opsize = 1 << ot;
1.1.1.6 root 2625:
1.1.1.7 root 2626: gen_op_movl_A0_reg(R_ESP);
1.1 root 2627: gen_op_addq_A0_im(-opsize);
1.1.1.7 root 2628: tcg_gen_mov_tl(cpu_T[1], cpu_A0);
1.1 root 2629:
2630: /* push bp */
1.1.1.7 root 2631: gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2632: gen_op_st_T0_A0(ot + s->mem_index);
1.1 root 2633: if (level) {
1.1.1.7 root 2634: /* XXX: must save state */
2635: gen_helper_enter64_level(tcg_const_i32(level),
2636: tcg_const_i32((ot == OT_QUAD)),
2637: cpu_T[1]);
2638: }
2639: gen_op_mov_reg_T1(ot, R_EBP);
2640: tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2641: gen_op_mov_reg_T1(OT_QUAD, R_ESP);
1.1.1.6 root 2642: } else
1.1 root 2643: #endif
2644: {
2645: ot = s->dflag + OT_WORD;
2646: opsize = 2 << s->dflag;
1.1.1.6 root 2647:
1.1.1.7 root 2648: gen_op_movl_A0_reg(R_ESP);
1.1 root 2649: gen_op_addl_A0_im(-opsize);
2650: if (!s->ss32)
2651: gen_op_andl_A0_ffff();
1.1.1.7 root 2652: tcg_gen_mov_tl(cpu_T[1], cpu_A0);
1.1 root 2653: if (s->addseg)
1.1.1.7 root 2654: gen_op_addl_A0_seg(R_SS);
1.1 root 2655: /* push bp */
1.1.1.7 root 2656: gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2657: gen_op_st_T0_A0(ot + s->mem_index);
1.1 root 2658: if (level) {
1.1.1.7 root 2659: /* XXX: must save state */
2660: gen_helper_enter_level(tcg_const_i32(level),
2661: tcg_const_i32(s->dflag),
2662: cpu_T[1]);
2663: }
2664: gen_op_mov_reg_T1(ot, R_EBP);
2665: tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2666: gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
1.1 root 2667: }
2668: }
2669:
2670: static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2671: {
2672: if (s->cc_op != CC_OP_DYNAMIC)
2673: gen_op_set_cc_op(s->cc_op);
2674: gen_jmp_im(cur_eip);
1.1.1.7 root 2675: gen_helper_raise_exception(tcg_const_i32(trapno));
1.1 root 2676: s->is_jmp = 3;
2677: }
2678:
2679: /* an interrupt is different from an exception because of the
1.1.1.6 root 2680: privilege checks */
2681: static void gen_interrupt(DisasContext *s, int intno,
1.1 root 2682: target_ulong cur_eip, target_ulong next_eip)
2683: {
2684: if (s->cc_op != CC_OP_DYNAMIC)
2685: gen_op_set_cc_op(s->cc_op);
2686: gen_jmp_im(cur_eip);
1.1.1.7 root 2687: gen_helper_raise_interrupt(tcg_const_i32(intno),
2688: tcg_const_i32(next_eip - cur_eip));
1.1 root 2689: s->is_jmp = 3;
2690: }
2691:
2692: static void gen_debug(DisasContext *s, target_ulong cur_eip)
2693: {
2694: if (s->cc_op != CC_OP_DYNAMIC)
2695: gen_op_set_cc_op(s->cc_op);
2696: gen_jmp_im(cur_eip);
1.1.1.7 root 2697: gen_helper_debug();
1.1 root 2698: s->is_jmp = 3;
2699: }
2700:
2701: /* generate a generic end of block. Trace exception is also generated
2702: if needed */
2703: static void gen_eob(DisasContext *s)
2704: {
2705: if (s->cc_op != CC_OP_DYNAMIC)
2706: gen_op_set_cc_op(s->cc_op);
2707: if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
1.1.1.7 root 2708: gen_helper_reset_inhibit_irq();
1.1 root 2709: }
1.1.1.8 root 2710: if (s->tb->flags & HF_RF_MASK) {
2711: gen_helper_reset_rf();
2712: }
1.1 root 2713: if (s->singlestep_enabled) {
1.1.1.7 root 2714: gen_helper_debug();
1.1 root 2715: } else if (s->tf) {
1.1.1.7 root 2716: gen_helper_single_step();
1.1 root 2717: } else {
1.1.1.7 root 2718: tcg_gen_exit_tb(0);
1.1 root 2719: }
2720: s->is_jmp = 3;
2721: }
2722:
2723: /* generate a jump to eip. No segment change must happen before as a
2724: direct call to the next block may occur */
2725: static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2726: {
2727: if (s->jmp_opt) {
1.1.1.2 root 2728: if (s->cc_op != CC_OP_DYNAMIC) {
1.1 root 2729: gen_op_set_cc_op(s->cc_op);
1.1.1.2 root 2730: s->cc_op = CC_OP_DYNAMIC;
2731: }
2732: gen_goto_tb(s, tb_num, eip);
1.1 root 2733: s->is_jmp = 3;
2734: } else {
2735: gen_jmp_im(eip);
2736: gen_eob(s);
2737: }
2738: }
2739:
2740: static void gen_jmp(DisasContext *s, target_ulong eip)
2741: {
2742: gen_jmp_tb(s, eip, 0);
2743: }
2744:
1.1.1.7 root 2745: static inline void gen_ldq_env_A0(int idx, int offset)
1.1 root 2746: {
1.1.1.7 root 2747: int mem_index = (idx >> 2) - 1;
2748: tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2749: tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
1.1 root 2750: }
2751:
1.1.1.7 root 2752: static inline void gen_stq_env_A0(int idx, int offset)
1.1 root 2753: {
1.1.1.7 root 2754: int mem_index = (idx >> 2) - 1;
2755: tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2756: tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
1.1 root 2757: }
2758:
1.1.1.7 root 2759: static inline void gen_ldo_env_A0(int idx, int offset)
1.1 root 2760: {
1.1.1.7 root 2761: int mem_index = (idx >> 2) - 1;
2762: tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2763: tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2764: tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2765: tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2766: tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
1.1 root 2767: }
2768:
1.1.1.7 root 2769: static inline void gen_sto_env_A0(int idx, int offset)
2770: {
2771: int mem_index = (idx >> 2) - 1;
2772: tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2773: tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2774: tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2775: tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2776: tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2777: }
1.1 root 2778:
1.1.1.7 root 2779: static inline void gen_op_movo(int d_offset, int s_offset)
2780: {
2781: tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2782: tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2783: tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2784: tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2785: }
1.1 root 2786:
1.1.1.7 root 2787: static inline void gen_op_movq(int d_offset, int s_offset)
2788: {
2789: tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2790: tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2791: }
1.1 root 2792:
1.1.1.7 root 2793: static inline void gen_op_movl(int d_offset, int s_offset)
2794: {
2795: tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2796: tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2797: }
2798:
2799: static inline void gen_op_movq_env_0(int d_offset)
2800: {
2801: tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2802: tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2803: }
1.1 root 2804:
1.1.1.7 root 2805: #define SSE_SPECIAL ((void *)1)
2806: #define SSE_DUMMY ((void *)2)
1.1 root 2807:
1.1.1.7 root 2808: #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2809: #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2810: gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
1.1 root 2811:
1.1.1.7 root 2812: static void *sse_op_table1[256][4] = {
2813: /* 3DNow! extensions */
2814: [0x0e] = { SSE_DUMMY }, /* femms */
2815: [0x0f] = { SSE_DUMMY }, /* pf... */
1.1 root 2816: /* pure SSE operations */
2817: [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2818: [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
1.1.1.3 root 2819: [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
1.1 root 2820: [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
1.1.1.7 root 2821: [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2822: [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
1.1 root 2823: [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2824: [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2825:
2826: [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2827: [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2828: [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
1.1.1.9 root 2829: [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
1.1 root 2830: [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2831: [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
1.1.1.7 root 2832: [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2833: [0x2f] = { gen_helper_comiss, gen_helper_comisd },
1.1 root 2834: [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2835: [0x51] = SSE_FOP(sqrt),
1.1.1.7 root 2836: [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2837: [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2838: [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2839: [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2840: [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2841: [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
1.1 root 2842: [0x58] = SSE_FOP(add),
2843: [0x59] = SSE_FOP(mul),
1.1.1.7 root 2844: [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2845: gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2846: [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
1.1 root 2847: [0x5c] = SSE_FOP(sub),
2848: [0x5d] = SSE_FOP(min),
2849: [0x5e] = SSE_FOP(div),
2850: [0x5f] = SSE_FOP(max),
2851:
2852: [0xc2] = SSE_FOP(cmpeq),
1.1.1.7 root 2853: [0xc6] = { gen_helper_shufps, gen_helper_shufpd },
2854:
2855: [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2856: [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
1.1 root 2857:
2858: /* MMX ops and their SSE extensions */
2859: [0x60] = MMX_OP2(punpcklbw),
2860: [0x61] = MMX_OP2(punpcklwd),
2861: [0x62] = MMX_OP2(punpckldq),
2862: [0x63] = MMX_OP2(packsswb),
2863: [0x64] = MMX_OP2(pcmpgtb),
2864: [0x65] = MMX_OP2(pcmpgtw),
2865: [0x66] = MMX_OP2(pcmpgtl),
2866: [0x67] = MMX_OP2(packuswb),
2867: [0x68] = MMX_OP2(punpckhbw),
2868: [0x69] = MMX_OP2(punpckhwd),
2869: [0x6a] = MMX_OP2(punpckhdq),
2870: [0x6b] = MMX_OP2(packssdw),
1.1.1.7 root 2871: [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2872: [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
1.1 root 2873: [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2874: [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
1.1.1.7 root 2875: [0x70] = { gen_helper_pshufw_mmx,
2876: gen_helper_pshufd_xmm,
2877: gen_helper_pshufhw_xmm,
2878: gen_helper_pshuflw_xmm },
1.1 root 2879: [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2880: [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2881: [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2882: [0x74] = MMX_OP2(pcmpeqb),
2883: [0x75] = MMX_OP2(pcmpeqw),
2884: [0x76] = MMX_OP2(pcmpeql),
1.1.1.7 root 2885: [0x77] = { SSE_DUMMY }, /* emms */
1.1.1.9 root 2886: [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2887: [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
1.1.1.7 root 2888: [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2889: [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
1.1 root 2890: [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2891: [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2892: [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2893: [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
1.1.1.7 root 2894: [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
1.1 root 2895: [0xd1] = MMX_OP2(psrlw),
2896: [0xd2] = MMX_OP2(psrld),
2897: [0xd3] = MMX_OP2(psrlq),
2898: [0xd4] = MMX_OP2(paddq),
2899: [0xd5] = MMX_OP2(pmullw),
2900: [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2901: [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2902: [0xd8] = MMX_OP2(psubusb),
2903: [0xd9] = MMX_OP2(psubusw),
2904: [0xda] = MMX_OP2(pminub),
2905: [0xdb] = MMX_OP2(pand),
2906: [0xdc] = MMX_OP2(paddusb),
2907: [0xdd] = MMX_OP2(paddusw),
2908: [0xde] = MMX_OP2(pmaxub),
2909: [0xdf] = MMX_OP2(pandn),
2910: [0xe0] = MMX_OP2(pavgb),
2911: [0xe1] = MMX_OP2(psraw),
2912: [0xe2] = MMX_OP2(psrad),
2913: [0xe3] = MMX_OP2(pavgw),
2914: [0xe4] = MMX_OP2(pmulhuw),
2915: [0xe5] = MMX_OP2(pmulhw),
1.1.1.7 root 2916: [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
1.1 root 2917: [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2918: [0xe8] = MMX_OP2(psubsb),
2919: [0xe9] = MMX_OP2(psubsw),
2920: [0xea] = MMX_OP2(pminsw),
2921: [0xeb] = MMX_OP2(por),
2922: [0xec] = MMX_OP2(paddsb),
2923: [0xed] = MMX_OP2(paddsw),
2924: [0xee] = MMX_OP2(pmaxsw),
2925: [0xef] = MMX_OP2(pxor),
1.1.1.3 root 2926: [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
1.1 root 2927: [0xf1] = MMX_OP2(psllw),
2928: [0xf2] = MMX_OP2(pslld),
2929: [0xf3] = MMX_OP2(psllq),
2930: [0xf4] = MMX_OP2(pmuludq),
2931: [0xf5] = MMX_OP2(pmaddwd),
2932: [0xf6] = MMX_OP2(psadbw),
2933: [0xf7] = MMX_OP2(maskmov),
2934: [0xf8] = MMX_OP2(psubb),
2935: [0xf9] = MMX_OP2(psubw),
2936: [0xfa] = MMX_OP2(psubl),
2937: [0xfb] = MMX_OP2(psubq),
2938: [0xfc] = MMX_OP2(paddb),
2939: [0xfd] = MMX_OP2(paddw),
2940: [0xfe] = MMX_OP2(paddl),
2941: };
2942:
1.1.1.7 root 2943: static void *sse_op_table2[3 * 8][2] = {
1.1 root 2944: [0 + 2] = MMX_OP2(psrlw),
2945: [0 + 4] = MMX_OP2(psraw),
2946: [0 + 6] = MMX_OP2(psllw),
2947: [8 + 2] = MMX_OP2(psrld),
2948: [8 + 4] = MMX_OP2(psrad),
2949: [8 + 6] = MMX_OP2(pslld),
2950: [16 + 2] = MMX_OP2(psrlq),
1.1.1.7 root 2951: [16 + 3] = { NULL, gen_helper_psrldq_xmm },
1.1 root 2952: [16 + 6] = MMX_OP2(psllq),
1.1.1.7 root 2953: [16 + 7] = { NULL, gen_helper_pslldq_xmm },
1.1 root 2954: };
2955:
1.1.1.7 root 2956: static void *sse_op_table3[4 * 3] = {
2957: gen_helper_cvtsi2ss,
2958: gen_helper_cvtsi2sd,
2959: X86_64_ONLY(gen_helper_cvtsq2ss),
2960: X86_64_ONLY(gen_helper_cvtsq2sd),
2961:
2962: gen_helper_cvttss2si,
2963: gen_helper_cvttsd2si,
2964: X86_64_ONLY(gen_helper_cvttss2sq),
2965: X86_64_ONLY(gen_helper_cvttsd2sq),
2966:
2967: gen_helper_cvtss2si,
2968: gen_helper_cvtsd2si,
2969: X86_64_ONLY(gen_helper_cvtss2sq),
2970: X86_64_ONLY(gen_helper_cvtsd2sq),
1.1 root 2971: };
1.1.1.6 root 2972:
1.1.1.7 root 2973: static void *sse_op_table4[8][4] = {
1.1 root 2974: SSE_FOP(cmpeq),
2975: SSE_FOP(cmplt),
2976: SSE_FOP(cmple),
2977: SSE_FOP(cmpunord),
2978: SSE_FOP(cmpneq),
2979: SSE_FOP(cmpnlt),
2980: SSE_FOP(cmpnle),
2981: SSE_FOP(cmpord),
2982: };
1.1.1.6 root 2983:
1.1.1.7 root 2984: static void *sse_op_table5[256] = {
2985: [0x0c] = gen_helper_pi2fw,
2986: [0x0d] = gen_helper_pi2fd,
2987: [0x1c] = gen_helper_pf2iw,
2988: [0x1d] = gen_helper_pf2id,
2989: [0x8a] = gen_helper_pfnacc,
2990: [0x8e] = gen_helper_pfpnacc,
2991: [0x90] = gen_helper_pfcmpge,
2992: [0x94] = gen_helper_pfmin,
2993: [0x96] = gen_helper_pfrcp,
2994: [0x97] = gen_helper_pfrsqrt,
2995: [0x9a] = gen_helper_pfsub,
2996: [0x9e] = gen_helper_pfadd,
2997: [0xa0] = gen_helper_pfcmpgt,
2998: [0xa4] = gen_helper_pfmax,
2999: [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
3000: [0xa7] = gen_helper_movq, /* pfrsqit1 */
3001: [0xaa] = gen_helper_pfsubr,
3002: [0xae] = gen_helper_pfacc,
3003: [0xb0] = gen_helper_pfcmpeq,
3004: [0xb4] = gen_helper_pfmul,
3005: [0xb6] = gen_helper_movq, /* pfrcpit2 */
3006: [0xb7] = gen_helper_pmulhrw_mmx,
3007: [0xbb] = gen_helper_pswapd,
3008: [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3009: };
3010:
3011: struct sse_op_helper_s {
3012: void *op[2]; uint32_t ext_mask;
3013: };
3014: #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3015: #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3016: #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3017: #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3018: static struct sse_op_helper_s sse_op_table6[256] = {
3019: [0x00] = SSSE3_OP(pshufb),
3020: [0x01] = SSSE3_OP(phaddw),
3021: [0x02] = SSSE3_OP(phaddd),
3022: [0x03] = SSSE3_OP(phaddsw),
3023: [0x04] = SSSE3_OP(pmaddubsw),
3024: [0x05] = SSSE3_OP(phsubw),
3025: [0x06] = SSSE3_OP(phsubd),
3026: [0x07] = SSSE3_OP(phsubsw),
3027: [0x08] = SSSE3_OP(psignb),
3028: [0x09] = SSSE3_OP(psignw),
3029: [0x0a] = SSSE3_OP(psignd),
3030: [0x0b] = SSSE3_OP(pmulhrsw),
3031: [0x10] = SSE41_OP(pblendvb),
3032: [0x14] = SSE41_OP(blendvps),
3033: [0x15] = SSE41_OP(blendvpd),
3034: [0x17] = SSE41_OP(ptest),
3035: [0x1c] = SSSE3_OP(pabsb),
3036: [0x1d] = SSSE3_OP(pabsw),
3037: [0x1e] = SSSE3_OP(pabsd),
3038: [0x20] = SSE41_OP(pmovsxbw),
3039: [0x21] = SSE41_OP(pmovsxbd),
3040: [0x22] = SSE41_OP(pmovsxbq),
3041: [0x23] = SSE41_OP(pmovsxwd),
3042: [0x24] = SSE41_OP(pmovsxwq),
3043: [0x25] = SSE41_OP(pmovsxdq),
3044: [0x28] = SSE41_OP(pmuldq),
3045: [0x29] = SSE41_OP(pcmpeqq),
3046: [0x2a] = SSE41_SPECIAL, /* movntqda */
3047: [0x2b] = SSE41_OP(packusdw),
3048: [0x30] = SSE41_OP(pmovzxbw),
3049: [0x31] = SSE41_OP(pmovzxbd),
3050: [0x32] = SSE41_OP(pmovzxbq),
3051: [0x33] = SSE41_OP(pmovzxwd),
3052: [0x34] = SSE41_OP(pmovzxwq),
3053: [0x35] = SSE41_OP(pmovzxdq),
3054: [0x37] = SSE42_OP(pcmpgtq),
3055: [0x38] = SSE41_OP(pminsb),
3056: [0x39] = SSE41_OP(pminsd),
3057: [0x3a] = SSE41_OP(pminuw),
3058: [0x3b] = SSE41_OP(pminud),
3059: [0x3c] = SSE41_OP(pmaxsb),
3060: [0x3d] = SSE41_OP(pmaxsd),
3061: [0x3e] = SSE41_OP(pmaxuw),
3062: [0x3f] = SSE41_OP(pmaxud),
3063: [0x40] = SSE41_OP(pmulld),
3064: [0x41] = SSE41_OP(phminposuw),
3065: };
3066:
3067: static struct sse_op_helper_s sse_op_table7[256] = {
3068: [0x08] = SSE41_OP(roundps),
3069: [0x09] = SSE41_OP(roundpd),
3070: [0x0a] = SSE41_OP(roundss),
3071: [0x0b] = SSE41_OP(roundsd),
3072: [0x0c] = SSE41_OP(blendps),
3073: [0x0d] = SSE41_OP(blendpd),
3074: [0x0e] = SSE41_OP(pblendw),
3075: [0x0f] = SSSE3_OP(palignr),
3076: [0x14] = SSE41_SPECIAL, /* pextrb */
3077: [0x15] = SSE41_SPECIAL, /* pextrw */
3078: [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3079: [0x17] = SSE41_SPECIAL, /* extractps */
3080: [0x20] = SSE41_SPECIAL, /* pinsrb */
3081: [0x21] = SSE41_SPECIAL, /* insertps */
3082: [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3083: [0x40] = SSE41_OP(dpps),
3084: [0x41] = SSE41_OP(dppd),
3085: [0x42] = SSE41_OP(mpsadbw),
3086: [0x60] = SSE42_OP(pcmpestrm),
3087: [0x61] = SSE42_OP(pcmpestri),
3088: [0x62] = SSE42_OP(pcmpistrm),
3089: [0x63] = SSE42_OP(pcmpistri),
3090: };
3091:
1.1 root 3092: static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3093: {
3094: int b1, op1_offset, op2_offset, is_xmm, val, ot;
3095: int modrm, mod, rm, reg, reg_addr, offset_addr;
1.1.1.7 root 3096: void *sse_op2;
1.1 root 3097:
3098: b &= 0xff;
1.1.1.6 root 3099: if (s->prefix & PREFIX_DATA)
1.1 root 3100: b1 = 1;
1.1.1.6 root 3101: else if (s->prefix & PREFIX_REPZ)
1.1 root 3102: b1 = 2;
1.1.1.6 root 3103: else if (s->prefix & PREFIX_REPNZ)
1.1 root 3104: b1 = 3;
3105: else
3106: b1 = 0;
3107: sse_op2 = sse_op_table1[b][b1];
1.1.1.6 root 3108: if (!sse_op2)
1.1 root 3109: goto illegal_op;
1.1.1.7 root 3110: if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
1.1 root 3111: is_xmm = 1;
3112: } else {
3113: if (b1 == 0) {
3114: /* MMX case */
3115: is_xmm = 0;
3116: } else {
3117: is_xmm = 1;
3118: }
3119: }
3120: /* simple MMX/SSE operation */
3121: if (s->flags & HF_TS_MASK) {
3122: gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3123: return;
3124: }
3125: if (s->flags & HF_EM_MASK) {
3126: illegal_op:
3127: gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3128: return;
3129: }
3130: if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
1.1.1.7 root 3131: if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3132: goto illegal_op;
3133: if (b == 0x0e) {
3134: if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3135: goto illegal_op;
3136: /* femms */
3137: gen_helper_emms();
3138: return;
3139: }
1.1 root 3140: if (b == 0x77) {
3141: /* emms */
1.1.1.7 root 3142: gen_helper_emms();
1.1 root 3143: return;
3144: }
3145: /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3146: the static cpu state) */
3147: if (!is_xmm) {
1.1.1.7 root 3148: gen_helper_enter_mmx();
1.1 root 3149: }
3150:
3151: modrm = ldub_code(s->pc++);
3152: reg = ((modrm >> 3) & 7);
3153: if (is_xmm)
3154: reg |= rex_r;
3155: mod = (modrm >> 6) & 3;
3156: if (sse_op2 == SSE_SPECIAL) {
3157: b |= (b1 << 8);
3158: switch(b) {
3159: case 0x0e7: /* movntq */
1.1.1.6 root 3160: if (mod == 3)
1.1 root 3161: goto illegal_op;
3162: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3163: gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
1.1 root 3164: break;
3165: case 0x1e7: /* movntdq */
3166: case 0x02b: /* movntps */
3167: case 0x12b: /* movntps */
1.1.1.3 root 3168: if (mod == 3)
1.1 root 3169: goto illegal_op;
3170: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3171: gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
1.1 root 3172: break;
1.1.1.11 root 3173: case 0x3f0: /* lddqu */
3174: if (mod == 3)
3175: goto illegal_op;
3176: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3177: gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3178: break;
1.1.1.9 root 3179: case 0x22b: /* movntss */
3180: case 0x32b: /* movntsd */
3181: if (mod == 3)
3182: goto illegal_op;
3183: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3184: if (b1 & 1) {
3185: gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3186: xmm_regs[reg]));
3187: } else {
3188: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3189: xmm_regs[reg].XMM_L(0)));
3190: gen_op_st_T0_A0(OT_LONG + s->mem_index);
3191: }
3192: break;
1.1 root 3193: case 0x6e: /* movd mm, ea */
1.1.1.5 root 3194: #ifdef TARGET_X86_64
3195: if (s->dflag == 2) {
3196: gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
1.1.1.7 root 3197: tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
1.1.1.6 root 3198: } else
1.1.1.5 root 3199: #endif
3200: {
3201: gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
1.1.1.7 root 3202: tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3203: offsetof(CPUX86State,fpregs[reg].mmx));
3204: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3205: gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
1.1.1.5 root 3206: }
1.1 root 3207: break;
3208: case 0x16e: /* movd xmm, ea */
1.1.1.5 root 3209: #ifdef TARGET_X86_64
3210: if (s->dflag == 2) {
3211: gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
1.1.1.7 root 3212: tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3213: offsetof(CPUX86State,xmm_regs[reg]));
3214: gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
1.1.1.6 root 3215: } else
1.1.1.5 root 3216: #endif
3217: {
3218: gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
1.1.1.7 root 3219: tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3220: offsetof(CPUX86State,xmm_regs[reg]));
3221: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3222: gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
1.1.1.5 root 3223: }
1.1 root 3224: break;
3225: case 0x6f: /* movq mm, ea */
3226: if (mod != 3) {
3227: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3228: gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
1.1 root 3229: } else {
3230: rm = (modrm & 7);
1.1.1.7 root 3231: tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3232: offsetof(CPUX86State,fpregs[rm].mmx));
3233: tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3234: offsetof(CPUX86State,fpregs[reg].mmx));
1.1 root 3235: }
3236: break;
3237: case 0x010: /* movups */
3238: case 0x110: /* movupd */
3239: case 0x028: /* movaps */
3240: case 0x128: /* movapd */
3241: case 0x16f: /* movdqa xmm, ea */
3242: case 0x26f: /* movdqu xmm, ea */
3243: if (mod != 3) {
3244: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3245: gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
1.1 root 3246: } else {
3247: rm = (modrm & 7) | REX_B(s);
3248: gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3249: offsetof(CPUX86State,xmm_regs[rm]));
3250: }
3251: break;
3252: case 0x210: /* movss xmm, ea */
3253: if (mod != 3) {
3254: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3255: gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3256: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
1.1 root 3257: gen_op_movl_T0_0();
1.1.1.7 root 3258: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3259: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3260: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
1.1 root 3261: } else {
3262: rm = (modrm & 7) | REX_B(s);
3263: gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3264: offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3265: }
3266: break;
3267: case 0x310: /* movsd xmm, ea */
3268: if (mod != 3) {
3269: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3270: gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
1.1 root 3271: gen_op_movl_T0_0();
1.1.1.7 root 3272: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3273: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
1.1 root 3274: } else {
3275: rm = (modrm & 7) | REX_B(s);
3276: gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3277: offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3278: }
3279: break;
3280: case 0x012: /* movlps */
3281: case 0x112: /* movlpd */
3282: if (mod != 3) {
3283: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3284: gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
1.1 root 3285: } else {
3286: /* movhlps */
3287: rm = (modrm & 7) | REX_B(s);
3288: gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3289: offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3290: }
3291: break;
1.1.1.3 root 3292: case 0x212: /* movsldup */
3293: if (mod != 3) {
3294: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3295: gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
1.1.1.3 root 3296: } else {
3297: rm = (modrm & 7) | REX_B(s);
3298: gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3299: offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3300: gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3301: offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3302: }
3303: gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3304: offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3305: gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3306: offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3307: break;
3308: case 0x312: /* movddup */
3309: if (mod != 3) {
3310: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3311: gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
1.1.1.3 root 3312: } else {
3313: rm = (modrm & 7) | REX_B(s);
3314: gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3315: offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3316: }
3317: gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3318: offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3319: break;
1.1 root 3320: case 0x016: /* movhps */
3321: case 0x116: /* movhpd */
3322: if (mod != 3) {
3323: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3324: gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
1.1 root 3325: } else {
3326: /* movlhps */
3327: rm = (modrm & 7) | REX_B(s);
3328: gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3329: offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3330: }
3331: break;
3332: case 0x216: /* movshdup */
3333: if (mod != 3) {
3334: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3335: gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
1.1 root 3336: } else {
3337: rm = (modrm & 7) | REX_B(s);
3338: gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3339: offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3340: gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3341: offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3342: }
3343: gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3344: offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3345: gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3346: offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3347: break;
1.1.1.9 root 3348: case 0x178:
3349: case 0x378:
3350: {
3351: int bit_index, field_length;
3352:
3353: if (b1 == 1 && reg != 0)
3354: goto illegal_op;
3355: field_length = ldub_code(s->pc++) & 0x3F;
3356: bit_index = ldub_code(s->pc++) & 0x3F;
3357: tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3358: offsetof(CPUX86State,xmm_regs[reg]));
3359: if (b1 == 1)
3360: gen_helper_extrq_i(cpu_ptr0, tcg_const_i32(bit_index),
3361: tcg_const_i32(field_length));
3362: else
3363: gen_helper_insertq_i(cpu_ptr0, tcg_const_i32(bit_index),
3364: tcg_const_i32(field_length));
3365: }
3366: break;
1.1 root 3367: case 0x7e: /* movd ea, mm */
1.1.1.5 root 3368: #ifdef TARGET_X86_64
3369: if (s->dflag == 2) {
1.1.1.7 root 3370: tcg_gen_ld_i64(cpu_T[0], cpu_env,
3371: offsetof(CPUX86State,fpregs[reg].mmx));
1.1.1.5 root 3372: gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
1.1.1.6 root 3373: } else
1.1.1.5 root 3374: #endif
3375: {
1.1.1.7 root 3376: tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3377: offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
1.1.1.5 root 3378: gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3379: }
1.1 root 3380: break;
3381: case 0x17e: /* movd ea, xmm */
1.1.1.5 root 3382: #ifdef TARGET_X86_64
3383: if (s->dflag == 2) {
1.1.1.7 root 3384: tcg_gen_ld_i64(cpu_T[0], cpu_env,
3385: offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
1.1.1.5 root 3386: gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
1.1.1.6 root 3387: } else
1.1.1.5 root 3388: #endif
3389: {
1.1.1.7 root 3390: tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3391: offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
1.1.1.5 root 3392: gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3393: }
1.1 root 3394: break;
3395: case 0x27e: /* movq xmm, ea */
3396: if (mod != 3) {
3397: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3398: gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
1.1 root 3399: } else {
3400: rm = (modrm & 7) | REX_B(s);
3401: gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3402: offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3403: }
3404: gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3405: break;
3406: case 0x7f: /* movq ea, mm */
3407: if (mod != 3) {
3408: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3409: gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
1.1 root 3410: } else {
3411: rm = (modrm & 7);
3412: gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3413: offsetof(CPUX86State,fpregs[reg].mmx));
3414: }
3415: break;
3416: case 0x011: /* movups */
3417: case 0x111: /* movupd */
3418: case 0x029: /* movaps */
3419: case 0x129: /* movapd */
3420: case 0x17f: /* movdqa ea, xmm */
3421: case 0x27f: /* movdqu ea, xmm */
3422: if (mod != 3) {
3423: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3424: gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
1.1 root 3425: } else {
3426: rm = (modrm & 7) | REX_B(s);
3427: gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3428: offsetof(CPUX86State,xmm_regs[reg]));
3429: }
3430: break;
3431: case 0x211: /* movss ea, xmm */
3432: if (mod != 3) {
3433: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3434: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3435: gen_op_st_T0_A0(OT_LONG + s->mem_index);
1.1 root 3436: } else {
3437: rm = (modrm & 7) | REX_B(s);
3438: gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3439: offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3440: }
3441: break;
3442: case 0x311: /* movsd ea, xmm */
3443: if (mod != 3) {
3444: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3445: gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
1.1 root 3446: } else {
3447: rm = (modrm & 7) | REX_B(s);
3448: gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3449: offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3450: }
3451: break;
3452: case 0x013: /* movlps */
3453: case 0x113: /* movlpd */
3454: if (mod != 3) {
3455: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3456: gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
1.1 root 3457: } else {
3458: goto illegal_op;
3459: }
3460: break;
3461: case 0x017: /* movhps */
3462: case 0x117: /* movhpd */
3463: if (mod != 3) {
3464: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3465: gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
1.1 root 3466: } else {
3467: goto illegal_op;
3468: }
3469: break;
3470: case 0x71: /* shift mm, im */
3471: case 0x72:
3472: case 0x73:
3473: case 0x171: /* shift xmm, im */
3474: case 0x172:
3475: case 0x173:
3476: val = ldub_code(s->pc++);
3477: if (is_xmm) {
3478: gen_op_movl_T0_im(val);
1.1.1.7 root 3479: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
1.1 root 3480: gen_op_movl_T0_0();
1.1.1.7 root 3481: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
1.1 root 3482: op1_offset = offsetof(CPUX86State,xmm_t0);
3483: } else {
3484: gen_op_movl_T0_im(val);
1.1.1.7 root 3485: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
1.1 root 3486: gen_op_movl_T0_0();
1.1.1.7 root 3487: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
1.1 root 3488: op1_offset = offsetof(CPUX86State,mmx_t0);
3489: }
3490: sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3491: if (!sse_op2)
3492: goto illegal_op;
3493: if (is_xmm) {
3494: rm = (modrm & 7) | REX_B(s);
3495: op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3496: } else {
3497: rm = (modrm & 7);
3498: op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3499: }
1.1.1.7 root 3500: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3501: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3502: ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
1.1 root 3503: break;
3504: case 0x050: /* movmskps */
3505: rm = (modrm & 7) | REX_B(s);
1.1.1.7 root 3506: tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3507: offsetof(CPUX86State,xmm_regs[rm]));
3508: gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0);
3509: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3510: gen_op_mov_reg_T0(OT_LONG, reg);
1.1 root 3511: break;
3512: case 0x150: /* movmskpd */
3513: rm = (modrm & 7) | REX_B(s);
1.1.1.7 root 3514: tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3515: offsetof(CPUX86State,xmm_regs[rm]));
3516: gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0);
3517: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3518: gen_op_mov_reg_T0(OT_LONG, reg);
1.1 root 3519: break;
3520: case 0x02a: /* cvtpi2ps */
3521: case 0x12a: /* cvtpi2pd */
1.1.1.7 root 3522: gen_helper_enter_mmx();
1.1 root 3523: if (mod != 3) {
3524: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3525: op2_offset = offsetof(CPUX86State,mmx_t0);
1.1.1.7 root 3526: gen_ldq_env_A0(s->mem_index, op2_offset);
1.1 root 3527: } else {
3528: rm = (modrm & 7);
3529: op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3530: }
3531: op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
1.1.1.7 root 3532: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3533: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
1.1 root 3534: switch(b >> 8) {
3535: case 0x0:
1.1.1.7 root 3536: gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1);
1.1 root 3537: break;
3538: default:
3539: case 0x1:
1.1.1.7 root 3540: gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1);
1.1 root 3541: break;
3542: }
3543: break;
3544: case 0x22a: /* cvtsi2ss */
3545: case 0x32a: /* cvtsi2sd */
3546: ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3547: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3548: op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
1.1.1.7 root 3549: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3550: sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3551: if (ot == OT_LONG) {
3552: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3553: ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32);
3554: } else {
3555: ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]);
3556: }
1.1 root 3557: break;
3558: case 0x02c: /* cvttps2pi */
3559: case 0x12c: /* cvttpd2pi */
3560: case 0x02d: /* cvtps2pi */
3561: case 0x12d: /* cvtpd2pi */
1.1.1.7 root 3562: gen_helper_enter_mmx();
1.1 root 3563: if (mod != 3) {
3564: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3565: op2_offset = offsetof(CPUX86State,xmm_t0);
1.1.1.7 root 3566: gen_ldo_env_A0(s->mem_index, op2_offset);
1.1 root 3567: } else {
3568: rm = (modrm & 7) | REX_B(s);
3569: op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3570: }
3571: op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
1.1.1.7 root 3572: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3573: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
1.1 root 3574: switch(b) {
3575: case 0x02c:
1.1.1.7 root 3576: gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1);
1.1 root 3577: break;
3578: case 0x12c:
1.1.1.7 root 3579: gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1);
1.1 root 3580: break;
3581: case 0x02d:
1.1.1.7 root 3582: gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1);
1.1 root 3583: break;
3584: case 0x12d:
1.1.1.7 root 3585: gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1);
1.1 root 3586: break;
3587: }
3588: break;
3589: case 0x22c: /* cvttss2si */
3590: case 0x32c: /* cvttsd2si */
3591: case 0x22d: /* cvtss2si */
3592: case 0x32d: /* cvtsd2si */
3593: ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3594: if (mod != 3) {
3595: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3596: if ((b >> 8) & 1) {
1.1.1.7 root 3597: gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
1.1 root 3598: } else {
1.1.1.7 root 3599: gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3600: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
1.1 root 3601: }
3602: op2_offset = offsetof(CPUX86State,xmm_t0);
3603: } else {
3604: rm = (modrm & 7) | REX_B(s);
3605: op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3606: }
1.1.1.7 root 3607: sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3608: (b & 1) * 4];
3609: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3610: if (ot == OT_LONG) {
3611: ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0);
3612: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3613: } else {
3614: ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0);
3615: }
3616: gen_op_mov_reg_T0(ot, reg);
1.1 root 3617: break;
3618: case 0xc4: /* pinsrw */
1.1.1.6 root 3619: case 0x1c4:
1.1.1.4 root 3620: s->rip_offset = 1;
1.1 root 3621: gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3622: val = ldub_code(s->pc++);
3623: if (b1) {
3624: val &= 7;
1.1.1.7 root 3625: tcg_gen_st16_tl(cpu_T[0], cpu_env,
3626: offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
1.1 root 3627: } else {
3628: val &= 3;
1.1.1.7 root 3629: tcg_gen_st16_tl(cpu_T[0], cpu_env,
3630: offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
1.1 root 3631: }
3632: break;
3633: case 0xc5: /* pextrw */
1.1.1.6 root 3634: case 0x1c5:
1.1 root 3635: if (mod != 3)
3636: goto illegal_op;
1.1.1.7 root 3637: ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
1.1 root 3638: val = ldub_code(s->pc++);
3639: if (b1) {
3640: val &= 7;
3641: rm = (modrm & 7) | REX_B(s);
1.1.1.7 root 3642: tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3643: offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
1.1 root 3644: } else {
3645: val &= 3;
3646: rm = (modrm & 7);
1.1.1.7 root 3647: tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3648: offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
1.1 root 3649: }
3650: reg = ((modrm >> 3) & 7) | rex_r;
1.1.1.7 root 3651: gen_op_mov_reg_T0(ot, reg);
1.1 root 3652: break;
3653: case 0x1d6: /* movq ea, xmm */
3654: if (mod != 3) {
3655: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 3656: gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
1.1 root 3657: } else {
3658: rm = (modrm & 7) | REX_B(s);
3659: gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3660: offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3661: gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3662: }
3663: break;
3664: case 0x2d6: /* movq2dq */
1.1.1.7 root 3665: gen_helper_enter_mmx();
1.1.1.4 root 3666: rm = (modrm & 7);
3667: gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3668: offsetof(CPUX86State,fpregs[rm].mmx));
3669: gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
1.1 root 3670: break;
3671: case 0x3d6: /* movdq2q */
1.1.1.7 root 3672: gen_helper_enter_mmx();
1.1.1.4 root 3673: rm = (modrm & 7) | REX_B(s);
3674: gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3675: offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
1.1 root 3676: break;
3677: case 0xd7: /* pmovmskb */
3678: case 0x1d7:
3679: if (mod != 3)
3680: goto illegal_op;
3681: if (b1) {
3682: rm = (modrm & 7) | REX_B(s);
1.1.1.7 root 3683: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3684: gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0);
1.1 root 3685: } else {
3686: rm = (modrm & 7);
1.1.1.7 root 3687: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3688: gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0);
3689: }
3690: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3691: reg = ((modrm >> 3) & 7) | rex_r;
3692: gen_op_mov_reg_T0(OT_LONG, reg);
3693: break;
3694: case 0x138:
3695: if (s->prefix & PREFIX_REPNZ)
3696: goto crc32;
3697: case 0x038:
3698: b = modrm;
3699: modrm = ldub_code(s->pc++);
3700: rm = modrm & 7;
3701: reg = ((modrm >> 3) & 7) | rex_r;
3702: mod = (modrm >> 6) & 3;
3703:
3704: sse_op2 = sse_op_table6[b].op[b1];
3705: if (!sse_op2)
3706: goto illegal_op;
3707: if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3708: goto illegal_op;
3709:
3710: if (b1) {
3711: op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3712: if (mod == 3) {
3713: op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3714: } else {
3715: op2_offset = offsetof(CPUX86State,xmm_t0);
3716: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3717: switch (b) {
3718: case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3719: case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3720: case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3721: gen_ldq_env_A0(s->mem_index, op2_offset +
3722: offsetof(XMMReg, XMM_Q(0)));
3723: break;
3724: case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3725: case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3726: tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3727: (s->mem_index >> 2) - 1);
3728: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3729: tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3730: offsetof(XMMReg, XMM_L(0)));
3731: break;
3732: case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3733: tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3734: (s->mem_index >> 2) - 1);
3735: tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3736: offsetof(XMMReg, XMM_W(0)));
3737: break;
3738: case 0x2a: /* movntqda */
3739: gen_ldo_env_A0(s->mem_index, op1_offset);
3740: return;
3741: default:
3742: gen_ldo_env_A0(s->mem_index, op2_offset);
3743: }
3744: }
3745: } else {
3746: op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3747: if (mod == 3) {
3748: op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3749: } else {
3750: op2_offset = offsetof(CPUX86State,mmx_t0);
3751: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3752: gen_ldq_env_A0(s->mem_index, op2_offset);
3753: }
1.1 root 3754: }
1.1.1.7 root 3755: if (sse_op2 == SSE_SPECIAL)
3756: goto illegal_op;
3757:
3758: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3759: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3760: ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3761:
3762: if (b == 0x17)
3763: s->cc_op = CC_OP_EFLAGS;
3764: break;
3765: case 0x338: /* crc32 */
3766: crc32:
3767: b = modrm;
3768: modrm = ldub_code(s->pc++);
3769: reg = ((modrm >> 3) & 7) | rex_r;
3770:
3771: if (b != 0xf0 && b != 0xf1)
3772: goto illegal_op;
3773: if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3774: goto illegal_op;
3775:
3776: if (b == 0xf0)
3777: ot = OT_BYTE;
3778: else if (b == 0xf1 && s->dflag != 2)
3779: if (s->prefix & PREFIX_DATA)
3780: ot = OT_WORD;
3781: else
3782: ot = OT_LONG;
3783: else
3784: ot = OT_QUAD;
3785:
3786: gen_op_mov_TN_reg(OT_LONG, 0, reg);
3787: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3788: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3789: gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3790: cpu_T[0], tcg_const_i32(8 << ot));
3791:
3792: ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3793: gen_op_mov_reg_T0(ot, reg);
3794: break;
3795: case 0x03a:
3796: case 0x13a:
3797: b = modrm;
3798: modrm = ldub_code(s->pc++);
3799: rm = modrm & 7;
1.1 root 3800: reg = ((modrm >> 3) & 7) | rex_r;
1.1.1.7 root 3801: mod = (modrm >> 6) & 3;
3802:
3803: sse_op2 = sse_op_table7[b].op[b1];
3804: if (!sse_op2)
3805: goto illegal_op;
3806: if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3807: goto illegal_op;
3808:
3809: if (sse_op2 == SSE_SPECIAL) {
3810: ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3811: rm = (modrm & 7) | REX_B(s);
3812: if (mod != 3)
3813: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3814: reg = ((modrm >> 3) & 7) | rex_r;
3815: val = ldub_code(s->pc++);
3816: switch (b) {
3817: case 0x14: /* pextrb */
3818: tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3819: xmm_regs[reg].XMM_B(val & 15)));
3820: if (mod == 3)
3821: gen_op_mov_reg_T0(ot, rm);
3822: else
3823: tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3824: (s->mem_index >> 2) - 1);
3825: break;
3826: case 0x15: /* pextrw */
3827: tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3828: xmm_regs[reg].XMM_W(val & 7)));
3829: if (mod == 3)
3830: gen_op_mov_reg_T0(ot, rm);
3831: else
3832: tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3833: (s->mem_index >> 2) - 1);
3834: break;
3835: case 0x16:
3836: if (ot == OT_LONG) { /* pextrd */
3837: tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3838: offsetof(CPUX86State,
3839: xmm_regs[reg].XMM_L(val & 3)));
3840: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3841: if (mod == 3)
3842: gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3843: else
3844: tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3845: (s->mem_index >> 2) - 1);
3846: } else { /* pextrq */
3847: #ifdef TARGET_X86_64
3848: tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3849: offsetof(CPUX86State,
3850: xmm_regs[reg].XMM_Q(val & 1)));
3851: if (mod == 3)
3852: gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3853: else
3854: tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3855: (s->mem_index >> 2) - 1);
3856: #else
3857: goto illegal_op;
3858: #endif
3859: }
3860: break;
3861: case 0x17: /* extractps */
3862: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3863: xmm_regs[reg].XMM_L(val & 3)));
3864: if (mod == 3)
3865: gen_op_mov_reg_T0(ot, rm);
3866: else
3867: tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3868: (s->mem_index >> 2) - 1);
3869: break;
3870: case 0x20: /* pinsrb */
3871: if (mod == 3)
3872: gen_op_mov_TN_reg(OT_LONG, 0, rm);
3873: else
3874: tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3875: (s->mem_index >> 2) - 1);
3876: tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3877: xmm_regs[reg].XMM_B(val & 15)));
3878: break;
3879: case 0x21: /* insertps */
3880: if (mod == 3) {
3881: tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3882: offsetof(CPUX86State,xmm_regs[rm]
3883: .XMM_L((val >> 6) & 3)));
3884: } else {
3885: tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3886: (s->mem_index >> 2) - 1);
3887: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3888: }
3889: tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3890: offsetof(CPUX86State,xmm_regs[reg]
3891: .XMM_L((val >> 4) & 3)));
3892: if ((val >> 0) & 1)
3893: tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3894: cpu_env, offsetof(CPUX86State,
3895: xmm_regs[reg].XMM_L(0)));
3896: if ((val >> 1) & 1)
3897: tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3898: cpu_env, offsetof(CPUX86State,
3899: xmm_regs[reg].XMM_L(1)));
3900: if ((val >> 2) & 1)
3901: tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3902: cpu_env, offsetof(CPUX86State,
3903: xmm_regs[reg].XMM_L(2)));
3904: if ((val >> 3) & 1)
3905: tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3906: cpu_env, offsetof(CPUX86State,
3907: xmm_regs[reg].XMM_L(3)));
3908: break;
3909: case 0x22:
3910: if (ot == OT_LONG) { /* pinsrd */
3911: if (mod == 3)
3912: gen_op_mov_v_reg(ot, cpu_tmp0, rm);
3913: else
3914: tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3915: (s->mem_index >> 2) - 1);
3916: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3917: tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3918: offsetof(CPUX86State,
3919: xmm_regs[reg].XMM_L(val & 3)));
3920: } else { /* pinsrq */
3921: #ifdef TARGET_X86_64
3922: if (mod == 3)
3923: gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3924: else
3925: tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3926: (s->mem_index >> 2) - 1);
3927: tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3928: offsetof(CPUX86State,
3929: xmm_regs[reg].XMM_Q(val & 1)));
3930: #else
3931: goto illegal_op;
3932: #endif
3933: }
3934: break;
3935: }
3936: return;
3937: }
3938:
3939: if (b1) {
3940: op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3941: if (mod == 3) {
3942: op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3943: } else {
3944: op2_offset = offsetof(CPUX86State,xmm_t0);
3945: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3946: gen_ldo_env_A0(s->mem_index, op2_offset);
3947: }
3948: } else {
3949: op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3950: if (mod == 3) {
3951: op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3952: } else {
3953: op2_offset = offsetof(CPUX86State,mmx_t0);
3954: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3955: gen_ldq_env_A0(s->mem_index, op2_offset);
3956: }
3957: }
3958: val = ldub_code(s->pc++);
3959:
3960: if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
3961: s->cc_op = CC_OP_EFLAGS;
3962:
3963: if (s->dflag == 2)
3964: /* The helper must use entire 64-bit gp registers */
3965: val |= 1 << 8;
3966: }
3967:
3968: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3969: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3970: ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
1.1 root 3971: break;
3972: default:
3973: goto illegal_op;
3974: }
3975: } else {
3976: /* generic MMX or SSE operation */
1.1.1.4 root 3977: switch(b) {
3978: case 0x70: /* pshufx insn */
3979: case 0xc6: /* pshufx insn */
3980: case 0xc2: /* compare insns */
3981: s->rip_offset = 1;
3982: break;
3983: default:
3984: break;
1.1 root 3985: }
3986: if (is_xmm) {
3987: op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3988: if (mod != 3) {
3989: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3990: op2_offset = offsetof(CPUX86State,xmm_t0);
1.1.1.4 root 3991: if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
1.1 root 3992: b == 0xc2)) {
3993: /* specific case for SSE single instructions */
3994: if (b1 == 2) {
3995: /* 32 bit access */
1.1.1.7 root 3996: gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3997: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
1.1 root 3998: } else {
3999: /* 64 bit access */
1.1.1.7 root 4000: gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
1.1 root 4001: }
4002: } else {
1.1.1.7 root 4003: gen_ldo_env_A0(s->mem_index, op2_offset);
1.1 root 4004: }
4005: } else {
4006: rm = (modrm & 7) | REX_B(s);
4007: op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4008: }
4009: } else {
4010: op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4011: if (mod != 3) {
4012: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4013: op2_offset = offsetof(CPUX86State,mmx_t0);
1.1.1.7 root 4014: gen_ldq_env_A0(s->mem_index, op2_offset);
1.1 root 4015: } else {
4016: rm = (modrm & 7);
4017: op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4018: }
4019: }
4020: switch(b) {
1.1.1.7 root 4021: case 0x0f: /* 3DNow! data insns */
4022: if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4023: goto illegal_op;
4024: val = ldub_code(s->pc++);
4025: sse_op2 = sse_op_table5[val];
4026: if (!sse_op2)
4027: goto illegal_op;
4028: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4029: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4030: ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4031: break;
1.1 root 4032: case 0x70: /* pshufx insn */
4033: case 0xc6: /* pshufx insn */
4034: val = ldub_code(s->pc++);
1.1.1.7 root 4035: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4036: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4037: ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
1.1 root 4038: break;
4039: case 0xc2:
4040: /* compare insns */
4041: val = ldub_code(s->pc++);
4042: if (val >= 8)
4043: goto illegal_op;
4044: sse_op2 = sse_op_table4[val][b1];
1.1.1.7 root 4045: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4046: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4047: ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4048: break;
4049: case 0xf7:
4050: /* maskmov : we must prepare A0 */
4051: if (mod != 3)
4052: goto illegal_op;
4053: #ifdef TARGET_X86_64
4054: if (s->aflag == 2) {
4055: gen_op_movq_A0_reg(R_EDI);
4056: } else
4057: #endif
4058: {
4059: gen_op_movl_A0_reg(R_EDI);
4060: if (s->aflag == 0)
4061: gen_op_andl_A0_ffff();
4062: }
4063: gen_add_A0_ds_seg(s);
4064:
4065: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4066: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4067: ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0);
1.1 root 4068: break;
4069: default:
1.1.1.7 root 4070: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4071: tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4072: ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
1.1 root 4073: break;
4074: }
4075: if (b == 0x2e || b == 0x2f) {
4076: s->cc_op = CC_OP_EFLAGS;
4077: }
4078: }
4079: }
4080:
4081: /* convert one instruction. s->is_jmp is set if the translation must
4082: be stopped. Return the next pc value */
4083: static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4084: {
4085: int b, prefixes, aflag, dflag;
4086: int shift, ot;
4087: int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4088: target_ulong next_eip, tval;
4089: int rex_w, rex_r;
4090:
1.1.1.7 root 4091: if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
4092: tcg_gen_debug_insn_start(pc_start);
1.1 root 4093: s->pc = pc_start;
4094: prefixes = 0;
4095: aflag = s->code32;
4096: dflag = s->code32;
4097: s->override = -1;
4098: rex_w = -1;
4099: rex_r = 0;
4100: #ifdef TARGET_X86_64
4101: s->rex_x = 0;
4102: s->rex_b = 0;
1.1.1.6 root 4103: x86_64_hregs = 0;
1.1 root 4104: #endif
4105: s->rip_offset = 0; /* for relative ip address */
4106: next_byte:
4107: b = ldub_code(s->pc);
4108: s->pc++;
4109: /* check prefixes */
4110: #ifdef TARGET_X86_64
4111: if (CODE64(s)) {
4112: switch (b) {
4113: case 0xf3:
4114: prefixes |= PREFIX_REPZ;
4115: goto next_byte;
4116: case 0xf2:
4117: prefixes |= PREFIX_REPNZ;
4118: goto next_byte;
4119: case 0xf0:
4120: prefixes |= PREFIX_LOCK;
4121: goto next_byte;
4122: case 0x2e:
4123: s->override = R_CS;
4124: goto next_byte;
4125: case 0x36:
4126: s->override = R_SS;
4127: goto next_byte;
4128: case 0x3e:
4129: s->override = R_DS;
4130: goto next_byte;
4131: case 0x26:
4132: s->override = R_ES;
4133: goto next_byte;
4134: case 0x64:
4135: s->override = R_FS;
4136: goto next_byte;
4137: case 0x65:
4138: s->override = R_GS;
4139: goto next_byte;
4140: case 0x66:
4141: prefixes |= PREFIX_DATA;
4142: goto next_byte;
4143: case 0x67:
4144: prefixes |= PREFIX_ADR;
4145: goto next_byte;
4146: case 0x40 ... 0x4f:
4147: /* REX prefix */
4148: rex_w = (b >> 3) & 1;
4149: rex_r = (b & 0x4) << 1;
4150: s->rex_x = (b & 0x2) << 2;
4151: REX_B(s) = (b & 0x1) << 3;
4152: x86_64_hregs = 1; /* select uniform byte register addressing */
4153: goto next_byte;
4154: }
4155: if (rex_w == 1) {
4156: /* 0x66 is ignored if rex.w is set */
4157: dflag = 2;
4158: } else {
4159: if (prefixes & PREFIX_DATA)
4160: dflag ^= 1;
4161: }
4162: if (!(prefixes & PREFIX_ADR))
4163: aflag = 2;
1.1.1.6 root 4164: } else
1.1 root 4165: #endif
4166: {
4167: switch (b) {
4168: case 0xf3:
4169: prefixes |= PREFIX_REPZ;
4170: goto next_byte;
4171: case 0xf2:
4172: prefixes |= PREFIX_REPNZ;
4173: goto next_byte;
4174: case 0xf0:
4175: prefixes |= PREFIX_LOCK;
4176: goto next_byte;
4177: case 0x2e:
4178: s->override = R_CS;
4179: goto next_byte;
4180: case 0x36:
4181: s->override = R_SS;
4182: goto next_byte;
4183: case 0x3e:
4184: s->override = R_DS;
4185: goto next_byte;
4186: case 0x26:
4187: s->override = R_ES;
4188: goto next_byte;
4189: case 0x64:
4190: s->override = R_FS;
4191: goto next_byte;
4192: case 0x65:
4193: s->override = R_GS;
4194: goto next_byte;
4195: case 0x66:
4196: prefixes |= PREFIX_DATA;
4197: goto next_byte;
4198: case 0x67:
4199: prefixes |= PREFIX_ADR;
4200: goto next_byte;
4201: }
4202: if (prefixes & PREFIX_DATA)
4203: dflag ^= 1;
4204: if (prefixes & PREFIX_ADR)
4205: aflag ^= 1;
4206: }
4207:
4208: s->prefix = prefixes;
4209: s->aflag = aflag;
4210: s->dflag = dflag;
4211:
4212: /* lock generation */
4213: if (prefixes & PREFIX_LOCK)
1.1.1.7 root 4214: gen_helper_lock();
1.1 root 4215:
4216: /* now check op code */
4217: reswitch:
4218: switch(b) {
4219: case 0x0f:
4220: /**************************/
4221: /* extended op code */
4222: b = ldub_code(s->pc++) | 0x100;
4223: goto reswitch;
1.1.1.6 root 4224:
1.1 root 4225: /**************************/
4226: /* arith & logic */
4227: case 0x00 ... 0x05:
4228: case 0x08 ... 0x0d:
4229: case 0x10 ... 0x15:
4230: case 0x18 ... 0x1d:
4231: case 0x20 ... 0x25:
4232: case 0x28 ... 0x2d:
4233: case 0x30 ... 0x35:
4234: case 0x38 ... 0x3d:
4235: {
4236: int op, f, val;
4237: op = (b >> 3) & 7;
4238: f = (b >> 1) & 3;
4239:
4240: if ((b & 1) == 0)
4241: ot = OT_BYTE;
4242: else
4243: ot = dflag + OT_WORD;
1.1.1.6 root 4244:
1.1 root 4245: switch(f) {
4246: case 0: /* OP Ev, Gv */
4247: modrm = ldub_code(s->pc++);
4248: reg = ((modrm >> 3) & 7) | rex_r;
4249: mod = (modrm >> 6) & 3;
4250: rm = (modrm & 7) | REX_B(s);
4251: if (mod != 3) {
4252: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4253: opreg = OR_TMP0;
4254: } else if (op == OP_XORL && rm == reg) {
4255: xor_zero:
4256: /* xor reg, reg optimisation */
4257: gen_op_movl_T0_0();
4258: s->cc_op = CC_OP_LOGICB + ot;
1.1.1.7 root 4259: gen_op_mov_reg_T0(ot, reg);
1.1 root 4260: gen_op_update1_cc();
4261: break;
4262: } else {
4263: opreg = rm;
4264: }
1.1.1.7 root 4265: gen_op_mov_TN_reg(ot, 1, reg);
1.1 root 4266: gen_op(s, op, ot, opreg);
4267: break;
4268: case 1: /* OP Gv, Ev */
4269: modrm = ldub_code(s->pc++);
4270: mod = (modrm >> 6) & 3;
4271: reg = ((modrm >> 3) & 7) | rex_r;
4272: rm = (modrm & 7) | REX_B(s);
4273: if (mod != 3) {
4274: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 4275: gen_op_ld_T1_A0(ot + s->mem_index);
1.1 root 4276: } else if (op == OP_XORL && rm == reg) {
4277: goto xor_zero;
4278: } else {
1.1.1.7 root 4279: gen_op_mov_TN_reg(ot, 1, rm);
1.1 root 4280: }
4281: gen_op(s, op, ot, reg);
4282: break;
4283: case 2: /* OP A, Iv */
4284: val = insn_get(s, ot);
4285: gen_op_movl_T1_im(val);
4286: gen_op(s, op, ot, OR_EAX);
4287: break;
4288: }
4289: }
4290: break;
4291:
1.1.1.7 root 4292: case 0x82:
4293: if (CODE64(s))
4294: goto illegal_op;
1.1 root 4295: case 0x80: /* GRP1 */
4296: case 0x81:
4297: case 0x83:
4298: {
4299: int val;
4300:
4301: if ((b & 1) == 0)
4302: ot = OT_BYTE;
4303: else
4304: ot = dflag + OT_WORD;
1.1.1.6 root 4305:
1.1 root 4306: modrm = ldub_code(s->pc++);
4307: mod = (modrm >> 6) & 3;
4308: rm = (modrm & 7) | REX_B(s);
4309: op = (modrm >> 3) & 7;
1.1.1.6 root 4310:
1.1 root 4311: if (mod != 3) {
4312: if (b == 0x83)
4313: s->rip_offset = 1;
4314: else
4315: s->rip_offset = insn_const_size(ot);
4316: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4317: opreg = OR_TMP0;
4318: } else {
4319: opreg = rm;
4320: }
4321:
4322: switch(b) {
4323: default:
4324: case 0x80:
4325: case 0x81:
4326: case 0x82:
4327: val = insn_get(s, ot);
4328: break;
4329: case 0x83:
4330: val = (int8_t)insn_get(s, OT_BYTE);
4331: break;
4332: }
4333: gen_op_movl_T1_im(val);
4334: gen_op(s, op, ot, opreg);
4335: }
4336: break;
4337:
4338: /**************************/
4339: /* inc, dec, and other misc arith */
4340: case 0x40 ... 0x47: /* inc Gv */
4341: ot = dflag ? OT_LONG : OT_WORD;
4342: gen_inc(s, ot, OR_EAX + (b & 7), 1);
4343: break;
4344: case 0x48 ... 0x4f: /* dec Gv */
4345: ot = dflag ? OT_LONG : OT_WORD;
4346: gen_inc(s, ot, OR_EAX + (b & 7), -1);
4347: break;
4348: case 0xf6: /* GRP3 */
4349: case 0xf7:
4350: if ((b & 1) == 0)
4351: ot = OT_BYTE;
4352: else
4353: ot = dflag + OT_WORD;
4354:
4355: modrm = ldub_code(s->pc++);
4356: mod = (modrm >> 6) & 3;
4357: rm = (modrm & 7) | REX_B(s);
4358: op = (modrm >> 3) & 7;
4359: if (mod != 3) {
4360: if (op == 0)
4361: s->rip_offset = insn_const_size(ot);
4362: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 4363: gen_op_ld_T0_A0(ot + s->mem_index);
1.1 root 4364: } else {
1.1.1.7 root 4365: gen_op_mov_TN_reg(ot, 0, rm);
1.1 root 4366: }
4367:
4368: switch(op) {
4369: case 0: /* test */
4370: val = insn_get(s, ot);
4371: gen_op_movl_T1_im(val);
4372: gen_op_testl_T0_T1_cc();
4373: s->cc_op = CC_OP_LOGICB + ot;
4374: break;
4375: case 2: /* not */
1.1.1.7 root 4376: tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
1.1 root 4377: if (mod != 3) {
1.1.1.7 root 4378: gen_op_st_T0_A0(ot + s->mem_index);
1.1 root 4379: } else {
1.1.1.7 root 4380: gen_op_mov_reg_T0(ot, rm);
1.1 root 4381: }
4382: break;
4383: case 3: /* neg */
1.1.1.7 root 4384: tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
1.1 root 4385: if (mod != 3) {
1.1.1.7 root 4386: gen_op_st_T0_A0(ot + s->mem_index);
1.1 root 4387: } else {
1.1.1.7 root 4388: gen_op_mov_reg_T0(ot, rm);
1.1 root 4389: }
4390: gen_op_update_neg_cc();
4391: s->cc_op = CC_OP_SUBB + ot;
4392: break;
4393: case 4: /* mul */
4394: switch(ot) {
4395: case OT_BYTE:
1.1.1.7 root 4396: gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4397: tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4398: tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4399: /* XXX: use 32 bit mul which could be faster */
4400: tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4401: gen_op_mov_reg_T0(OT_WORD, R_EAX);
4402: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4403: tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
1.1 root 4404: s->cc_op = CC_OP_MULB;
4405: break;
4406: case OT_WORD:
1.1.1.7 root 4407: gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4408: tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4409: tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4410: /* XXX: use 32 bit mul which could be faster */
4411: tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4412: gen_op_mov_reg_T0(OT_WORD, R_EAX);
4413: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4414: tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4415: gen_op_mov_reg_T0(OT_WORD, R_EDX);
4416: tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
1.1 root 4417: s->cc_op = CC_OP_MULW;
4418: break;
4419: default:
4420: case OT_LONG:
1.1.1.7 root 4421: #ifdef TARGET_X86_64
4422: gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4423: tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4424: tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4425: tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4426: gen_op_mov_reg_T0(OT_LONG, R_EAX);
4427: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4428: tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4429: gen_op_mov_reg_T0(OT_LONG, R_EDX);
4430: tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4431: #else
4432: {
4433: TCGv_i64 t0, t1;
4434: t0 = tcg_temp_new_i64();
4435: t1 = tcg_temp_new_i64();
4436: gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4437: tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4438: tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4439: tcg_gen_mul_i64(t0, t0, t1);
4440: tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4441: gen_op_mov_reg_T0(OT_LONG, R_EAX);
4442: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4443: tcg_gen_shri_i64(t0, t0, 32);
4444: tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4445: gen_op_mov_reg_T0(OT_LONG, R_EDX);
4446: tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4447: }
4448: #endif
1.1 root 4449: s->cc_op = CC_OP_MULL;
4450: break;
4451: #ifdef TARGET_X86_64
4452: case OT_QUAD:
1.1.1.7 root 4453: gen_helper_mulq_EAX_T0(cpu_T[0]);
1.1 root 4454: s->cc_op = CC_OP_MULQ;
4455: break;
4456: #endif
4457: }
4458: break;
4459: case 5: /* imul */
4460: switch(ot) {
4461: case OT_BYTE:
1.1.1.7 root 4462: gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4463: tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4464: tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4465: /* XXX: use 32 bit mul which could be faster */
4466: tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4467: gen_op_mov_reg_T0(OT_WORD, R_EAX);
4468: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4469: tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4470: tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
1.1 root 4471: s->cc_op = CC_OP_MULB;
4472: break;
4473: case OT_WORD:
1.1.1.7 root 4474: gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4475: tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4476: tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4477: /* XXX: use 32 bit mul which could be faster */
4478: tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4479: gen_op_mov_reg_T0(OT_WORD, R_EAX);
4480: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4481: tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4482: tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4483: tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4484: gen_op_mov_reg_T0(OT_WORD, R_EDX);
1.1 root 4485: s->cc_op = CC_OP_MULW;
4486: break;
4487: default:
4488: case OT_LONG:
1.1.1.7 root 4489: #ifdef TARGET_X86_64
4490: gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4491: tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4492: tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4493: tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4494: gen_op_mov_reg_T0(OT_LONG, R_EAX);
4495: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4496: tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4497: tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4498: tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4499: gen_op_mov_reg_T0(OT_LONG, R_EDX);
4500: #else
4501: {
4502: TCGv_i64 t0, t1;
4503: t0 = tcg_temp_new_i64();
4504: t1 = tcg_temp_new_i64();
4505: gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4506: tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4507: tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4508: tcg_gen_mul_i64(t0, t0, t1);
4509: tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4510: gen_op_mov_reg_T0(OT_LONG, R_EAX);
4511: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4512: tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4513: tcg_gen_shri_i64(t0, t0, 32);
4514: tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4515: gen_op_mov_reg_T0(OT_LONG, R_EDX);
4516: tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4517: }
4518: #endif
1.1 root 4519: s->cc_op = CC_OP_MULL;
4520: break;
4521: #ifdef TARGET_X86_64
4522: case OT_QUAD:
1.1.1.7 root 4523: gen_helper_imulq_EAX_T0(cpu_T[0]);
1.1 root 4524: s->cc_op = CC_OP_MULQ;
4525: break;
4526: #endif
4527: }
4528: break;
4529: case 6: /* div */
4530: switch(ot) {
4531: case OT_BYTE:
4532: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4533: gen_helper_divb_AL(cpu_T[0]);
1.1 root 4534: break;
4535: case OT_WORD:
4536: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4537: gen_helper_divw_AX(cpu_T[0]);
1.1 root 4538: break;
4539: default:
4540: case OT_LONG:
4541: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4542: gen_helper_divl_EAX(cpu_T[0]);
1.1 root 4543: break;
4544: #ifdef TARGET_X86_64
4545: case OT_QUAD:
4546: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4547: gen_helper_divq_EAX(cpu_T[0]);
1.1 root 4548: break;
4549: #endif
4550: }
4551: break;
4552: case 7: /* idiv */
4553: switch(ot) {
4554: case OT_BYTE:
4555: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4556: gen_helper_idivb_AL(cpu_T[0]);
1.1 root 4557: break;
4558: case OT_WORD:
4559: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4560: gen_helper_idivw_AX(cpu_T[0]);
1.1 root 4561: break;
4562: default:
4563: case OT_LONG:
4564: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4565: gen_helper_idivl_EAX(cpu_T[0]);
1.1 root 4566: break;
4567: #ifdef TARGET_X86_64
4568: case OT_QUAD:
4569: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4570: gen_helper_idivq_EAX(cpu_T[0]);
1.1 root 4571: break;
4572: #endif
4573: }
4574: break;
4575: default:
4576: goto illegal_op;
4577: }
4578: break;
4579:
4580: case 0xfe: /* GRP4 */
4581: case 0xff: /* GRP5 */
4582: if ((b & 1) == 0)
4583: ot = OT_BYTE;
4584: else
4585: ot = dflag + OT_WORD;
4586:
4587: modrm = ldub_code(s->pc++);
4588: mod = (modrm >> 6) & 3;
4589: rm = (modrm & 7) | REX_B(s);
4590: op = (modrm >> 3) & 7;
4591: if (op >= 2 && b == 0xfe) {
4592: goto illegal_op;
4593: }
4594: if (CODE64(s)) {
4595: if (op == 2 || op == 4) {
4596: /* operand size for jumps is 64 bit */
4597: ot = OT_QUAD;
4598: } else if (op == 3 || op == 5) {
1.1.1.11 root 4599: ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
1.1 root 4600: } else if (op == 6) {
4601: /* default push size is 64 bit */
4602: ot = dflag ? OT_QUAD : OT_WORD;
4603: }
4604: }
4605: if (mod != 3) {
4606: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4607: if (op >= 2 && op != 3 && op != 5)
1.1.1.7 root 4608: gen_op_ld_T0_A0(ot + s->mem_index);
1.1 root 4609: } else {
1.1.1.7 root 4610: gen_op_mov_TN_reg(ot, 0, rm);
1.1 root 4611: }
4612:
4613: switch(op) {
4614: case 0: /* inc Ev */
4615: if (mod != 3)
4616: opreg = OR_TMP0;
4617: else
4618: opreg = rm;
4619: gen_inc(s, ot, opreg, 1);
4620: break;
4621: case 1: /* dec Ev */
4622: if (mod != 3)
4623: opreg = OR_TMP0;
4624: else
4625: opreg = rm;
4626: gen_inc(s, ot, opreg, -1);
4627: break;
4628: case 2: /* call Ev */
4629: /* XXX: optimize if memory (no 'and' is necessary) */
4630: if (s->dflag == 0)
4631: gen_op_andl_T0_ffff();
4632: next_eip = s->pc - s->cs_base;
4633: gen_movtl_T1_im(next_eip);
4634: gen_push_T1(s);
4635: gen_op_jmp_T0();
4636: gen_eob(s);
4637: break;
4638: case 3: /* lcall Ev */
1.1.1.7 root 4639: gen_op_ld_T1_A0(ot + s->mem_index);
1.1 root 4640: gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
1.1.1.7 root 4641: gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
1.1 root 4642: do_lcall:
4643: if (s->pe && !s->vm86) {
4644: if (s->cc_op != CC_OP_DYNAMIC)
4645: gen_op_set_cc_op(s->cc_op);
4646: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4647: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4648: gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4649: tcg_const_i32(dflag),
4650: tcg_const_i32(s->pc - pc_start));
4651: } else {
4652: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4653: gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4654: tcg_const_i32(dflag),
4655: tcg_const_i32(s->pc - s->cs_base));
1.1 root 4656: }
4657: gen_eob(s);
4658: break;
4659: case 4: /* jmp Ev */
4660: if (s->dflag == 0)
4661: gen_op_andl_T0_ffff();
4662: gen_op_jmp_T0();
4663: gen_eob(s);
4664: break;
4665: case 5: /* ljmp Ev */
1.1.1.7 root 4666: gen_op_ld_T1_A0(ot + s->mem_index);
1.1 root 4667: gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
1.1.1.7 root 4668: gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
1.1 root 4669: do_ljmp:
4670: if (s->pe && !s->vm86) {
4671: if (s->cc_op != CC_OP_DYNAMIC)
4672: gen_op_set_cc_op(s->cc_op);
4673: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 4674: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4675: gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4676: tcg_const_i32(s->pc - pc_start));
1.1 root 4677: } else {
1.1.1.7 root 4678: gen_op_movl_seg_T0_vm(R_CS);
1.1 root 4679: gen_op_movl_T0_T1();
4680: gen_op_jmp_T0();
4681: }
4682: gen_eob(s);
4683: break;
4684: case 6: /* push Ev */
4685: gen_push_T0(s);
4686: break;
4687: default:
4688: goto illegal_op;
4689: }
4690: break;
4691:
4692: case 0x84: /* test Ev, Gv */
1.1.1.6 root 4693: case 0x85:
1.1 root 4694: if ((b & 1) == 0)
4695: ot = OT_BYTE;
4696: else
4697: ot = dflag + OT_WORD;
4698:
4699: modrm = ldub_code(s->pc++);
4700: mod = (modrm >> 6) & 3;
4701: rm = (modrm & 7) | REX_B(s);
4702: reg = ((modrm >> 3) & 7) | rex_r;
1.1.1.6 root 4703:
1.1 root 4704: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
1.1.1.7 root 4705: gen_op_mov_TN_reg(ot, 1, reg);
1.1 root 4706: gen_op_testl_T0_T1_cc();
4707: s->cc_op = CC_OP_LOGICB + ot;
4708: break;
1.1.1.6 root 4709:
1.1 root 4710: case 0xa8: /* test eAX, Iv */
4711: case 0xa9:
4712: if ((b & 1) == 0)
4713: ot = OT_BYTE;
4714: else
4715: ot = dflag + OT_WORD;
4716: val = insn_get(s, ot);
4717:
1.1.1.7 root 4718: gen_op_mov_TN_reg(ot, 0, OR_EAX);
1.1 root 4719: gen_op_movl_T1_im(val);
4720: gen_op_testl_T0_T1_cc();
4721: s->cc_op = CC_OP_LOGICB + ot;
4722: break;
1.1.1.6 root 4723:
1.1 root 4724: case 0x98: /* CWDE/CBW */
4725: #ifdef TARGET_X86_64
4726: if (dflag == 2) {
1.1.1.7 root 4727: gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4728: tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4729: gen_op_mov_reg_T0(OT_QUAD, R_EAX);
1.1 root 4730: } else
4731: #endif
1.1.1.7 root 4732: if (dflag == 1) {
4733: gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4734: tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4735: gen_op_mov_reg_T0(OT_LONG, R_EAX);
4736: } else {
4737: gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4738: tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4739: gen_op_mov_reg_T0(OT_WORD, R_EAX);
4740: }
1.1 root 4741: break;
4742: case 0x99: /* CDQ/CWD */
4743: #ifdef TARGET_X86_64
4744: if (dflag == 2) {
1.1.1.7 root 4745: gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4746: tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4747: gen_op_mov_reg_T0(OT_QUAD, R_EDX);
1.1 root 4748: } else
4749: #endif
1.1.1.7 root 4750: if (dflag == 1) {
4751: gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4752: tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4753: tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4754: gen_op_mov_reg_T0(OT_LONG, R_EDX);
4755: } else {
4756: gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4757: tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4758: tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4759: gen_op_mov_reg_T0(OT_WORD, R_EDX);
4760: }
1.1 root 4761: break;
4762: case 0x1af: /* imul Gv, Ev */
4763: case 0x69: /* imul Gv, Ev, I */
4764: case 0x6b:
4765: ot = dflag + OT_WORD;
4766: modrm = ldub_code(s->pc++);
4767: reg = ((modrm >> 3) & 7) | rex_r;
4768: if (b == 0x69)
4769: s->rip_offset = insn_const_size(ot);
4770: else if (b == 0x6b)
4771: s->rip_offset = 1;
4772: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4773: if (b == 0x69) {
4774: val = insn_get(s, ot);
4775: gen_op_movl_T1_im(val);
4776: } else if (b == 0x6b) {
4777: val = (int8_t)insn_get(s, OT_BYTE);
4778: gen_op_movl_T1_im(val);
4779: } else {
1.1.1.7 root 4780: gen_op_mov_TN_reg(ot, 1, reg);
1.1 root 4781: }
4782:
4783: #ifdef TARGET_X86_64
4784: if (ot == OT_QUAD) {
1.1.1.7 root 4785: gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
1.1 root 4786: } else
4787: #endif
4788: if (ot == OT_LONG) {
1.1.1.7 root 4789: #ifdef TARGET_X86_64
4790: tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4791: tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4792: tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4793: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4794: tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4795: tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4796: #else
4797: {
4798: TCGv_i64 t0, t1;
4799: t0 = tcg_temp_new_i64();
4800: t1 = tcg_temp_new_i64();
4801: tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4802: tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4803: tcg_gen_mul_i64(t0, t0, t1);
4804: tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4805: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4806: tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4807: tcg_gen_shri_i64(t0, t0, 32);
4808: tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4809: tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4810: }
4811: #endif
1.1 root 4812: } else {
1.1.1.7 root 4813: tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4814: tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4815: /* XXX: use 32 bit mul which could be faster */
4816: tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4817: tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4818: tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4819: tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
1.1 root 4820: }
1.1.1.7 root 4821: gen_op_mov_reg_T0(ot, reg);
1.1 root 4822: s->cc_op = CC_OP_MULB + ot;
4823: break;
4824: case 0x1c0:
4825: case 0x1c1: /* xadd Ev, Gv */
4826: if ((b & 1) == 0)
4827: ot = OT_BYTE;
4828: else
4829: ot = dflag + OT_WORD;
4830: modrm = ldub_code(s->pc++);
4831: reg = ((modrm >> 3) & 7) | rex_r;
4832: mod = (modrm >> 6) & 3;
4833: if (mod == 3) {
4834: rm = (modrm & 7) | REX_B(s);
1.1.1.7 root 4835: gen_op_mov_TN_reg(ot, 0, reg);
4836: gen_op_mov_TN_reg(ot, 1, rm);
1.1 root 4837: gen_op_addl_T0_T1();
1.1.1.7 root 4838: gen_op_mov_reg_T1(ot, reg);
4839: gen_op_mov_reg_T0(ot, rm);
1.1 root 4840: } else {
4841: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 4842: gen_op_mov_TN_reg(ot, 0, reg);
4843: gen_op_ld_T1_A0(ot + s->mem_index);
1.1 root 4844: gen_op_addl_T0_T1();
1.1.1.7 root 4845: gen_op_st_T0_A0(ot + s->mem_index);
4846: gen_op_mov_reg_T1(ot, reg);
1.1 root 4847: }
4848: gen_op_update2_cc();
4849: s->cc_op = CC_OP_ADDB + ot;
4850: break;
4851: case 0x1b0:
4852: case 0x1b1: /* cmpxchg Ev, Gv */
1.1.1.7 root 4853: {
4854: int label1, label2;
4855: TCGv t0, t1, t2, a0;
4856:
4857: if ((b & 1) == 0)
4858: ot = OT_BYTE;
4859: else
4860: ot = dflag + OT_WORD;
4861: modrm = ldub_code(s->pc++);
4862: reg = ((modrm >> 3) & 7) | rex_r;
4863: mod = (modrm >> 6) & 3;
4864: t0 = tcg_temp_local_new();
4865: t1 = tcg_temp_local_new();
4866: t2 = tcg_temp_local_new();
4867: a0 = tcg_temp_local_new();
4868: gen_op_mov_v_reg(ot, t1, reg);
4869: if (mod == 3) {
4870: rm = (modrm & 7) | REX_B(s);
4871: gen_op_mov_v_reg(ot, t0, rm);
4872: } else {
4873: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4874: tcg_gen_mov_tl(a0, cpu_A0);
4875: gen_op_ld_v(ot + s->mem_index, t0, a0);
4876: rm = 0; /* avoid warning */
4877: }
4878: label1 = gen_new_label();
1.1.1.9 root 4879: tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
1.1.1.7 root 4880: gen_extu(ot, t2);
4881: tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4882: if (mod == 3) {
4883: label2 = gen_new_label();
4884: gen_op_mov_reg_v(ot, R_EAX, t0);
4885: tcg_gen_br(label2);
4886: gen_set_label(label1);
4887: gen_op_mov_reg_v(ot, rm, t1);
4888: gen_set_label(label2);
4889: } else {
4890: tcg_gen_mov_tl(t1, t0);
4891: gen_op_mov_reg_v(ot, R_EAX, t0);
4892: gen_set_label(label1);
4893: /* always store */
4894: gen_op_st_v(ot + s->mem_index, t1, a0);
4895: }
4896: tcg_gen_mov_tl(cpu_cc_src, t0);
4897: tcg_gen_mov_tl(cpu_cc_dst, t2);
4898: s->cc_op = CC_OP_SUBB + ot;
4899: tcg_temp_free(t0);
4900: tcg_temp_free(t1);
4901: tcg_temp_free(t2);
4902: tcg_temp_free(a0);
1.1 root 4903: }
4904: break;
4905: case 0x1c7: /* cmpxchg8b */
4906: modrm = ldub_code(s->pc++);
4907: mod = (modrm >> 6) & 3;
1.1.1.6 root 4908: if ((mod == 3) || ((modrm & 0x38) != 0x8))
1.1 root 4909: goto illegal_op;
1.1.1.7 root 4910: #ifdef TARGET_X86_64
4911: if (dflag == 2) {
4912: if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4913: goto illegal_op;
4914: gen_jmp_im(pc_start - s->cs_base);
4915: if (s->cc_op != CC_OP_DYNAMIC)
4916: gen_op_set_cc_op(s->cc_op);
4917: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4918: gen_helper_cmpxchg16b(cpu_A0);
4919: } else
4920: #endif
4921: {
4922: if (!(s->cpuid_features & CPUID_CX8))
4923: goto illegal_op;
4924: gen_jmp_im(pc_start - s->cs_base);
4925: if (s->cc_op != CC_OP_DYNAMIC)
4926: gen_op_set_cc_op(s->cc_op);
4927: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4928: gen_helper_cmpxchg8b(cpu_A0);
4929: }
1.1 root 4930: s->cc_op = CC_OP_EFLAGS;
4931: break;
1.1.1.6 root 4932:
1.1 root 4933: /**************************/
4934: /* push/pop */
4935: case 0x50 ... 0x57: /* push */
1.1.1.7 root 4936: gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
1.1 root 4937: gen_push_T0(s);
4938: break;
4939: case 0x58 ... 0x5f: /* pop */
4940: if (CODE64(s)) {
4941: ot = dflag ? OT_QUAD : OT_WORD;
4942: } else {
4943: ot = dflag + OT_WORD;
4944: }
4945: gen_pop_T0(s);
4946: /* NOTE: order is important for pop %sp */
4947: gen_pop_update(s);
1.1.1.7 root 4948: gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
1.1 root 4949: break;
4950: case 0x60: /* pusha */
4951: if (CODE64(s))
4952: goto illegal_op;
4953: gen_pusha(s);
4954: break;
4955: case 0x61: /* popa */
4956: if (CODE64(s))
4957: goto illegal_op;
4958: gen_popa(s);
4959: break;
4960: case 0x68: /* push Iv */
4961: case 0x6a:
4962: if (CODE64(s)) {
4963: ot = dflag ? OT_QUAD : OT_WORD;
4964: } else {
4965: ot = dflag + OT_WORD;
4966: }
4967: if (b == 0x68)
4968: val = insn_get(s, ot);
4969: else
4970: val = (int8_t)insn_get(s, OT_BYTE);
4971: gen_op_movl_T0_im(val);
4972: gen_push_T0(s);
4973: break;
4974: case 0x8f: /* pop Ev */
4975: if (CODE64(s)) {
4976: ot = dflag ? OT_QUAD : OT_WORD;
4977: } else {
4978: ot = dflag + OT_WORD;
4979: }
4980: modrm = ldub_code(s->pc++);
4981: mod = (modrm >> 6) & 3;
4982: gen_pop_T0(s);
4983: if (mod == 3) {
4984: /* NOTE: order is important for pop %sp */
4985: gen_pop_update(s);
4986: rm = (modrm & 7) | REX_B(s);
1.1.1.7 root 4987: gen_op_mov_reg_T0(ot, rm);
1.1 root 4988: } else {
4989: /* NOTE: order is important too for MMU exceptions */
4990: s->popl_esp_hack = 1 << ot;
4991: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4992: s->popl_esp_hack = 0;
4993: gen_pop_update(s);
4994: }
4995: break;
4996: case 0xc8: /* enter */
4997: {
4998: int level;
4999: val = lduw_code(s->pc);
5000: s->pc += 2;
5001: level = ldub_code(s->pc++);
5002: gen_enter(s, val, level);
5003: }
5004: break;
5005: case 0xc9: /* leave */
5006: /* XXX: exception not precise (ESP is updated before potential exception) */
5007: if (CODE64(s)) {
1.1.1.7 root 5008: gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
5009: gen_op_mov_reg_T0(OT_QUAD, R_ESP);
1.1 root 5010: } else if (s->ss32) {
1.1.1.7 root 5011: gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
5012: gen_op_mov_reg_T0(OT_LONG, R_ESP);
1.1 root 5013: } else {
1.1.1.7 root 5014: gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
5015: gen_op_mov_reg_T0(OT_WORD, R_ESP);
1.1 root 5016: }
5017: gen_pop_T0(s);
5018: if (CODE64(s)) {
5019: ot = dflag ? OT_QUAD : OT_WORD;
5020: } else {
5021: ot = dflag + OT_WORD;
5022: }
1.1.1.7 root 5023: gen_op_mov_reg_T0(ot, R_EBP);
1.1 root 5024: gen_pop_update(s);
5025: break;
5026: case 0x06: /* push es */
5027: case 0x0e: /* push cs */
5028: case 0x16: /* push ss */
5029: case 0x1e: /* push ds */
5030: if (CODE64(s))
5031: goto illegal_op;
5032: gen_op_movl_T0_seg(b >> 3);
5033: gen_push_T0(s);
5034: break;
5035: case 0x1a0: /* push fs */
5036: case 0x1a8: /* push gs */
5037: gen_op_movl_T0_seg((b >> 3) & 7);
5038: gen_push_T0(s);
5039: break;
5040: case 0x07: /* pop es */
5041: case 0x17: /* pop ss */
5042: case 0x1f: /* pop ds */
5043: if (CODE64(s))
5044: goto illegal_op;
5045: reg = b >> 3;
5046: gen_pop_T0(s);
5047: gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5048: gen_pop_update(s);
5049: if (reg == R_SS) {
5050: /* if reg == SS, inhibit interrupts/trace. */
5051: /* If several instructions disable interrupts, only the
5052: _first_ does it */
5053: if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
1.1.1.7 root 5054: gen_helper_set_inhibit_irq();
1.1 root 5055: s->tf = 0;
5056: }
5057: if (s->is_jmp) {
5058: gen_jmp_im(s->pc - s->cs_base);
5059: gen_eob(s);
5060: }
5061: break;
5062: case 0x1a1: /* pop fs */
5063: case 0x1a9: /* pop gs */
5064: gen_pop_T0(s);
5065: gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5066: gen_pop_update(s);
5067: if (s->is_jmp) {
5068: gen_jmp_im(s->pc - s->cs_base);
5069: gen_eob(s);
5070: }
5071: break;
5072:
5073: /**************************/
5074: /* mov */
5075: case 0x88:
5076: case 0x89: /* mov Gv, Ev */
5077: if ((b & 1) == 0)
5078: ot = OT_BYTE;
5079: else
5080: ot = dflag + OT_WORD;
5081: modrm = ldub_code(s->pc++);
5082: reg = ((modrm >> 3) & 7) | rex_r;
1.1.1.6 root 5083:
1.1 root 5084: /* generate a generic store */
5085: gen_ldst_modrm(s, modrm, ot, reg, 1);
5086: break;
5087: case 0xc6:
5088: case 0xc7: /* mov Ev, Iv */
5089: if ((b & 1) == 0)
5090: ot = OT_BYTE;
5091: else
5092: ot = dflag + OT_WORD;
5093: modrm = ldub_code(s->pc++);
5094: mod = (modrm >> 6) & 3;
5095: if (mod != 3) {
5096: s->rip_offset = insn_const_size(ot);
5097: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5098: }
5099: val = insn_get(s, ot);
5100: gen_op_movl_T0_im(val);
5101: if (mod != 3)
1.1.1.7 root 5102: gen_op_st_T0_A0(ot + s->mem_index);
1.1 root 5103: else
1.1.1.7 root 5104: gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
1.1 root 5105: break;
5106: case 0x8a:
5107: case 0x8b: /* mov Ev, Gv */
5108: if ((b & 1) == 0)
5109: ot = OT_BYTE;
5110: else
5111: ot = OT_WORD + dflag;
5112: modrm = ldub_code(s->pc++);
5113: reg = ((modrm >> 3) & 7) | rex_r;
1.1.1.6 root 5114:
1.1 root 5115: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
1.1.1.7 root 5116: gen_op_mov_reg_T0(ot, reg);
1.1 root 5117: break;
5118: case 0x8e: /* mov seg, Gv */
5119: modrm = ldub_code(s->pc++);
5120: reg = (modrm >> 3) & 7;
5121: if (reg >= 6 || reg == R_CS)
5122: goto illegal_op;
5123: gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5124: gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5125: if (reg == R_SS) {
5126: /* if reg == SS, inhibit interrupts/trace */
5127: /* If several instructions disable interrupts, only the
5128: _first_ does it */
5129: if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
1.1.1.7 root 5130: gen_helper_set_inhibit_irq();
1.1 root 5131: s->tf = 0;
5132: }
5133: if (s->is_jmp) {
5134: gen_jmp_im(s->pc - s->cs_base);
5135: gen_eob(s);
5136: }
5137: break;
5138: case 0x8c: /* mov Gv, seg */
5139: modrm = ldub_code(s->pc++);
5140: reg = (modrm >> 3) & 7;
5141: mod = (modrm >> 6) & 3;
5142: if (reg >= 6)
5143: goto illegal_op;
5144: gen_op_movl_T0_seg(reg);
5145: if (mod == 3)
5146: ot = OT_WORD + dflag;
5147: else
5148: ot = OT_WORD;
5149: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5150: break;
5151:
5152: case 0x1b6: /* movzbS Gv, Eb */
5153: case 0x1b7: /* movzwS Gv, Eb */
5154: case 0x1be: /* movsbS Gv, Eb */
5155: case 0x1bf: /* movswS Gv, Eb */
5156: {
5157: int d_ot;
5158: /* d_ot is the size of destination */
5159: d_ot = dflag + OT_WORD;
5160: /* ot is the size of source */
5161: ot = (b & 1) + OT_BYTE;
5162: modrm = ldub_code(s->pc++);
5163: reg = ((modrm >> 3) & 7) | rex_r;
5164: mod = (modrm >> 6) & 3;
5165: rm = (modrm & 7) | REX_B(s);
1.1.1.6 root 5166:
1.1 root 5167: if (mod == 3) {
1.1.1.7 root 5168: gen_op_mov_TN_reg(ot, 0, rm);
1.1 root 5169: switch(ot | (b & 8)) {
5170: case OT_BYTE:
1.1.1.7 root 5171: tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
1.1 root 5172: break;
5173: case OT_BYTE | 8:
1.1.1.7 root 5174: tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
1.1 root 5175: break;
5176: case OT_WORD:
1.1.1.7 root 5177: tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
1.1 root 5178: break;
5179: default:
5180: case OT_WORD | 8:
1.1.1.7 root 5181: tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
1.1 root 5182: break;
5183: }
1.1.1.7 root 5184: gen_op_mov_reg_T0(d_ot, reg);
1.1 root 5185: } else {
5186: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5187: if (b & 8) {
1.1.1.7 root 5188: gen_op_lds_T0_A0(ot + s->mem_index);
1.1 root 5189: } else {
1.1.1.7 root 5190: gen_op_ldu_T0_A0(ot + s->mem_index);
1.1 root 5191: }
1.1.1.7 root 5192: gen_op_mov_reg_T0(d_ot, reg);
1.1 root 5193: }
5194: }
5195: break;
5196:
5197: case 0x8d: /* lea */
5198: ot = dflag + OT_WORD;
5199: modrm = ldub_code(s->pc++);
5200: mod = (modrm >> 6) & 3;
5201: if (mod == 3)
5202: goto illegal_op;
5203: reg = ((modrm >> 3) & 7) | rex_r;
5204: /* we must ensure that no segment is added */
5205: s->override = -1;
5206: val = s->addseg;
5207: s->addseg = 0;
5208: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5209: s->addseg = val;
1.1.1.7 root 5210: gen_op_mov_reg_A0(ot - OT_WORD, reg);
1.1 root 5211: break;
1.1.1.6 root 5212:
1.1 root 5213: case 0xa0: /* mov EAX, Ov */
5214: case 0xa1:
5215: case 0xa2: /* mov Ov, EAX */
5216: case 0xa3:
5217: {
5218: target_ulong offset_addr;
5219:
5220: if ((b & 1) == 0)
5221: ot = OT_BYTE;
5222: else
5223: ot = dflag + OT_WORD;
5224: #ifdef TARGET_X86_64
5225: if (s->aflag == 2) {
5226: offset_addr = ldq_code(s->pc);
5227: s->pc += 8;
1.1.1.7 root 5228: gen_op_movq_A0_im(offset_addr);
1.1.1.6 root 5229: } else
1.1 root 5230: #endif
5231: {
5232: if (s->aflag) {
5233: offset_addr = insn_get(s, OT_LONG);
5234: } else {
5235: offset_addr = insn_get(s, OT_WORD);
5236: }
5237: gen_op_movl_A0_im(offset_addr);
5238: }
5239: gen_add_A0_ds_seg(s);
5240: if ((b & 2) == 0) {
1.1.1.7 root 5241: gen_op_ld_T0_A0(ot + s->mem_index);
5242: gen_op_mov_reg_T0(ot, R_EAX);
1.1 root 5243: } else {
1.1.1.7 root 5244: gen_op_mov_TN_reg(ot, 0, R_EAX);
5245: gen_op_st_T0_A0(ot + s->mem_index);
1.1 root 5246: }
5247: }
5248: break;
5249: case 0xd7: /* xlat */
5250: #ifdef TARGET_X86_64
5251: if (s->aflag == 2) {
1.1.1.7 root 5252: gen_op_movq_A0_reg(R_EBX);
5253: gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5254: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5255: tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
1.1.1.6 root 5256: } else
1.1 root 5257: #endif
5258: {
1.1.1.7 root 5259: gen_op_movl_A0_reg(R_EBX);
5260: gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5261: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5262: tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
1.1 root 5263: if (s->aflag == 0)
5264: gen_op_andl_A0_ffff();
1.1.1.7 root 5265: else
5266: tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
1.1 root 5267: }
5268: gen_add_A0_ds_seg(s);
1.1.1.7 root 5269: gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5270: gen_op_mov_reg_T0(OT_BYTE, R_EAX);
1.1 root 5271: break;
5272: case 0xb0 ... 0xb7: /* mov R, Ib */
5273: val = insn_get(s, OT_BYTE);
5274: gen_op_movl_T0_im(val);
1.1.1.7 root 5275: gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
1.1 root 5276: break;
5277: case 0xb8 ... 0xbf: /* mov R, Iv */
5278: #ifdef TARGET_X86_64
5279: if (dflag == 2) {
5280: uint64_t tmp;
5281: /* 64 bit case */
5282: tmp = ldq_code(s->pc);
5283: s->pc += 8;
5284: reg = (b & 7) | REX_B(s);
5285: gen_movtl_T0_im(tmp);
1.1.1.7 root 5286: gen_op_mov_reg_T0(OT_QUAD, reg);
1.1.1.6 root 5287: } else
1.1 root 5288: #endif
5289: {
5290: ot = dflag ? OT_LONG : OT_WORD;
5291: val = insn_get(s, ot);
5292: reg = (b & 7) | REX_B(s);
5293: gen_op_movl_T0_im(val);
1.1.1.7 root 5294: gen_op_mov_reg_T0(ot, reg);
1.1 root 5295: }
5296: break;
5297:
5298: case 0x91 ... 0x97: /* xchg R, EAX */
1.1.1.12! root 5299: do_xchg_reg_eax:
1.1 root 5300: ot = dflag + OT_WORD;
5301: reg = (b & 7) | REX_B(s);
5302: rm = R_EAX;
5303: goto do_xchg_reg;
5304: case 0x86:
5305: case 0x87: /* xchg Ev, Gv */
5306: if ((b & 1) == 0)
5307: ot = OT_BYTE;
5308: else
5309: ot = dflag + OT_WORD;
5310: modrm = ldub_code(s->pc++);
5311: reg = ((modrm >> 3) & 7) | rex_r;
5312: mod = (modrm >> 6) & 3;
5313: if (mod == 3) {
5314: rm = (modrm & 7) | REX_B(s);
5315: do_xchg_reg:
1.1.1.7 root 5316: gen_op_mov_TN_reg(ot, 0, reg);
5317: gen_op_mov_TN_reg(ot, 1, rm);
5318: gen_op_mov_reg_T0(ot, rm);
5319: gen_op_mov_reg_T1(ot, reg);
1.1 root 5320: } else {
5321: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 5322: gen_op_mov_TN_reg(ot, 0, reg);
1.1 root 5323: /* for xchg, lock is implicit */
5324: if (!(prefixes & PREFIX_LOCK))
1.1.1.7 root 5325: gen_helper_lock();
5326: gen_op_ld_T1_A0(ot + s->mem_index);
5327: gen_op_st_T0_A0(ot + s->mem_index);
1.1 root 5328: if (!(prefixes & PREFIX_LOCK))
1.1.1.7 root 5329: gen_helper_unlock();
5330: gen_op_mov_reg_T1(ot, reg);
1.1 root 5331: }
5332: break;
5333: case 0xc4: /* les Gv */
5334: if (CODE64(s))
5335: goto illegal_op;
5336: op = R_ES;
5337: goto do_lxx;
5338: case 0xc5: /* lds Gv */
5339: if (CODE64(s))
5340: goto illegal_op;
5341: op = R_DS;
5342: goto do_lxx;
5343: case 0x1b2: /* lss Gv */
5344: op = R_SS;
5345: goto do_lxx;
5346: case 0x1b4: /* lfs Gv */
5347: op = R_FS;
5348: goto do_lxx;
5349: case 0x1b5: /* lgs Gv */
5350: op = R_GS;
5351: do_lxx:
5352: ot = dflag ? OT_LONG : OT_WORD;
5353: modrm = ldub_code(s->pc++);
5354: reg = ((modrm >> 3) & 7) | rex_r;
5355: mod = (modrm >> 6) & 3;
5356: if (mod == 3)
5357: goto illegal_op;
5358: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 5359: gen_op_ld_T1_A0(ot + s->mem_index);
1.1 root 5360: gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5361: /* load the segment first to handle exceptions properly */
1.1.1.7 root 5362: gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
1.1 root 5363: gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5364: /* then put the data */
1.1.1.7 root 5365: gen_op_mov_reg_T1(ot, reg);
1.1 root 5366: if (s->is_jmp) {
5367: gen_jmp_im(s->pc - s->cs_base);
5368: gen_eob(s);
5369: }
5370: break;
1.1.1.6 root 5371:
1.1 root 5372: /************************/
5373: /* shifts */
5374: case 0xc0:
5375: case 0xc1:
5376: /* shift Ev,Ib */
5377: shift = 2;
5378: grp2:
5379: {
5380: if ((b & 1) == 0)
5381: ot = OT_BYTE;
5382: else
5383: ot = dflag + OT_WORD;
1.1.1.6 root 5384:
1.1 root 5385: modrm = ldub_code(s->pc++);
5386: mod = (modrm >> 6) & 3;
5387: op = (modrm >> 3) & 7;
1.1.1.6 root 5388:
1.1 root 5389: if (mod != 3) {
5390: if (shift == 2) {
5391: s->rip_offset = 1;
5392: }
5393: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5394: opreg = OR_TMP0;
5395: } else {
5396: opreg = (modrm & 7) | REX_B(s);
5397: }
5398:
5399: /* simpler op */
5400: if (shift == 0) {
5401: gen_shift(s, op, ot, opreg, OR_ECX);
5402: } else {
5403: if (shift == 2) {
5404: shift = ldub_code(s->pc++);
5405: }
5406: gen_shifti(s, op, ot, opreg, shift);
5407: }
5408: }
5409: break;
5410: case 0xd0:
5411: case 0xd1:
5412: /* shift Ev,1 */
5413: shift = 1;
5414: goto grp2;
5415: case 0xd2:
5416: case 0xd3:
5417: /* shift Ev,cl */
5418: shift = 0;
5419: goto grp2;
5420:
5421: case 0x1a4: /* shld imm */
5422: op = 0;
5423: shift = 1;
5424: goto do_shiftd;
5425: case 0x1a5: /* shld cl */
5426: op = 0;
5427: shift = 0;
5428: goto do_shiftd;
5429: case 0x1ac: /* shrd imm */
5430: op = 1;
5431: shift = 1;
5432: goto do_shiftd;
5433: case 0x1ad: /* shrd cl */
5434: op = 1;
5435: shift = 0;
5436: do_shiftd:
5437: ot = dflag + OT_WORD;
5438: modrm = ldub_code(s->pc++);
5439: mod = (modrm >> 6) & 3;
5440: rm = (modrm & 7) | REX_B(s);
5441: reg = ((modrm >> 3) & 7) | rex_r;
5442: if (mod != 3) {
5443: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 5444: opreg = OR_TMP0;
1.1 root 5445: } else {
1.1.1.7 root 5446: opreg = rm;
1.1 root 5447: }
1.1.1.7 root 5448: gen_op_mov_TN_reg(ot, 1, reg);
1.1.1.6 root 5449:
1.1 root 5450: if (shift) {
5451: val = ldub_code(s->pc++);
1.1.1.7 root 5452: tcg_gen_movi_tl(cpu_T3, val);
1.1 root 5453: } else {
1.1.1.9 root 5454: tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
1.1 root 5455: }
1.1.1.7 root 5456: gen_shiftd_rm_T1_T3(s, ot, opreg, op);
1.1 root 5457: break;
5458:
5459: /************************/
5460: /* floats */
1.1.1.6 root 5461: case 0xd8 ... 0xdf:
1.1 root 5462: if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5463: /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5464: /* XXX: what to do if illegal op ? */
5465: gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5466: break;
5467: }
5468: modrm = ldub_code(s->pc++);
5469: mod = (modrm >> 6) & 3;
5470: rm = modrm & 7;
5471: op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5472: if (mod != 3) {
5473: /* memory op */
5474: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5475: switch(op) {
5476: case 0x00 ... 0x07: /* fxxxs */
5477: case 0x10 ... 0x17: /* fixxxl */
5478: case 0x20 ... 0x27: /* fxxxl */
5479: case 0x30 ... 0x37: /* fixxx */
5480: {
5481: int op1;
5482: op1 = op & 7;
5483:
5484: switch(op >> 4) {
5485: case 0:
1.1.1.7 root 5486: gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5487: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5488: gen_helper_flds_FT0(cpu_tmp2_i32);
1.1 root 5489: break;
5490: case 1:
1.1.1.7 root 5491: gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5492: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5493: gen_helper_fildl_FT0(cpu_tmp2_i32);
1.1 root 5494: break;
5495: case 2:
1.1.1.7 root 5496: tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5497: (s->mem_index >> 2) - 1);
5498: gen_helper_fldl_FT0(cpu_tmp1_i64);
1.1 root 5499: break;
5500: case 3:
5501: default:
1.1.1.7 root 5502: gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5503: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5504: gen_helper_fildl_FT0(cpu_tmp2_i32);
1.1 root 5505: break;
5506: }
1.1.1.6 root 5507:
1.1.1.7 root 5508: gen_helper_fp_arith_ST0_FT0(op1);
1.1 root 5509: if (op1 == 3) {
5510: /* fcomp needs pop */
1.1.1.7 root 5511: gen_helper_fpop();
1.1 root 5512: }
5513: }
5514: break;
5515: case 0x08: /* flds */
5516: case 0x0a: /* fsts */
5517: case 0x0b: /* fstps */
1.1.1.3 root 5518: case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5519: case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5520: case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
1.1 root 5521: switch(op & 7) {
5522: case 0:
5523: switch(op >> 4) {
5524: case 0:
1.1.1.7 root 5525: gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5526: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5527: gen_helper_flds_ST0(cpu_tmp2_i32);
1.1 root 5528: break;
5529: case 1:
1.1.1.7 root 5530: gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5531: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5532: gen_helper_fildl_ST0(cpu_tmp2_i32);
1.1 root 5533: break;
5534: case 2:
1.1.1.7 root 5535: tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5536: (s->mem_index >> 2) - 1);
5537: gen_helper_fldl_ST0(cpu_tmp1_i64);
1.1 root 5538: break;
5539: case 3:
5540: default:
1.1.1.7 root 5541: gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5542: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5543: gen_helper_fildl_ST0(cpu_tmp2_i32);
1.1 root 5544: break;
5545: }
5546: break;
1.1.1.3 root 5547: case 1:
1.1.1.7 root 5548: /* XXX: the corresponding CPUID bit must be tested ! */
1.1.1.3 root 5549: switch(op >> 4) {
5550: case 1:
1.1.1.7 root 5551: gen_helper_fisttl_ST0(cpu_tmp2_i32);
5552: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5553: gen_op_st_T0_A0(OT_LONG + s->mem_index);
1.1.1.3 root 5554: break;
5555: case 2:
1.1.1.7 root 5556: gen_helper_fisttll_ST0(cpu_tmp1_i64);
5557: tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5558: (s->mem_index >> 2) - 1);
1.1.1.3 root 5559: break;
5560: case 3:
5561: default:
1.1.1.7 root 5562: gen_helper_fistt_ST0(cpu_tmp2_i32);
5563: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5564: gen_op_st_T0_A0(OT_WORD + s->mem_index);
5565: break;
1.1.1.3 root 5566: }
1.1.1.7 root 5567: gen_helper_fpop();
1.1.1.3 root 5568: break;
1.1 root 5569: default:
5570: switch(op >> 4) {
5571: case 0:
1.1.1.7 root 5572: gen_helper_fsts_ST0(cpu_tmp2_i32);
5573: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5574: gen_op_st_T0_A0(OT_LONG + s->mem_index);
1.1 root 5575: break;
5576: case 1:
1.1.1.7 root 5577: gen_helper_fistl_ST0(cpu_tmp2_i32);
5578: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5579: gen_op_st_T0_A0(OT_LONG + s->mem_index);
1.1 root 5580: break;
5581: case 2:
1.1.1.7 root 5582: gen_helper_fstl_ST0(cpu_tmp1_i64);
5583: tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5584: (s->mem_index >> 2) - 1);
1.1 root 5585: break;
5586: case 3:
5587: default:
1.1.1.7 root 5588: gen_helper_fist_ST0(cpu_tmp2_i32);
5589: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5590: gen_op_st_T0_A0(OT_WORD + s->mem_index);
1.1 root 5591: break;
5592: }
5593: if ((op & 7) == 3)
1.1.1.7 root 5594: gen_helper_fpop();
1.1 root 5595: break;
5596: }
5597: break;
5598: case 0x0c: /* fldenv mem */
1.1.1.7 root 5599: if (s->cc_op != CC_OP_DYNAMIC)
5600: gen_op_set_cc_op(s->cc_op);
5601: gen_jmp_im(pc_start - s->cs_base);
5602: gen_helper_fldenv(
5603: cpu_A0, tcg_const_i32(s->dflag));
1.1 root 5604: break;
5605: case 0x0d: /* fldcw mem */
1.1.1.7 root 5606: gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5607: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5608: gen_helper_fldcw(cpu_tmp2_i32);
1.1 root 5609: break;
5610: case 0x0e: /* fnstenv mem */
1.1.1.7 root 5611: if (s->cc_op != CC_OP_DYNAMIC)
5612: gen_op_set_cc_op(s->cc_op);
5613: gen_jmp_im(pc_start - s->cs_base);
5614: gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag));
1.1 root 5615: break;
5616: case 0x0f: /* fnstcw mem */
1.1.1.7 root 5617: gen_helper_fnstcw(cpu_tmp2_i32);
5618: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5619: gen_op_st_T0_A0(OT_WORD + s->mem_index);
1.1 root 5620: break;
5621: case 0x1d: /* fldt mem */
1.1.1.7 root 5622: if (s->cc_op != CC_OP_DYNAMIC)
5623: gen_op_set_cc_op(s->cc_op);
5624: gen_jmp_im(pc_start - s->cs_base);
5625: gen_helper_fldt_ST0(cpu_A0);
1.1 root 5626: break;
5627: case 0x1f: /* fstpt mem */
1.1.1.7 root 5628: if (s->cc_op != CC_OP_DYNAMIC)
5629: gen_op_set_cc_op(s->cc_op);
5630: gen_jmp_im(pc_start - s->cs_base);
5631: gen_helper_fstt_ST0(cpu_A0);
5632: gen_helper_fpop();
1.1 root 5633: break;
5634: case 0x2c: /* frstor mem */
1.1.1.7 root 5635: if (s->cc_op != CC_OP_DYNAMIC)
5636: gen_op_set_cc_op(s->cc_op);
5637: gen_jmp_im(pc_start - s->cs_base);
5638: gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag));
1.1 root 5639: break;
5640: case 0x2e: /* fnsave mem */
1.1.1.7 root 5641: if (s->cc_op != CC_OP_DYNAMIC)
5642: gen_op_set_cc_op(s->cc_op);
5643: gen_jmp_im(pc_start - s->cs_base);
5644: gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag));
1.1 root 5645: break;
5646: case 0x2f: /* fnstsw mem */
1.1.1.7 root 5647: gen_helper_fnstsw(cpu_tmp2_i32);
5648: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5649: gen_op_st_T0_A0(OT_WORD + s->mem_index);
1.1 root 5650: break;
5651: case 0x3c: /* fbld */
1.1.1.7 root 5652: if (s->cc_op != CC_OP_DYNAMIC)
5653: gen_op_set_cc_op(s->cc_op);
5654: gen_jmp_im(pc_start - s->cs_base);
5655: gen_helper_fbld_ST0(cpu_A0);
1.1 root 5656: break;
5657: case 0x3e: /* fbstp */
1.1.1.7 root 5658: if (s->cc_op != CC_OP_DYNAMIC)
5659: gen_op_set_cc_op(s->cc_op);
5660: gen_jmp_im(pc_start - s->cs_base);
5661: gen_helper_fbst_ST0(cpu_A0);
5662: gen_helper_fpop();
1.1 root 5663: break;
5664: case 0x3d: /* fildll */
1.1.1.7 root 5665: tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5666: (s->mem_index >> 2) - 1);
5667: gen_helper_fildll_ST0(cpu_tmp1_i64);
1.1 root 5668: break;
5669: case 0x3f: /* fistpll */
1.1.1.7 root 5670: gen_helper_fistll_ST0(cpu_tmp1_i64);
5671: tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5672: (s->mem_index >> 2) - 1);
5673: gen_helper_fpop();
1.1 root 5674: break;
5675: default:
5676: goto illegal_op;
5677: }
5678: } else {
5679: /* register float ops */
5680: opreg = rm;
5681:
5682: switch(op) {
5683: case 0x08: /* fld sti */
1.1.1.7 root 5684: gen_helper_fpush();
5685: gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7));
1.1 root 5686: break;
5687: case 0x09: /* fxchg sti */
5688: case 0x29: /* fxchg4 sti, undocumented op */
5689: case 0x39: /* fxchg7 sti, undocumented op */
1.1.1.7 root 5690: gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg));
1.1 root 5691: break;
5692: case 0x0a: /* grp d9/2 */
5693: switch(rm) {
5694: case 0: /* fnop */
5695: /* check exceptions (FreeBSD FPU probe) */
5696: if (s->cc_op != CC_OP_DYNAMIC)
5697: gen_op_set_cc_op(s->cc_op);
5698: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 5699: gen_helper_fwait();
1.1 root 5700: break;
5701: default:
5702: goto illegal_op;
5703: }
5704: break;
5705: case 0x0c: /* grp d9/4 */
5706: switch(rm) {
5707: case 0: /* fchs */
1.1.1.7 root 5708: gen_helper_fchs_ST0();
1.1 root 5709: break;
5710: case 1: /* fabs */
1.1.1.7 root 5711: gen_helper_fabs_ST0();
1.1 root 5712: break;
5713: case 4: /* ftst */
1.1.1.7 root 5714: gen_helper_fldz_FT0();
5715: gen_helper_fcom_ST0_FT0();
1.1 root 5716: break;
5717: case 5: /* fxam */
1.1.1.7 root 5718: gen_helper_fxam_ST0();
1.1 root 5719: break;
5720: default:
5721: goto illegal_op;
5722: }
5723: break;
5724: case 0x0d: /* grp d9/5 */
5725: {
5726: switch(rm) {
5727: case 0:
1.1.1.7 root 5728: gen_helper_fpush();
5729: gen_helper_fld1_ST0();
1.1 root 5730: break;
5731: case 1:
1.1.1.7 root 5732: gen_helper_fpush();
5733: gen_helper_fldl2t_ST0();
1.1 root 5734: break;
5735: case 2:
1.1.1.7 root 5736: gen_helper_fpush();
5737: gen_helper_fldl2e_ST0();
1.1 root 5738: break;
5739: case 3:
1.1.1.7 root 5740: gen_helper_fpush();
5741: gen_helper_fldpi_ST0();
1.1 root 5742: break;
5743: case 4:
1.1.1.7 root 5744: gen_helper_fpush();
5745: gen_helper_fldlg2_ST0();
1.1 root 5746: break;
5747: case 5:
1.1.1.7 root 5748: gen_helper_fpush();
5749: gen_helper_fldln2_ST0();
1.1 root 5750: break;
5751: case 6:
1.1.1.7 root 5752: gen_helper_fpush();
5753: gen_helper_fldz_ST0();
1.1 root 5754: break;
5755: default:
5756: goto illegal_op;
5757: }
5758: }
5759: break;
5760: case 0x0e: /* grp d9/6 */
5761: switch(rm) {
5762: case 0: /* f2xm1 */
1.1.1.7 root 5763: gen_helper_f2xm1();
1.1 root 5764: break;
5765: case 1: /* fyl2x */
1.1.1.7 root 5766: gen_helper_fyl2x();
1.1 root 5767: break;
5768: case 2: /* fptan */
1.1.1.7 root 5769: gen_helper_fptan();
1.1 root 5770: break;
5771: case 3: /* fpatan */
1.1.1.7 root 5772: gen_helper_fpatan();
1.1 root 5773: break;
5774: case 4: /* fxtract */
1.1.1.7 root 5775: gen_helper_fxtract();
1.1 root 5776: break;
5777: case 5: /* fprem1 */
1.1.1.7 root 5778: gen_helper_fprem1();
1.1 root 5779: break;
5780: case 6: /* fdecstp */
1.1.1.7 root 5781: gen_helper_fdecstp();
1.1 root 5782: break;
5783: default:
5784: case 7: /* fincstp */
1.1.1.7 root 5785: gen_helper_fincstp();
1.1 root 5786: break;
5787: }
5788: break;
5789: case 0x0f: /* grp d9/7 */
5790: switch(rm) {
5791: case 0: /* fprem */
1.1.1.7 root 5792: gen_helper_fprem();
1.1 root 5793: break;
5794: case 1: /* fyl2xp1 */
1.1.1.7 root 5795: gen_helper_fyl2xp1();
1.1 root 5796: break;
5797: case 2: /* fsqrt */
1.1.1.7 root 5798: gen_helper_fsqrt();
1.1 root 5799: break;
5800: case 3: /* fsincos */
1.1.1.7 root 5801: gen_helper_fsincos();
1.1 root 5802: break;
5803: case 5: /* fscale */
1.1.1.7 root 5804: gen_helper_fscale();
1.1 root 5805: break;
5806: case 4: /* frndint */
1.1.1.7 root 5807: gen_helper_frndint();
1.1 root 5808: break;
5809: case 6: /* fsin */
1.1.1.7 root 5810: gen_helper_fsin();
1.1 root 5811: break;
5812: default:
5813: case 7: /* fcos */
1.1.1.7 root 5814: gen_helper_fcos();
1.1 root 5815: break;
5816: }
5817: break;
5818: case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5819: case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5820: case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5821: {
5822: int op1;
1.1.1.6 root 5823:
1.1 root 5824: op1 = op & 7;
5825: if (op >= 0x20) {
1.1.1.7 root 5826: gen_helper_fp_arith_STN_ST0(op1, opreg);
1.1 root 5827: if (op >= 0x30)
1.1.1.7 root 5828: gen_helper_fpop();
1.1 root 5829: } else {
1.1.1.7 root 5830: gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5831: gen_helper_fp_arith_ST0_FT0(op1);
1.1 root 5832: }
5833: }
5834: break;
5835: case 0x02: /* fcom */
5836: case 0x22: /* fcom2, undocumented op */
1.1.1.7 root 5837: gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5838: gen_helper_fcom_ST0_FT0();
1.1 root 5839: break;
5840: case 0x03: /* fcomp */
5841: case 0x23: /* fcomp3, undocumented op */
5842: case 0x32: /* fcomp5, undocumented op */
1.1.1.7 root 5843: gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5844: gen_helper_fcom_ST0_FT0();
5845: gen_helper_fpop();
1.1 root 5846: break;
5847: case 0x15: /* da/5 */
5848: switch(rm) {
5849: case 1: /* fucompp */
1.1.1.7 root 5850: gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5851: gen_helper_fucom_ST0_FT0();
5852: gen_helper_fpop();
5853: gen_helper_fpop();
1.1 root 5854: break;
5855: default:
5856: goto illegal_op;
5857: }
5858: break;
5859: case 0x1c:
5860: switch(rm) {
5861: case 0: /* feni (287 only, just do nop here) */
5862: break;
5863: case 1: /* fdisi (287 only, just do nop here) */
5864: break;
5865: case 2: /* fclex */
1.1.1.7 root 5866: gen_helper_fclex();
1.1 root 5867: break;
5868: case 3: /* fninit */
1.1.1.7 root 5869: gen_helper_fninit();
1.1 root 5870: break;
5871: case 4: /* fsetpm (287 only, just do nop here) */
5872: break;
5873: default:
5874: goto illegal_op;
5875: }
5876: break;
5877: case 0x1d: /* fucomi */
5878: if (s->cc_op != CC_OP_DYNAMIC)
5879: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 5880: gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5881: gen_helper_fucomi_ST0_FT0();
1.1 root 5882: s->cc_op = CC_OP_EFLAGS;
5883: break;
5884: case 0x1e: /* fcomi */
5885: if (s->cc_op != CC_OP_DYNAMIC)
5886: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 5887: gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5888: gen_helper_fcomi_ST0_FT0();
1.1 root 5889: s->cc_op = CC_OP_EFLAGS;
5890: break;
5891: case 0x28: /* ffree sti */
1.1.1.7 root 5892: gen_helper_ffree_STN(tcg_const_i32(opreg));
1.1.1.6 root 5893: break;
1.1 root 5894: case 0x2a: /* fst sti */
1.1.1.7 root 5895: gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
1.1 root 5896: break;
5897: case 0x2b: /* fstp sti */
5898: case 0x0b: /* fstp1 sti, undocumented op */
5899: case 0x3a: /* fstp8 sti, undocumented op */
5900: case 0x3b: /* fstp9 sti, undocumented op */
1.1.1.7 root 5901: gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5902: gen_helper_fpop();
1.1 root 5903: break;
5904: case 0x2c: /* fucom st(i) */
1.1.1.7 root 5905: gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5906: gen_helper_fucom_ST0_FT0();
1.1 root 5907: break;
5908: case 0x2d: /* fucomp st(i) */
1.1.1.7 root 5909: gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5910: gen_helper_fucom_ST0_FT0();
5911: gen_helper_fpop();
1.1 root 5912: break;
5913: case 0x33: /* de/3 */
5914: switch(rm) {
5915: case 1: /* fcompp */
1.1.1.7 root 5916: gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5917: gen_helper_fcom_ST0_FT0();
5918: gen_helper_fpop();
5919: gen_helper_fpop();
1.1 root 5920: break;
5921: default:
5922: goto illegal_op;
5923: }
5924: break;
5925: case 0x38: /* ffreep sti, undocumented op */
1.1.1.7 root 5926: gen_helper_ffree_STN(tcg_const_i32(opreg));
5927: gen_helper_fpop();
1.1 root 5928: break;
5929: case 0x3c: /* df/4 */
5930: switch(rm) {
5931: case 0:
1.1.1.7 root 5932: gen_helper_fnstsw(cpu_tmp2_i32);
5933: tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5934: gen_op_mov_reg_T0(OT_WORD, R_EAX);
1.1 root 5935: break;
5936: default:
5937: goto illegal_op;
5938: }
5939: break;
5940: case 0x3d: /* fucomip */
5941: if (s->cc_op != CC_OP_DYNAMIC)
5942: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 5943: gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5944: gen_helper_fucomi_ST0_FT0();
5945: gen_helper_fpop();
1.1 root 5946: s->cc_op = CC_OP_EFLAGS;
5947: break;
5948: case 0x3e: /* fcomip */
5949: if (s->cc_op != CC_OP_DYNAMIC)
5950: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 5951: gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5952: gen_helper_fcomi_ST0_FT0();
5953: gen_helper_fpop();
1.1 root 5954: s->cc_op = CC_OP_EFLAGS;
5955: break;
5956: case 0x10 ... 0x13: /* fcmovxx */
5957: case 0x18 ... 0x1b:
5958: {
1.1.1.7 root 5959: int op1, l1;
5960: static const uint8_t fcmov_cc[8] = {
1.1 root 5961: (JCC_B << 1),
5962: (JCC_Z << 1),
5963: (JCC_BE << 1),
5964: (JCC_P << 1),
5965: };
1.1.1.7 root 5966: op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
5967: l1 = gen_new_label();
5968: gen_jcc1(s, s->cc_op, op1, l1);
5969: gen_helper_fmov_ST0_STN(tcg_const_i32(opreg));
5970: gen_set_label(l1);
1.1 root 5971: }
5972: break;
5973: default:
5974: goto illegal_op;
5975: }
5976: }
5977: break;
5978: /************************/
5979: /* string ops */
5980:
5981: case 0xa4: /* movsS */
5982: case 0xa5:
5983: if ((b & 1) == 0)
5984: ot = OT_BYTE;
5985: else
5986: ot = dflag + OT_WORD;
5987:
5988: if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5989: gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5990: } else {
5991: gen_movs(s, ot);
5992: }
5993: break;
1.1.1.6 root 5994:
1.1 root 5995: case 0xaa: /* stosS */
5996: case 0xab:
5997: if ((b & 1) == 0)
5998: ot = OT_BYTE;
5999: else
6000: ot = dflag + OT_WORD;
6001:
6002: if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6003: gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6004: } else {
6005: gen_stos(s, ot);
6006: }
6007: break;
6008: case 0xac: /* lodsS */
6009: case 0xad:
6010: if ((b & 1) == 0)
6011: ot = OT_BYTE;
6012: else
6013: ot = dflag + OT_WORD;
6014: if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6015: gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6016: } else {
6017: gen_lods(s, ot);
6018: }
6019: break;
6020: case 0xae: /* scasS */
6021: case 0xaf:
6022: if ((b & 1) == 0)
6023: ot = OT_BYTE;
6024: else
6025: ot = dflag + OT_WORD;
6026: if (prefixes & PREFIX_REPNZ) {
6027: gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6028: } else if (prefixes & PREFIX_REPZ) {
6029: gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6030: } else {
6031: gen_scas(s, ot);
6032: s->cc_op = CC_OP_SUBB + ot;
6033: }
6034: break;
6035:
6036: case 0xa6: /* cmpsS */
6037: case 0xa7:
6038: if ((b & 1) == 0)
6039: ot = OT_BYTE;
6040: else
6041: ot = dflag + OT_WORD;
6042: if (prefixes & PREFIX_REPNZ) {
6043: gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6044: } else if (prefixes & PREFIX_REPZ) {
6045: gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6046: } else {
6047: gen_cmps(s, ot);
6048: s->cc_op = CC_OP_SUBB + ot;
6049: }
6050: break;
6051: case 0x6c: /* insS */
6052: case 0x6d:
6053: if ((b & 1) == 0)
6054: ot = OT_BYTE;
6055: else
6056: ot = dflag ? OT_LONG : OT_WORD;
1.1.1.7 root 6057: gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
1.1.1.6 root 6058: gen_op_andl_T0_ffff();
1.1.1.7 root 6059: gen_check_io(s, ot, pc_start - s->cs_base,
6060: SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
1.1 root 6061: if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6062: gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6063: } else {
6064: gen_ins(s, ot);
1.1.1.7 root 6065: if (use_icount) {
6066: gen_jmp(s, s->pc - s->cs_base);
6067: }
1.1 root 6068: }
6069: break;
6070: case 0x6e: /* outsS */
6071: case 0x6f:
6072: if ((b & 1) == 0)
6073: ot = OT_BYTE;
6074: else
6075: ot = dflag ? OT_LONG : OT_WORD;
1.1.1.7 root 6076: gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
1.1.1.6 root 6077: gen_op_andl_T0_ffff();
1.1.1.7 root 6078: gen_check_io(s, ot, pc_start - s->cs_base,
6079: svm_is_rep(prefixes) | 4);
1.1 root 6080: if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6081: gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6082: } else {
6083: gen_outs(s, ot);
1.1.1.7 root 6084: if (use_icount) {
6085: gen_jmp(s, s->pc - s->cs_base);
6086: }
1.1 root 6087: }
6088: break;
6089:
6090: /************************/
6091: /* port I/O */
1.1.1.6 root 6092:
1.1 root 6093: case 0xe4:
6094: case 0xe5:
6095: if ((b & 1) == 0)
6096: ot = OT_BYTE;
6097: else
6098: ot = dflag ? OT_LONG : OT_WORD;
6099: val = ldub_code(s->pc++);
6100: gen_op_movl_T0_im(val);
1.1.1.7 root 6101: gen_check_io(s, ot, pc_start - s->cs_base,
6102: SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6103: if (use_icount)
6104: gen_io_start();
6105: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6106: gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6107: gen_op_mov_reg_T1(ot, R_EAX);
6108: if (use_icount) {
6109: gen_io_end();
6110: gen_jmp(s, s->pc - s->cs_base);
6111: }
1.1 root 6112: break;
6113: case 0xe6:
6114: case 0xe7:
6115: if ((b & 1) == 0)
6116: ot = OT_BYTE;
6117: else
6118: ot = dflag ? OT_LONG : OT_WORD;
6119: val = ldub_code(s->pc++);
6120: gen_op_movl_T0_im(val);
1.1.1.7 root 6121: gen_check_io(s, ot, pc_start - s->cs_base,
6122: svm_is_rep(prefixes));
6123: gen_op_mov_TN_reg(ot, 1, R_EAX);
6124:
6125: if (use_icount)
6126: gen_io_start();
6127: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6128: tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6129: tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6130: gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6131: if (use_icount) {
6132: gen_io_end();
6133: gen_jmp(s, s->pc - s->cs_base);
6134: }
1.1 root 6135: break;
6136: case 0xec:
6137: case 0xed:
6138: if ((b & 1) == 0)
6139: ot = OT_BYTE;
6140: else
6141: ot = dflag ? OT_LONG : OT_WORD;
1.1.1.7 root 6142: gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
1.1 root 6143: gen_op_andl_T0_ffff();
1.1.1.7 root 6144: gen_check_io(s, ot, pc_start - s->cs_base,
6145: SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6146: if (use_icount)
6147: gen_io_start();
6148: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6149: gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6150: gen_op_mov_reg_T1(ot, R_EAX);
6151: if (use_icount) {
6152: gen_io_end();
6153: gen_jmp(s, s->pc - s->cs_base);
6154: }
1.1 root 6155: break;
6156: case 0xee:
6157: case 0xef:
6158: if ((b & 1) == 0)
6159: ot = OT_BYTE;
6160: else
6161: ot = dflag ? OT_LONG : OT_WORD;
1.1.1.7 root 6162: gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
1.1 root 6163: gen_op_andl_T0_ffff();
1.1.1.7 root 6164: gen_check_io(s, ot, pc_start - s->cs_base,
6165: svm_is_rep(prefixes));
6166: gen_op_mov_TN_reg(ot, 1, R_EAX);
6167:
6168: if (use_icount)
6169: gen_io_start();
6170: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6171: tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6172: tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6173: gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6174: if (use_icount) {
6175: gen_io_end();
6176: gen_jmp(s, s->pc - s->cs_base);
6177: }
1.1 root 6178: break;
6179:
6180: /************************/
6181: /* control */
6182: case 0xc2: /* ret im */
6183: val = ldsw_code(s->pc);
6184: s->pc += 2;
6185: gen_pop_T0(s);
6186: if (CODE64(s) && s->dflag)
6187: s->dflag = 2;
6188: gen_stack_update(s, val + (2 << s->dflag));
6189: if (s->dflag == 0)
6190: gen_op_andl_T0_ffff();
6191: gen_op_jmp_T0();
6192: gen_eob(s);
6193: break;
6194: case 0xc3: /* ret */
6195: gen_pop_T0(s);
6196: gen_pop_update(s);
6197: if (s->dflag == 0)
6198: gen_op_andl_T0_ffff();
6199: gen_op_jmp_T0();
6200: gen_eob(s);
6201: break;
6202: case 0xca: /* lret im */
6203: val = ldsw_code(s->pc);
6204: s->pc += 2;
6205: do_lret:
6206: if (s->pe && !s->vm86) {
6207: if (s->cc_op != CC_OP_DYNAMIC)
6208: gen_op_set_cc_op(s->cc_op);
6209: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6210: gen_helper_lret_protected(tcg_const_i32(s->dflag),
6211: tcg_const_i32(val));
1.1 root 6212: } else {
6213: gen_stack_A0(s);
6214: /* pop offset */
1.1.1.7 root 6215: gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
1.1 root 6216: if (s->dflag == 0)
6217: gen_op_andl_T0_ffff();
6218: /* NOTE: keeping EIP updated is not a problem in case of
6219: exception */
6220: gen_op_jmp_T0();
6221: /* pop selector */
6222: gen_op_addl_A0_im(2 << s->dflag);
1.1.1.7 root 6223: gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6224: gen_op_movl_seg_T0_vm(R_CS);
1.1 root 6225: /* add stack offset */
6226: gen_stack_update(s, val + (4 << s->dflag));
6227: }
6228: gen_eob(s);
6229: break;
6230: case 0xcb: /* lret */
6231: val = 0;
6232: goto do_lret;
6233: case 0xcf: /* iret */
1.1.1.7 root 6234: gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
1.1 root 6235: if (!s->pe) {
6236: /* real mode */
1.1.1.7 root 6237: gen_helper_iret_real(tcg_const_i32(s->dflag));
1.1 root 6238: s->cc_op = CC_OP_EFLAGS;
6239: } else if (s->vm86) {
6240: if (s->iopl != 3) {
6241: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6242: } else {
1.1.1.7 root 6243: gen_helper_iret_real(tcg_const_i32(s->dflag));
1.1 root 6244: s->cc_op = CC_OP_EFLAGS;
6245: }
6246: } else {
6247: if (s->cc_op != CC_OP_DYNAMIC)
6248: gen_op_set_cc_op(s->cc_op);
6249: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6250: gen_helper_iret_protected(tcg_const_i32(s->dflag),
6251: tcg_const_i32(s->pc - s->cs_base));
1.1 root 6252: s->cc_op = CC_OP_EFLAGS;
6253: }
6254: gen_eob(s);
6255: break;
6256: case 0xe8: /* call im */
6257: {
6258: if (dflag)
6259: tval = (int32_t)insn_get(s, OT_LONG);
6260: else
6261: tval = (int16_t)insn_get(s, OT_WORD);
6262: next_eip = s->pc - s->cs_base;
6263: tval += next_eip;
6264: if (s->dflag == 0)
6265: tval &= 0xffff;
1.1.1.10 root 6266: else if(!CODE64(s))
6267: tval &= 0xffffffff;
1.1 root 6268: gen_movtl_T0_im(next_eip);
6269: gen_push_T0(s);
6270: gen_jmp(s, tval);
6271: }
6272: break;
6273: case 0x9a: /* lcall im */
6274: {
6275: unsigned int selector, offset;
1.1.1.6 root 6276:
1.1 root 6277: if (CODE64(s))
6278: goto illegal_op;
6279: ot = dflag ? OT_LONG : OT_WORD;
6280: offset = insn_get(s, ot);
6281: selector = insn_get(s, OT_WORD);
1.1.1.6 root 6282:
1.1 root 6283: gen_op_movl_T0_im(selector);
6284: gen_op_movl_T1_imu(offset);
6285: }
6286: goto do_lcall;
6287: case 0xe9: /* jmp im */
6288: if (dflag)
6289: tval = (int32_t)insn_get(s, OT_LONG);
6290: else
6291: tval = (int16_t)insn_get(s, OT_WORD);
6292: tval += s->pc - s->cs_base;
6293: if (s->dflag == 0)
6294: tval &= 0xffff;
1.1.1.7 root 6295: else if(!CODE64(s))
6296: tval &= 0xffffffff;
1.1 root 6297: gen_jmp(s, tval);
6298: break;
6299: case 0xea: /* ljmp im */
6300: {
6301: unsigned int selector, offset;
6302:
6303: if (CODE64(s))
6304: goto illegal_op;
6305: ot = dflag ? OT_LONG : OT_WORD;
6306: offset = insn_get(s, ot);
6307: selector = insn_get(s, OT_WORD);
1.1.1.6 root 6308:
1.1 root 6309: gen_op_movl_T0_im(selector);
6310: gen_op_movl_T1_imu(offset);
6311: }
6312: goto do_ljmp;
6313: case 0xeb: /* jmp Jb */
6314: tval = (int8_t)insn_get(s, OT_BYTE);
6315: tval += s->pc - s->cs_base;
6316: if (s->dflag == 0)
6317: tval &= 0xffff;
6318: gen_jmp(s, tval);
6319: break;
6320: case 0x70 ... 0x7f: /* jcc Jb */
6321: tval = (int8_t)insn_get(s, OT_BYTE);
6322: goto do_jcc;
6323: case 0x180 ... 0x18f: /* jcc Jv */
6324: if (dflag) {
6325: tval = (int32_t)insn_get(s, OT_LONG);
6326: } else {
1.1.1.6 root 6327: tval = (int16_t)insn_get(s, OT_WORD);
1.1 root 6328: }
6329: do_jcc:
6330: next_eip = s->pc - s->cs_base;
6331: tval += next_eip;
6332: if (s->dflag == 0)
6333: tval &= 0xffff;
6334: gen_jcc(s, b, tval, next_eip);
6335: break;
6336:
6337: case 0x190 ... 0x19f: /* setcc Gv */
6338: modrm = ldub_code(s->pc++);
6339: gen_setcc(s, b);
6340: gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6341: break;
6342: case 0x140 ... 0x14f: /* cmov Gv, Ev */
1.1.1.7 root 6343: {
6344: int l1;
6345: TCGv t0;
6346:
6347: ot = dflag + OT_WORD;
6348: modrm = ldub_code(s->pc++);
6349: reg = ((modrm >> 3) & 7) | rex_r;
6350: mod = (modrm >> 6) & 3;
6351: t0 = tcg_temp_local_new();
6352: if (mod != 3) {
6353: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6354: gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6355: } else {
6356: rm = (modrm & 7) | REX_B(s);
6357: gen_op_mov_v_reg(ot, t0, rm);
6358: }
6359: #ifdef TARGET_X86_64
6360: if (ot == OT_LONG) {
6361: /* XXX: specific Intel behaviour ? */
6362: l1 = gen_new_label();
6363: gen_jcc1(s, s->cc_op, b ^ 1, l1);
1.1.1.9 root 6364: tcg_gen_mov_tl(cpu_regs[reg], t0);
1.1.1.7 root 6365: gen_set_label(l1);
1.1.1.9 root 6366: tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
1.1.1.7 root 6367: } else
6368: #endif
6369: {
6370: l1 = gen_new_label();
6371: gen_jcc1(s, s->cc_op, b ^ 1, l1);
6372: gen_op_mov_reg_v(ot, reg, t0);
6373: gen_set_label(l1);
6374: }
6375: tcg_temp_free(t0);
1.1 root 6376: }
6377: break;
1.1.1.6 root 6378:
1.1 root 6379: /************************/
6380: /* flags */
6381: case 0x9c: /* pushf */
1.1.1.7 root 6382: gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
1.1 root 6383: if (s->vm86 && s->iopl != 3) {
6384: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6385: } else {
6386: if (s->cc_op != CC_OP_DYNAMIC)
6387: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6388: gen_helper_read_eflags(cpu_T[0]);
1.1 root 6389: gen_push_T0(s);
6390: }
6391: break;
6392: case 0x9d: /* popf */
1.1.1.7 root 6393: gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
1.1 root 6394: if (s->vm86 && s->iopl != 3) {
6395: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6396: } else {
6397: gen_pop_T0(s);
6398: if (s->cpl == 0) {
6399: if (s->dflag) {
1.1.1.7 root 6400: gen_helper_write_eflags(cpu_T[0],
6401: tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
1.1 root 6402: } else {
1.1.1.7 root 6403: gen_helper_write_eflags(cpu_T[0],
6404: tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
1.1 root 6405: }
6406: } else {
6407: if (s->cpl <= s->iopl) {
6408: if (s->dflag) {
1.1.1.7 root 6409: gen_helper_write_eflags(cpu_T[0],
6410: tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
1.1 root 6411: } else {
1.1.1.7 root 6412: gen_helper_write_eflags(cpu_T[0],
6413: tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
1.1 root 6414: }
6415: } else {
6416: if (s->dflag) {
1.1.1.7 root 6417: gen_helper_write_eflags(cpu_T[0],
6418: tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
1.1 root 6419: } else {
1.1.1.7 root 6420: gen_helper_write_eflags(cpu_T[0],
6421: tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
1.1 root 6422: }
6423: }
6424: }
6425: gen_pop_update(s);
6426: s->cc_op = CC_OP_EFLAGS;
6427: /* abort translation because TF flag may change */
6428: gen_jmp_im(s->pc - s->cs_base);
6429: gen_eob(s);
6430: }
6431: break;
6432: case 0x9e: /* sahf */
1.1.1.7 root 6433: if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
1.1 root 6434: goto illegal_op;
1.1.1.7 root 6435: gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
1.1 root 6436: if (s->cc_op != CC_OP_DYNAMIC)
6437: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6438: gen_compute_eflags(cpu_cc_src);
6439: tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6440: tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6441: tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
1.1 root 6442: s->cc_op = CC_OP_EFLAGS;
6443: break;
6444: case 0x9f: /* lahf */
1.1.1.7 root 6445: if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
1.1 root 6446: goto illegal_op;
6447: if (s->cc_op != CC_OP_DYNAMIC)
6448: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6449: gen_compute_eflags(cpu_T[0]);
6450: /* Note: gen_compute_eflags() only gives the condition codes */
6451: tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6452: gen_op_mov_reg_T0(OT_BYTE, R_AH);
1.1 root 6453: break;
6454: case 0xf5: /* cmc */
6455: if (s->cc_op != CC_OP_DYNAMIC)
6456: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6457: gen_compute_eflags(cpu_cc_src);
6458: tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
1.1 root 6459: s->cc_op = CC_OP_EFLAGS;
6460: break;
6461: case 0xf8: /* clc */
6462: if (s->cc_op != CC_OP_DYNAMIC)
6463: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6464: gen_compute_eflags(cpu_cc_src);
6465: tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
1.1 root 6466: s->cc_op = CC_OP_EFLAGS;
6467: break;
6468: case 0xf9: /* stc */
6469: if (s->cc_op != CC_OP_DYNAMIC)
6470: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6471: gen_compute_eflags(cpu_cc_src);
6472: tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
1.1 root 6473: s->cc_op = CC_OP_EFLAGS;
6474: break;
6475: case 0xfc: /* cld */
1.1.1.7 root 6476: tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6477: tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
1.1 root 6478: break;
6479: case 0xfd: /* std */
1.1.1.7 root 6480: tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6481: tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
1.1 root 6482: break;
6483:
6484: /************************/
6485: /* bit operations */
6486: case 0x1ba: /* bt/bts/btr/btc Gv, im */
6487: ot = dflag + OT_WORD;
6488: modrm = ldub_code(s->pc++);
1.1.1.3 root 6489: op = (modrm >> 3) & 7;
1.1 root 6490: mod = (modrm >> 6) & 3;
6491: rm = (modrm & 7) | REX_B(s);
6492: if (mod != 3) {
6493: s->rip_offset = 1;
6494: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 6495: gen_op_ld_T0_A0(ot + s->mem_index);
1.1 root 6496: } else {
1.1.1.7 root 6497: gen_op_mov_TN_reg(ot, 0, rm);
1.1 root 6498: }
6499: /* load shift */
6500: val = ldub_code(s->pc++);
6501: gen_op_movl_T1_im(val);
6502: if (op < 4)
6503: goto illegal_op;
6504: op -= 4;
1.1.1.7 root 6505: goto bt_op;
1.1 root 6506: case 0x1a3: /* bt Gv, Ev */
6507: op = 0;
6508: goto do_btx;
6509: case 0x1ab: /* bts */
6510: op = 1;
6511: goto do_btx;
6512: case 0x1b3: /* btr */
6513: op = 2;
6514: goto do_btx;
6515: case 0x1bb: /* btc */
6516: op = 3;
6517: do_btx:
6518: ot = dflag + OT_WORD;
6519: modrm = ldub_code(s->pc++);
6520: reg = ((modrm >> 3) & 7) | rex_r;
6521: mod = (modrm >> 6) & 3;
6522: rm = (modrm & 7) | REX_B(s);
1.1.1.7 root 6523: gen_op_mov_TN_reg(OT_LONG, 1, reg);
1.1 root 6524: if (mod != 3) {
6525: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6526: /* specific case: we need to add a displacement */
1.1.1.7 root 6527: gen_exts(ot, cpu_T[1]);
6528: tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6529: tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6530: tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6531: gen_op_ld_T0_A0(ot + s->mem_index);
1.1 root 6532: } else {
1.1.1.7 root 6533: gen_op_mov_TN_reg(ot, 0, rm);
6534: }
6535: bt_op:
6536: tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6537: switch(op) {
6538: case 0:
6539: tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6540: tcg_gen_movi_tl(cpu_cc_dst, 0);
6541: break;
6542: case 1:
6543: tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6544: tcg_gen_movi_tl(cpu_tmp0, 1);
6545: tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6546: tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6547: break;
6548: case 2:
6549: tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6550: tcg_gen_movi_tl(cpu_tmp0, 1);
6551: tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6552: tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6553: tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6554: break;
6555: default:
6556: case 3:
6557: tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6558: tcg_gen_movi_tl(cpu_tmp0, 1);
6559: tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6560: tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6561: break;
1.1 root 6562: }
6563: s->cc_op = CC_OP_SARB + ot;
6564: if (op != 0) {
6565: if (mod != 3)
1.1.1.7 root 6566: gen_op_st_T0_A0(ot + s->mem_index);
1.1 root 6567: else
1.1.1.7 root 6568: gen_op_mov_reg_T0(ot, rm);
6569: tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6570: tcg_gen_movi_tl(cpu_cc_dst, 0);
1.1 root 6571: }
6572: break;
6573: case 0x1bc: /* bsf */
6574: case 0x1bd: /* bsr */
1.1.1.7 root 6575: {
6576: int label1;
6577: TCGv t0;
6578:
6579: ot = dflag + OT_WORD;
6580: modrm = ldub_code(s->pc++);
6581: reg = ((modrm >> 3) & 7) | rex_r;
1.1.1.9 root 6582: gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
1.1.1.7 root 6583: gen_extu(ot, cpu_T[0]);
6584: t0 = tcg_temp_local_new();
6585: tcg_gen_mov_tl(t0, cpu_T[0]);
1.1.1.9 root 6586: if ((b & 1) && (prefixes & PREFIX_REPZ) &&
6587: (s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
6588: switch(ot) {
6589: case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6590: tcg_const_i32(16)); break;
6591: case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6592: tcg_const_i32(32)); break;
6593: case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6594: tcg_const_i32(64)); break;
6595: }
6596: gen_op_mov_reg_T0(ot, reg);
1.1.1.7 root 6597: } else {
1.1.1.9 root 6598: label1 = gen_new_label();
6599: tcg_gen_movi_tl(cpu_cc_dst, 0);
6600: tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6601: if (b & 1) {
6602: gen_helper_bsr(cpu_T[0], t0);
6603: } else {
6604: gen_helper_bsf(cpu_T[0], t0);
6605: }
6606: gen_op_mov_reg_T0(ot, reg);
6607: tcg_gen_movi_tl(cpu_cc_dst, 1);
6608: gen_set_label(label1);
6609: tcg_gen_discard_tl(cpu_cc_src);
6610: s->cc_op = CC_OP_LOGICB + ot;
1.1.1.7 root 6611: }
6612: tcg_temp_free(t0);
6613: }
1.1 root 6614: break;
6615: /************************/
6616: /* bcd */
6617: case 0x27: /* daa */
6618: if (CODE64(s))
6619: goto illegal_op;
6620: if (s->cc_op != CC_OP_DYNAMIC)
6621: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6622: gen_helper_daa();
1.1 root 6623: s->cc_op = CC_OP_EFLAGS;
6624: break;
6625: case 0x2f: /* das */
6626: if (CODE64(s))
6627: goto illegal_op;
6628: if (s->cc_op != CC_OP_DYNAMIC)
6629: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6630: gen_helper_das();
1.1 root 6631: s->cc_op = CC_OP_EFLAGS;
6632: break;
6633: case 0x37: /* aaa */
6634: if (CODE64(s))
6635: goto illegal_op;
6636: if (s->cc_op != CC_OP_DYNAMIC)
6637: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6638: gen_helper_aaa();
1.1 root 6639: s->cc_op = CC_OP_EFLAGS;
6640: break;
6641: case 0x3f: /* aas */
6642: if (CODE64(s))
6643: goto illegal_op;
6644: if (s->cc_op != CC_OP_DYNAMIC)
6645: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6646: gen_helper_aas();
1.1 root 6647: s->cc_op = CC_OP_EFLAGS;
6648: break;
6649: case 0xd4: /* aam */
6650: if (CODE64(s))
6651: goto illegal_op;
6652: val = ldub_code(s->pc++);
1.1.1.6 root 6653: if (val == 0) {
6654: gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6655: } else {
1.1.1.7 root 6656: gen_helper_aam(tcg_const_i32(val));
1.1.1.6 root 6657: s->cc_op = CC_OP_LOGICB;
6658: }
1.1 root 6659: break;
6660: case 0xd5: /* aad */
6661: if (CODE64(s))
6662: goto illegal_op;
6663: val = ldub_code(s->pc++);
1.1.1.7 root 6664: gen_helper_aad(tcg_const_i32(val));
1.1 root 6665: s->cc_op = CC_OP_LOGICB;
6666: break;
6667: /************************/
6668: /* misc */
6669: case 0x90: /* nop */
6670: /* XXX: correct lock test for all insn */
1.1.1.12! root 6671: if (prefixes & PREFIX_LOCK) {
1.1 root 6672: goto illegal_op;
1.1.1.12! root 6673: }
! 6674: /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
! 6675: if (REX_B(s)) {
! 6676: goto do_xchg_reg_eax;
! 6677: }
1.1.1.6 root 6678: if (prefixes & PREFIX_REPZ) {
6679: gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6680: }
1.1 root 6681: break;
6682: case 0x9b: /* fwait */
1.1.1.6 root 6683: if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
1.1 root 6684: (HF_MP_MASK | HF_TS_MASK)) {
6685: gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6686: } else {
6687: if (s->cc_op != CC_OP_DYNAMIC)
6688: gen_op_set_cc_op(s->cc_op);
6689: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6690: gen_helper_fwait();
1.1 root 6691: }
6692: break;
6693: case 0xcc: /* int3 */
6694: gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6695: break;
6696: case 0xcd: /* int N */
6697: val = ldub_code(s->pc++);
6698: if (s->vm86 && s->iopl != 3) {
1.1.1.6 root 6699: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
1.1 root 6700: } else {
6701: gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6702: }
6703: break;
6704: case 0xce: /* into */
6705: if (CODE64(s))
6706: goto illegal_op;
6707: if (s->cc_op != CC_OP_DYNAMIC)
6708: gen_op_set_cc_op(s->cc_op);
6709: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6710: gen_helper_into(tcg_const_i32(s->pc - pc_start));
1.1 root 6711: break;
1.1.1.7 root 6712: #ifdef WANT_ICEBP
1.1 root 6713: case 0xf1: /* icebp (undocumented, exits to external debugger) */
1.1.1.7 root 6714: gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
1.1 root 6715: #if 1
6716: gen_debug(s, pc_start - s->cs_base);
6717: #else
6718: /* start debug */
6719: tb_flush(cpu_single_env);
6720: cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6721: #endif
6722: break;
1.1.1.7 root 6723: #endif
1.1 root 6724: case 0xfa: /* cli */
6725: if (!s->vm86) {
6726: if (s->cpl <= s->iopl) {
1.1.1.7 root 6727: gen_helper_cli();
1.1 root 6728: } else {
6729: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6730: }
6731: } else {
6732: if (s->iopl == 3) {
1.1.1.7 root 6733: gen_helper_cli();
1.1 root 6734: } else {
6735: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6736: }
6737: }
6738: break;
6739: case 0xfb: /* sti */
6740: if (!s->vm86) {
6741: if (s->cpl <= s->iopl) {
6742: gen_sti:
1.1.1.7 root 6743: gen_helper_sti();
1.1 root 6744: /* interruptions are enabled only the first insn after sti */
6745: /* If several instructions disable interrupts, only the
6746: _first_ does it */
6747: if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
1.1.1.7 root 6748: gen_helper_set_inhibit_irq();
1.1 root 6749: /* give a chance to handle pending irqs */
6750: gen_jmp_im(s->pc - s->cs_base);
6751: gen_eob(s);
6752: } else {
6753: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6754: }
6755: } else {
6756: if (s->iopl == 3) {
6757: goto gen_sti;
6758: } else {
6759: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6760: }
6761: }
6762: break;
6763: case 0x62: /* bound */
6764: if (CODE64(s))
6765: goto illegal_op;
6766: ot = dflag ? OT_LONG : OT_WORD;
6767: modrm = ldub_code(s->pc++);
6768: reg = (modrm >> 3) & 7;
6769: mod = (modrm >> 6) & 3;
6770: if (mod == 3)
6771: goto illegal_op;
1.1.1.7 root 6772: gen_op_mov_TN_reg(ot, 0, reg);
1.1 root 6773: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6774: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6775: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
1.1 root 6776: if (ot == OT_WORD)
1.1.1.7 root 6777: gen_helper_boundw(cpu_A0, cpu_tmp2_i32);
1.1 root 6778: else
1.1.1.7 root 6779: gen_helper_boundl(cpu_A0, cpu_tmp2_i32);
1.1 root 6780: break;
6781: case 0x1c8 ... 0x1cf: /* bswap reg */
6782: reg = (b & 7) | REX_B(s);
6783: #ifdef TARGET_X86_64
6784: if (dflag == 2) {
1.1.1.7 root 6785: gen_op_mov_TN_reg(OT_QUAD, 0, reg);
1.1.1.8 root 6786: tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
1.1.1.7 root 6787: gen_op_mov_reg_T0(OT_QUAD, reg);
1.1.1.6 root 6788: } else
1.1.1.8 root 6789: #endif
1.1.1.7 root 6790: {
6791: gen_op_mov_TN_reg(OT_LONG, 0, reg);
1.1.1.8 root 6792: tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6793: tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
1.1.1.7 root 6794: gen_op_mov_reg_T0(OT_LONG, reg);
1.1 root 6795: }
6796: break;
6797: case 0xd6: /* salc */
6798: if (CODE64(s))
6799: goto illegal_op;
6800: if (s->cc_op != CC_OP_DYNAMIC)
6801: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6802: gen_compute_eflags_c(cpu_T[0]);
6803: tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6804: gen_op_mov_reg_T0(OT_BYTE, R_EAX);
1.1 root 6805: break;
6806: case 0xe0: /* loopnz */
6807: case 0xe1: /* loopz */
6808: case 0xe2: /* loop */
6809: case 0xe3: /* jecxz */
6810: {
1.1.1.7 root 6811: int l1, l2, l3;
1.1 root 6812:
6813: tval = (int8_t)insn_get(s, OT_BYTE);
6814: next_eip = s->pc - s->cs_base;
6815: tval += next_eip;
6816: if (s->dflag == 0)
6817: tval &= 0xffff;
1.1.1.6 root 6818:
1.1 root 6819: l1 = gen_new_label();
6820: l2 = gen_new_label();
1.1.1.7 root 6821: l3 = gen_new_label();
1.1 root 6822: b &= 3;
1.1.1.7 root 6823: switch(b) {
6824: case 0: /* loopnz */
6825: case 1: /* loopz */
6826: if (s->cc_op != CC_OP_DYNAMIC)
6827: gen_op_set_cc_op(s->cc_op);
6828: gen_op_add_reg_im(s->aflag, R_ECX, -1);
6829: gen_op_jz_ecx(s->aflag, l3);
6830: gen_compute_eflags(cpu_tmp0);
6831: tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6832: if (b == 0) {
6833: tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6834: } else {
6835: tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6836: }
6837: break;
6838: case 2: /* loop */
6839: gen_op_add_reg_im(s->aflag, R_ECX, -1);
6840: gen_op_jnz_ecx(s->aflag, l1);
6841: break;
6842: default:
6843: case 3: /* jcxz */
6844: gen_op_jz_ecx(s->aflag, l1);
6845: break;
1.1 root 6846: }
6847:
1.1.1.7 root 6848: gen_set_label(l3);
1.1 root 6849: gen_jmp_im(next_eip);
1.1.1.7 root 6850: tcg_gen_br(l2);
6851:
1.1 root 6852: gen_set_label(l1);
6853: gen_jmp_im(tval);
6854: gen_set_label(l2);
6855: gen_eob(s);
6856: }
6857: break;
6858: case 0x130: /* wrmsr */
6859: case 0x132: /* rdmsr */
6860: if (s->cpl != 0) {
6861: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6862: } else {
1.1.1.7 root 6863: if (s->cc_op != CC_OP_DYNAMIC)
6864: gen_op_set_cc_op(s->cc_op);
6865: gen_jmp_im(pc_start - s->cs_base);
1.1.1.6 root 6866: if (b & 2) {
1.1.1.7 root 6867: gen_helper_rdmsr();
1.1.1.6 root 6868: } else {
1.1.1.7 root 6869: gen_helper_wrmsr();
1.1.1.6 root 6870: }
1.1 root 6871: }
6872: break;
6873: case 0x131: /* rdtsc */
1.1.1.7 root 6874: if (s->cc_op != CC_OP_DYNAMIC)
6875: gen_op_set_cc_op(s->cc_op);
1.1 root 6876: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6877: if (use_icount)
6878: gen_io_start();
6879: gen_helper_rdtsc();
6880: if (use_icount) {
6881: gen_io_end();
6882: gen_jmp(s, s->pc - s->cs_base);
6883: }
1.1 root 6884: break;
1.1.1.6 root 6885: case 0x133: /* rdpmc */
1.1.1.7 root 6886: if (s->cc_op != CC_OP_DYNAMIC)
6887: gen_op_set_cc_op(s->cc_op);
1.1.1.6 root 6888: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6889: gen_helper_rdpmc();
1.1.1.6 root 6890: break;
1.1 root 6891: case 0x134: /* sysenter */
1.1.1.7 root 6892: /* For Intel SYSENTER is valid on 64-bit */
6893: if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
1.1 root 6894: goto illegal_op;
6895: if (!s->pe) {
6896: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6897: } else {
6898: if (s->cc_op != CC_OP_DYNAMIC) {
6899: gen_op_set_cc_op(s->cc_op);
6900: s->cc_op = CC_OP_DYNAMIC;
6901: }
6902: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6903: gen_helper_sysenter();
1.1 root 6904: gen_eob(s);
6905: }
6906: break;
6907: case 0x135: /* sysexit */
1.1.1.7 root 6908: /* For Intel SYSEXIT is valid on 64-bit */
6909: if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
1.1 root 6910: goto illegal_op;
6911: if (!s->pe) {
6912: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6913: } else {
6914: if (s->cc_op != CC_OP_DYNAMIC) {
6915: gen_op_set_cc_op(s->cc_op);
6916: s->cc_op = CC_OP_DYNAMIC;
6917: }
6918: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6919: gen_helper_sysexit(tcg_const_i32(dflag));
1.1 root 6920: gen_eob(s);
6921: }
6922: break;
6923: #ifdef TARGET_X86_64
6924: case 0x105: /* syscall */
6925: /* XXX: is it usable in real mode ? */
6926: if (s->cc_op != CC_OP_DYNAMIC) {
6927: gen_op_set_cc_op(s->cc_op);
6928: s->cc_op = CC_OP_DYNAMIC;
6929: }
6930: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6931: gen_helper_syscall(tcg_const_i32(s->pc - pc_start));
1.1 root 6932: gen_eob(s);
6933: break;
6934: case 0x107: /* sysret */
6935: if (!s->pe) {
6936: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6937: } else {
6938: if (s->cc_op != CC_OP_DYNAMIC) {
6939: gen_op_set_cc_op(s->cc_op);
6940: s->cc_op = CC_OP_DYNAMIC;
6941: }
6942: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6943: gen_helper_sysret(tcg_const_i32(s->dflag));
1.1 root 6944: /* condition codes are modified only in long mode */
6945: if (s->lma)
6946: s->cc_op = CC_OP_EFLAGS;
6947: gen_eob(s);
6948: }
6949: break;
6950: #endif
6951: case 0x1a2: /* cpuid */
1.1.1.7 root 6952: if (s->cc_op != CC_OP_DYNAMIC)
6953: gen_op_set_cc_op(s->cc_op);
6954: gen_jmp_im(pc_start - s->cs_base);
6955: gen_helper_cpuid();
1.1 root 6956: break;
6957: case 0xf4: /* hlt */
6958: if (s->cpl != 0) {
6959: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6960: } else {
6961: if (s->cc_op != CC_OP_DYNAMIC)
6962: gen_op_set_cc_op(s->cc_op);
1.1.1.7 root 6963: gen_jmp_im(pc_start - s->cs_base);
6964: gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
1.1 root 6965: s->is_jmp = 3;
6966: }
6967: break;
6968: case 0x100:
6969: modrm = ldub_code(s->pc++);
6970: mod = (modrm >> 6) & 3;
6971: op = (modrm >> 3) & 7;
6972: switch(op) {
6973: case 0: /* sldt */
6974: if (!s->pe || s->vm86)
6975: goto illegal_op;
1.1.1.7 root 6976: gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
6977: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
1.1 root 6978: ot = OT_WORD;
6979: if (mod == 3)
6980: ot += s->dflag;
6981: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6982: break;
6983: case 2: /* lldt */
6984: if (!s->pe || s->vm86)
6985: goto illegal_op;
6986: if (s->cpl != 0) {
6987: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6988: } else {
1.1.1.7 root 6989: gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
1.1 root 6990: gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6991: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 6992: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6993: gen_helper_lldt(cpu_tmp2_i32);
1.1 root 6994: }
6995: break;
6996: case 1: /* str */
6997: if (!s->pe || s->vm86)
6998: goto illegal_op;
1.1.1.7 root 6999: gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
7000: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
1.1 root 7001: ot = OT_WORD;
7002: if (mod == 3)
7003: ot += s->dflag;
7004: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
7005: break;
7006: case 3: /* ltr */
7007: if (!s->pe || s->vm86)
7008: goto illegal_op;
7009: if (s->cpl != 0) {
7010: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7011: } else {
1.1.1.7 root 7012: gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
1.1 root 7013: gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7014: gen_jmp_im(pc_start - s->cs_base);
1.1.1.7 root 7015: tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7016: gen_helper_ltr(cpu_tmp2_i32);
1.1 root 7017: }
7018: break;
7019: case 4: /* verr */
7020: case 5: /* verw */
7021: if (!s->pe || s->vm86)
7022: goto illegal_op;
7023: gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7024: if (s->cc_op != CC_OP_DYNAMIC)
7025: gen_op_set_cc_op(s->cc_op);
7026: if (op == 4)
1.1.1.7 root 7027: gen_helper_verr(cpu_T[0]);
1.1 root 7028: else
1.1.1.7 root 7029: gen_helper_verw(cpu_T[0]);
1.1 root 7030: s->cc_op = CC_OP_EFLAGS;
7031: break;
7032: default:
7033: goto illegal_op;
7034: }
7035: break;
7036: case 0x101:
7037: modrm = ldub_code(s->pc++);
7038: mod = (modrm >> 6) & 3;
7039: op = (modrm >> 3) & 7;
1.1.1.4 root 7040: rm = modrm & 7;
1.1 root 7041: switch(op) {
7042: case 0: /* sgdt */
7043: if (mod == 3)
7044: goto illegal_op;
1.1.1.7 root 7045: gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
1.1 root 7046: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 7047: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7048: gen_op_st_T0_A0(OT_WORD + s->mem_index);
1.1 root 7049: gen_add_A0_im(s, 2);
1.1.1.7 root 7050: tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
1.1 root 7051: if (!s->dflag)
7052: gen_op_andl_T0_im(0xffffff);
1.1.1.7 root 7053: gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
1.1 root 7054: break;
1.1.1.4 root 7055: case 1:
7056: if (mod == 3) {
7057: switch (rm) {
7058: case 0: /* monitor */
7059: if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7060: s->cpl != 0)
7061: goto illegal_op;
1.1.1.7 root 7062: if (s->cc_op != CC_OP_DYNAMIC)
7063: gen_op_set_cc_op(s->cc_op);
1.1.1.4 root 7064: gen_jmp_im(pc_start - s->cs_base);
7065: #ifdef TARGET_X86_64
7066: if (s->aflag == 2) {
1.1.1.7 root 7067: gen_op_movq_A0_reg(R_EAX);
1.1.1.6 root 7068: } else
1.1.1.4 root 7069: #endif
7070: {
1.1.1.7 root 7071: gen_op_movl_A0_reg(R_EAX);
1.1.1.4 root 7072: if (s->aflag == 0)
7073: gen_op_andl_A0_ffff();
7074: }
7075: gen_add_A0_ds_seg(s);
1.1.1.7 root 7076: gen_helper_monitor(cpu_A0);
1.1.1.4 root 7077: break;
7078: case 1: /* mwait */
7079: if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7080: s->cpl != 0)
7081: goto illegal_op;
7082: if (s->cc_op != CC_OP_DYNAMIC) {
7083: gen_op_set_cc_op(s->cc_op);
7084: s->cc_op = CC_OP_DYNAMIC;
7085: }
1.1.1.7 root 7086: gen_jmp_im(pc_start - s->cs_base);
7087: gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
1.1.1.4 root 7088: gen_eob(s);
7089: break;
7090: default:
7091: goto illegal_op;
7092: }
7093: } else { /* sidt */
1.1.1.7 root 7094: gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
1.1.1.4 root 7095: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 7096: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7097: gen_op_st_T0_A0(OT_WORD + s->mem_index);
1.1.1.4 root 7098: gen_add_A0_im(s, 2);
1.1.1.7 root 7099: tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
1.1.1.4 root 7100: if (!s->dflag)
7101: gen_op_andl_T0_im(0xffffff);
1.1.1.7 root 7102: gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
1.1.1.4 root 7103: }
7104: break;
1.1 root 7105: case 2: /* lgdt */
7106: case 3: /* lidt */
1.1.1.6 root 7107: if (mod == 3) {
1.1.1.7 root 7108: if (s->cc_op != CC_OP_DYNAMIC)
7109: gen_op_set_cc_op(s->cc_op);
7110: gen_jmp_im(pc_start - s->cs_base);
1.1.1.6 root 7111: switch(rm) {
7112: case 0: /* VMRUN */
1.1.1.7 root 7113: if (!(s->flags & HF_SVME_MASK) || !s->pe)
7114: goto illegal_op;
7115: if (s->cpl != 0) {
7116: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
1.1.1.6 root 7117: break;
1.1.1.7 root 7118: } else {
7119: gen_helper_vmrun(tcg_const_i32(s->aflag),
7120: tcg_const_i32(s->pc - pc_start));
7121: tcg_gen_exit_tb(0);
7122: s->is_jmp = 3;
7123: }
1.1.1.6 root 7124: break;
7125: case 1: /* VMMCALL */
1.1.1.7 root 7126: if (!(s->flags & HF_SVME_MASK))
7127: goto illegal_op;
7128: gen_helper_vmmcall();
1.1.1.6 root 7129: break;
7130: case 2: /* VMLOAD */
1.1.1.7 root 7131: if (!(s->flags & HF_SVME_MASK) || !s->pe)
7132: goto illegal_op;
7133: if (s->cpl != 0) {
7134: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7135: break;
7136: } else {
7137: gen_helper_vmload(tcg_const_i32(s->aflag));
7138: }
1.1.1.6 root 7139: break;
7140: case 3: /* VMSAVE */
1.1.1.7 root 7141: if (!(s->flags & HF_SVME_MASK) || !s->pe)
7142: goto illegal_op;
7143: if (s->cpl != 0) {
7144: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7145: break;
7146: } else {
7147: gen_helper_vmsave(tcg_const_i32(s->aflag));
7148: }
1.1.1.6 root 7149: break;
7150: case 4: /* STGI */
1.1.1.7 root 7151: if ((!(s->flags & HF_SVME_MASK) &&
7152: !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7153: !s->pe)
7154: goto illegal_op;
7155: if (s->cpl != 0) {
7156: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7157: break;
7158: } else {
7159: gen_helper_stgi();
7160: }
1.1.1.6 root 7161: break;
7162: case 5: /* CLGI */
1.1.1.7 root 7163: if (!(s->flags & HF_SVME_MASK) || !s->pe)
7164: goto illegal_op;
7165: if (s->cpl != 0) {
7166: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7167: break;
7168: } else {
7169: gen_helper_clgi();
7170: }
1.1.1.6 root 7171: break;
7172: case 6: /* SKINIT */
1.1.1.7 root 7173: if ((!(s->flags & HF_SVME_MASK) &&
7174: !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7175: !s->pe)
7176: goto illegal_op;
7177: gen_helper_skinit();
1.1.1.6 root 7178: break;
7179: case 7: /* INVLPGA */
1.1.1.7 root 7180: if (!(s->flags & HF_SVME_MASK) || !s->pe)
7181: goto illegal_op;
7182: if (s->cpl != 0) {
7183: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7184: break;
7185: } else {
7186: gen_helper_invlpga(tcg_const_i32(s->aflag));
7187: }
1.1.1.6 root 7188: break;
7189: default:
7190: goto illegal_op;
7191: }
7192: } else if (s->cpl != 0) {
1.1 root 7193: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7194: } else {
1.1.1.7 root 7195: gen_svm_check_intercept(s, pc_start,
7196: op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
1.1 root 7197: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 7198: gen_op_ld_T1_A0(OT_WORD + s->mem_index);
1.1 root 7199: gen_add_A0_im(s, 2);
1.1.1.7 root 7200: gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
1.1 root 7201: if (!s->dflag)
7202: gen_op_andl_T0_im(0xffffff);
7203: if (op == 2) {
1.1.1.7 root 7204: tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7205: tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
1.1 root 7206: } else {
1.1.1.7 root 7207: tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7208: tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
1.1 root 7209: }
7210: }
7211: break;
7212: case 4: /* smsw */
1.1.1.7 root 7213: gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
1.1.1.9 root 7214: #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
1.1.1.7 root 7215: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7216: #else
7217: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7218: #endif
1.1 root 7219: gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7220: break;
7221: case 6: /* lmsw */
7222: if (s->cpl != 0) {
7223: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7224: } else {
1.1.1.7 root 7225: gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
1.1 root 7226: gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
1.1.1.7 root 7227: gen_helper_lmsw(cpu_T[0]);
1.1 root 7228: gen_jmp_im(s->pc - s->cs_base);
7229: gen_eob(s);
7230: }
7231: break;
1.1.1.9 root 7232: case 7:
7233: if (mod != 3) { /* invlpg */
7234: if (s->cpl != 0) {
7235: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7236: } else {
7237: if (s->cc_op != CC_OP_DYNAMIC)
7238: gen_op_set_cc_op(s->cc_op);
7239: gen_jmp_im(pc_start - s->cs_base);
7240: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7241: gen_helper_invlpg(cpu_A0);
7242: gen_jmp_im(s->pc - s->cs_base);
7243: gen_eob(s);
7244: }
1.1 root 7245: } else {
1.1.1.9 root 7246: switch (rm) {
7247: case 0: /* swapgs */
1.1 root 7248: #ifdef TARGET_X86_64
1.1.1.9 root 7249: if (CODE64(s)) {
7250: if (s->cpl != 0) {
7251: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7252: } else {
7253: tcg_gen_ld_tl(cpu_T[0], cpu_env,
7254: offsetof(CPUX86State,segs[R_GS].base));
7255: tcg_gen_ld_tl(cpu_T[1], cpu_env,
7256: offsetof(CPUX86State,kernelgsbase));
7257: tcg_gen_st_tl(cpu_T[1], cpu_env,
7258: offsetof(CPUX86State,segs[R_GS].base));
7259: tcg_gen_st_tl(cpu_T[0], cpu_env,
7260: offsetof(CPUX86State,kernelgsbase));
7261: }
1.1.1.6 root 7262: } else
1.1 root 7263: #endif
7264: {
7265: goto illegal_op;
7266: }
1.1.1.9 root 7267: break;
7268: case 1: /* rdtscp */
7269: if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7270: goto illegal_op;
1.1.1.7 root 7271: if (s->cc_op != CC_OP_DYNAMIC)
7272: gen_op_set_cc_op(s->cc_op);
7273: gen_jmp_im(pc_start - s->cs_base);
1.1.1.9 root 7274: if (use_icount)
7275: gen_io_start();
7276: gen_helper_rdtscp();
7277: if (use_icount) {
7278: gen_io_end();
7279: gen_jmp(s, s->pc - s->cs_base);
7280: }
7281: break;
7282: default:
7283: goto illegal_op;
1.1 root 7284: }
7285: }
7286: break;
7287: default:
7288: goto illegal_op;
7289: }
7290: break;
7291: case 0x108: /* invd */
7292: case 0x109: /* wbinvd */
7293: if (s->cpl != 0) {
7294: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7295: } else {
1.1.1.7 root 7296: gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
1.1 root 7297: /* nothing to do */
7298: }
7299: break;
7300: case 0x63: /* arpl or movslS (x86_64) */
7301: #ifdef TARGET_X86_64
7302: if (CODE64(s)) {
7303: int d_ot;
7304: /* d_ot is the size of destination */
7305: d_ot = dflag + OT_WORD;
7306:
7307: modrm = ldub_code(s->pc++);
7308: reg = ((modrm >> 3) & 7) | rex_r;
7309: mod = (modrm >> 6) & 3;
7310: rm = (modrm & 7) | REX_B(s);
1.1.1.6 root 7311:
1.1 root 7312: if (mod == 3) {
1.1.1.7 root 7313: gen_op_mov_TN_reg(OT_LONG, 0, rm);
1.1 root 7314: /* sign extend */
7315: if (d_ot == OT_QUAD)
1.1.1.7 root 7316: tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7317: gen_op_mov_reg_T0(d_ot, reg);
1.1 root 7318: } else {
7319: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7320: if (d_ot == OT_QUAD) {
1.1.1.7 root 7321: gen_op_lds_T0_A0(OT_LONG + s->mem_index);
1.1 root 7322: } else {
1.1.1.7 root 7323: gen_op_ld_T0_A0(OT_LONG + s->mem_index);
1.1 root 7324: }
1.1.1.7 root 7325: gen_op_mov_reg_T0(d_ot, reg);
1.1 root 7326: }
1.1.1.6 root 7327: } else
1.1 root 7328: #endif
7329: {
1.1.1.7 root 7330: int label1;
1.1.1.9 root 7331: TCGv t0, t1, t2, a0;
1.1.1.7 root 7332:
1.1 root 7333: if (!s->pe || s->vm86)
7334: goto illegal_op;
1.1.1.7 root 7335: t0 = tcg_temp_local_new();
7336: t1 = tcg_temp_local_new();
7337: t2 = tcg_temp_local_new();
7338: ot = OT_WORD;
1.1 root 7339: modrm = ldub_code(s->pc++);
7340: reg = (modrm >> 3) & 7;
7341: mod = (modrm >> 6) & 3;
7342: rm = modrm & 7;
7343: if (mod != 3) {
7344: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 7345: gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
1.1.1.9 root 7346: a0 = tcg_temp_local_new();
7347: tcg_gen_mov_tl(a0, cpu_A0);
1.1 root 7348: } else {
1.1.1.7 root 7349: gen_op_mov_v_reg(ot, t0, rm);
1.1.1.9 root 7350: TCGV_UNUSED(a0);
1.1 root 7351: }
1.1.1.7 root 7352: gen_op_mov_v_reg(ot, t1, reg);
7353: tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7354: tcg_gen_andi_tl(t1, t1, 3);
7355: tcg_gen_movi_tl(t2, 0);
7356: label1 = gen_new_label();
7357: tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7358: tcg_gen_andi_tl(t0, t0, ~3);
7359: tcg_gen_or_tl(t0, t0, t1);
7360: tcg_gen_movi_tl(t2, CC_Z);
7361: gen_set_label(label1);
1.1 root 7362: if (mod != 3) {
1.1.1.9 root 7363: gen_op_st_v(ot + s->mem_index, t0, a0);
7364: tcg_temp_free(a0);
7365: } else {
1.1.1.7 root 7366: gen_op_mov_reg_v(ot, rm, t0);
1.1 root 7367: }
1.1.1.7 root 7368: if (s->cc_op != CC_OP_DYNAMIC)
7369: gen_op_set_cc_op(s->cc_op);
7370: gen_compute_eflags(cpu_cc_src);
7371: tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7372: tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7373: s->cc_op = CC_OP_EFLAGS;
7374: tcg_temp_free(t0);
7375: tcg_temp_free(t1);
7376: tcg_temp_free(t2);
1.1 root 7377: }
7378: break;
7379: case 0x102: /* lar */
7380: case 0x103: /* lsl */
1.1.1.7 root 7381: {
7382: int label1;
7383: TCGv t0;
7384: if (!s->pe || s->vm86)
7385: goto illegal_op;
7386: ot = dflag ? OT_LONG : OT_WORD;
7387: modrm = ldub_code(s->pc++);
7388: reg = ((modrm >> 3) & 7) | rex_r;
7389: gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7390: t0 = tcg_temp_local_new();
7391: if (s->cc_op != CC_OP_DYNAMIC)
7392: gen_op_set_cc_op(s->cc_op);
7393: if (b == 0x102)
7394: gen_helper_lar(t0, cpu_T[0]);
7395: else
7396: gen_helper_lsl(t0, cpu_T[0]);
7397: tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7398: label1 = gen_new_label();
7399: tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7400: gen_op_mov_reg_v(ot, reg, t0);
7401: gen_set_label(label1);
7402: s->cc_op = CC_OP_EFLAGS;
7403: tcg_temp_free(t0);
7404: }
1.1 root 7405: break;
7406: case 0x118:
7407: modrm = ldub_code(s->pc++);
7408: mod = (modrm >> 6) & 3;
7409: op = (modrm >> 3) & 7;
7410: switch(op) {
7411: case 0: /* prefetchnta */
7412: case 1: /* prefetchnt0 */
7413: case 2: /* prefetchnt0 */
7414: case 3: /* prefetchnt0 */
7415: if (mod == 3)
7416: goto illegal_op;
7417: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7418: /* nothing more to do */
7419: break;
1.1.1.5 root 7420: default: /* nop (multi byte) */
7421: gen_nop_modrm(s, modrm);
7422: break;
1.1 root 7423: }
7424: break;
1.1.1.5 root 7425: case 0x119 ... 0x11f: /* nop (multi byte) */
7426: modrm = ldub_code(s->pc++);
7427: gen_nop_modrm(s, modrm);
7428: break;
1.1 root 7429: case 0x120: /* mov reg, crN */
7430: case 0x122: /* mov crN, reg */
7431: if (s->cpl != 0) {
7432: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7433: } else {
7434: modrm = ldub_code(s->pc++);
7435: if ((modrm & 0xc0) != 0xc0)
7436: goto illegal_op;
7437: rm = (modrm & 7) | REX_B(s);
7438: reg = ((modrm >> 3) & 7) | rex_r;
7439: if (CODE64(s))
7440: ot = OT_QUAD;
7441: else
7442: ot = OT_LONG;
1.1.1.9 root 7443: if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7444: (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7445: reg = 8;
7446: }
1.1 root 7447: switch(reg) {
7448: case 0:
7449: case 2:
7450: case 3:
7451: case 4:
7452: case 8:
1.1.1.7 root 7453: if (s->cc_op != CC_OP_DYNAMIC)
7454: gen_op_set_cc_op(s->cc_op);
7455: gen_jmp_im(pc_start - s->cs_base);
1.1 root 7456: if (b & 2) {
1.1.1.7 root 7457: gen_op_mov_TN_reg(ot, 0, rm);
7458: gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
1.1 root 7459: gen_jmp_im(s->pc - s->cs_base);
7460: gen_eob(s);
7461: } else {
1.1.1.7 root 7462: gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
7463: gen_op_mov_reg_T0(ot, rm);
1.1 root 7464: }
7465: break;
7466: default:
7467: goto illegal_op;
7468: }
7469: }
7470: break;
7471: case 0x121: /* mov reg, drN */
7472: case 0x123: /* mov drN, reg */
7473: if (s->cpl != 0) {
7474: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7475: } else {
7476: modrm = ldub_code(s->pc++);
7477: if ((modrm & 0xc0) != 0xc0)
7478: goto illegal_op;
7479: rm = (modrm & 7) | REX_B(s);
7480: reg = ((modrm >> 3) & 7) | rex_r;
7481: if (CODE64(s))
7482: ot = OT_QUAD;
7483: else
7484: ot = OT_LONG;
7485: /* XXX: do it dynamically with CR4.DE bit */
7486: if (reg == 4 || reg == 5 || reg >= 8)
7487: goto illegal_op;
7488: if (b & 2) {
1.1.1.6 root 7489: gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
1.1.1.7 root 7490: gen_op_mov_TN_reg(ot, 0, rm);
7491: gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
1.1 root 7492: gen_jmp_im(s->pc - s->cs_base);
7493: gen_eob(s);
7494: } else {
1.1.1.6 root 7495: gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
1.1.1.7 root 7496: tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7497: gen_op_mov_reg_T0(ot, rm);
1.1 root 7498: }
7499: }
7500: break;
7501: case 0x106: /* clts */
7502: if (s->cpl != 0) {
7503: gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7504: } else {
1.1.1.6 root 7505: gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
1.1.1.7 root 7506: gen_helper_clts();
1.1 root 7507: /* abort block because static cpu state changed */
7508: gen_jmp_im(s->pc - s->cs_base);
7509: gen_eob(s);
7510: }
7511: break;
1.1.1.7 root 7512: /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
1.1 root 7513: case 0x1c3: /* MOVNTI reg, mem */
7514: if (!(s->cpuid_features & CPUID_SSE2))
7515: goto illegal_op;
7516: ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7517: modrm = ldub_code(s->pc++);
7518: mod = (modrm >> 6) & 3;
7519: if (mod == 3)
7520: goto illegal_op;
7521: reg = ((modrm >> 3) & 7) | rex_r;
7522: /* generate a generic store */
7523: gen_ldst_modrm(s, modrm, ot, reg, 1);
7524: break;
7525: case 0x1ae:
7526: modrm = ldub_code(s->pc++);
7527: mod = (modrm >> 6) & 3;
7528: op = (modrm >> 3) & 7;
7529: switch(op) {
7530: case 0: /* fxsave */
1.1.1.6 root 7531: if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
1.1.1.9 root 7532: (s->prefix & PREFIX_LOCK))
1.1 root 7533: goto illegal_op;
1.1.1.9 root 7534: if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
1.1.1.3 root 7535: gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7536: break;
7537: }
1.1 root 7538: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 7539: if (s->cc_op != CC_OP_DYNAMIC)
7540: gen_op_set_cc_op(s->cc_op);
7541: gen_jmp_im(pc_start - s->cs_base);
7542: gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2)));
1.1 root 7543: break;
7544: case 1: /* fxrstor */
1.1.1.6 root 7545: if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
1.1.1.9 root 7546: (s->prefix & PREFIX_LOCK))
1.1 root 7547: goto illegal_op;
1.1.1.9 root 7548: if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
1.1.1.3 root 7549: gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7550: break;
7551: }
1.1 root 7552: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1.1.1.7 root 7553: if (s->cc_op != CC_OP_DYNAMIC)
7554: gen_op_set_cc_op(s->cc_op);
7555: gen_jmp_im(pc_start - s->cs_base);
7556: gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2)));
1.1 root 7557: break;
7558: case 2: /* ldmxcsr */
7559: case 3: /* stmxcsr */
7560: if (s->flags & HF_TS_MASK) {
7561: gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7562: break;
7563: }
7564: if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7565: mod == 3)
7566: goto illegal_op;
7567: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7568: if (op == 2) {
1.1.1.7 root 7569: gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7570: tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
1.1 root 7571: } else {
1.1.1.7 root 7572: tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7573: gen_op_st_T0_A0(OT_LONG + s->mem_index);
1.1 root 7574: }
7575: break;
7576: case 5: /* lfence */
7577: case 6: /* mfence */
7578: if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
7579: goto illegal_op;
7580: break;
7581: case 7: /* sfence / clflush */
7582: if ((modrm & 0xc7) == 0xc0) {
7583: /* sfence */
1.1.1.7 root 7584: /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
1.1 root 7585: if (!(s->cpuid_features & CPUID_SSE))
7586: goto illegal_op;
7587: } else {
7588: /* clflush */
7589: if (!(s->cpuid_features & CPUID_CLFLUSH))
7590: goto illegal_op;
7591: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7592: }
7593: break;
7594: default:
7595: goto illegal_op;
7596: }
7597: break;
1.1.1.7 root 7598: case 0x10d: /* 3DNow! prefetch(w) */
1.1 root 7599: modrm = ldub_code(s->pc++);
1.1.1.7 root 7600: mod = (modrm >> 6) & 3;
7601: if (mod == 3)
7602: goto illegal_op;
1.1 root 7603: gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7604: /* ignore for now */
7605: break;
1.1.1.5 root 7606: case 0x1aa: /* rsm */
1.1.1.7 root 7607: gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
1.1.1.5 root 7608: if (!(s->flags & HF_SMM_MASK))
7609: goto illegal_op;
7610: if (s->cc_op != CC_OP_DYNAMIC) {
7611: gen_op_set_cc_op(s->cc_op);
7612: s->cc_op = CC_OP_DYNAMIC;
7613: }
7614: gen_jmp_im(s->pc - s->cs_base);
1.1.1.7 root 7615: gen_helper_rsm();
1.1.1.5 root 7616: gen_eob(s);
7617: break;
1.1.1.7 root 7618: case 0x1b8: /* SSE4.2 popcnt */
7619: if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7620: PREFIX_REPZ)
7621: goto illegal_op;
7622: if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7623: goto illegal_op;
7624:
7625: modrm = ldub_code(s->pc++);
7626: reg = ((modrm >> 3) & 7);
7627:
7628: if (s->prefix & PREFIX_DATA)
7629: ot = OT_WORD;
7630: else if (s->dflag != 2)
7631: ot = OT_LONG;
7632: else
7633: ot = OT_QUAD;
7634:
7635: gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7636: gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot));
7637: gen_op_mov_reg_T0(ot, reg);
7638:
7639: s->cc_op = CC_OP_EFLAGS;
7640: break;
7641: case 0x10e ... 0x10f:
7642: /* 3DNow! instructions, ignore prefixes */
7643: s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
1.1 root 7644: case 0x110 ... 0x117:
7645: case 0x128 ... 0x12f:
1.1.1.7 root 7646: case 0x138 ... 0x13a:
1.1.1.9 root 7647: case 0x150 ... 0x179:
1.1 root 7648: case 0x17c ... 0x17f:
7649: case 0x1c2:
7650: case 0x1c4 ... 0x1c6:
7651: case 0x1d0 ... 0x1fe:
7652: gen_sse(s, b, pc_start, rex_r);
7653: break;
7654: default:
7655: goto illegal_op;
7656: }
7657: /* lock generation */
7658: if (s->prefix & PREFIX_LOCK)
1.1.1.7 root 7659: gen_helper_unlock();
1.1 root 7660: return s->pc;
7661: illegal_op:
7662: if (s->prefix & PREFIX_LOCK)
1.1.1.7 root 7663: gen_helper_unlock();
1.1 root 7664: /* XXX: ensure that no lock was generated */
7665: gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7666: return s->pc;
7667: }
7668:
7669: void optimize_flags_init(void)
7670: {
1.1.1.7 root 7671: #if TCG_TARGET_REG_BITS == 32
7672: assert(sizeof(CCTable) == (1 << 3));
7673: #else
7674: assert(sizeof(CCTable) == (1 << 4));
7675: #endif
7676: cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7677: cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7678: offsetof(CPUState, cc_op), "cc_op");
7679: cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
7680: "cc_src");
7681: cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
7682: "cc_dst");
7683: cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp),
7684: "cc_tmp");
7685:
1.1.1.9 root 7686: #ifdef TARGET_X86_64
7687: cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
7688: offsetof(CPUState, regs[R_EAX]), "rax");
7689: cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
7690: offsetof(CPUState, regs[R_ECX]), "rcx");
7691: cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
7692: offsetof(CPUState, regs[R_EDX]), "rdx");
7693: cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
7694: offsetof(CPUState, regs[R_EBX]), "rbx");
7695: cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
7696: offsetof(CPUState, regs[R_ESP]), "rsp");
7697: cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
7698: offsetof(CPUState, regs[R_EBP]), "rbp");
7699: cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
7700: offsetof(CPUState, regs[R_ESI]), "rsi");
7701: cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
7702: offsetof(CPUState, regs[R_EDI]), "rdi");
7703: cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
7704: offsetof(CPUState, regs[8]), "r8");
7705: cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
7706: offsetof(CPUState, regs[9]), "r9");
7707: cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
7708: offsetof(CPUState, regs[10]), "r10");
7709: cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
7710: offsetof(CPUState, regs[11]), "r11");
7711: cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
7712: offsetof(CPUState, regs[12]), "r12");
7713: cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
7714: offsetof(CPUState, regs[13]), "r13");
7715: cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
7716: offsetof(CPUState, regs[14]), "r14");
7717: cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
7718: offsetof(CPUState, regs[15]), "r15");
7719: #else
7720: cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
7721: offsetof(CPUState, regs[R_EAX]), "eax");
7722: cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
7723: offsetof(CPUState, regs[R_ECX]), "ecx");
7724: cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
7725: offsetof(CPUState, regs[R_EDX]), "edx");
7726: cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
7727: offsetof(CPUState, regs[R_EBX]), "ebx");
7728: cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
7729: offsetof(CPUState, regs[R_ESP]), "esp");
7730: cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
7731: offsetof(CPUState, regs[R_EBP]), "ebp");
7732: cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
7733: offsetof(CPUState, regs[R_ESI]), "esi");
7734: cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
7735: offsetof(CPUState, regs[R_EDI]), "edi");
7736: #endif
7737:
1.1.1.7 root 7738: /* register helpers */
7739: #define GEN_HELPER 2
7740: #include "helper.h"
1.1 root 7741: }
7742:
7743: /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7744: basic block 'tb'. If search_pc is TRUE, also generate PC
7745: information for each intermediate instruction. */
1.1.1.7 root 7746: static inline void gen_intermediate_code_internal(CPUState *env,
7747: TranslationBlock *tb,
7748: int search_pc)
1.1 root 7749: {
7750: DisasContext dc1, *dc = &dc1;
7751: target_ulong pc_ptr;
7752: uint16_t *gen_opc_end;
1.1.1.7 root 7753: CPUBreakpoint *bp;
1.1.1.6 root 7754: int j, lj, cflags;
7755: uint64_t flags;
1.1 root 7756: target_ulong pc_start;
7757: target_ulong cs_base;
1.1.1.7 root 7758: int num_insns;
7759: int max_insns;
1.1.1.6 root 7760:
1.1 root 7761: /* generate intermediate code */
7762: pc_start = tb->pc;
7763: cs_base = tb->cs_base;
7764: flags = tb->flags;
7765: cflags = tb->cflags;
7766:
7767: dc->pe = (flags >> HF_PE_SHIFT) & 1;
7768: dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7769: dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7770: dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7771: dc->f_st = 0;
7772: dc->vm86 = (flags >> VM_SHIFT) & 1;
7773: dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7774: dc->iopl = (flags >> IOPL_SHIFT) & 3;
7775: dc->tf = (flags >> TF_SHIFT) & 1;
7776: dc->singlestep_enabled = env->singlestep_enabled;
7777: dc->cc_op = CC_OP_DYNAMIC;
7778: dc->cs_base = cs_base;
7779: dc->tb = tb;
7780: dc->popl_esp_hack = 0;
7781: /* select memory access functions */
7782: dc->mem_index = 0;
7783: if (flags & HF_SOFTMMU_MASK) {
7784: if (dc->cpl == 3)
7785: dc->mem_index = 2 * 4;
7786: else
7787: dc->mem_index = 1 * 4;
7788: }
7789: dc->cpuid_features = env->cpuid_features;
1.1.1.4 root 7790: dc->cpuid_ext_features = env->cpuid_ext_features;
1.1.1.7 root 7791: dc->cpuid_ext2_features = env->cpuid_ext2_features;
7792: dc->cpuid_ext3_features = env->cpuid_ext3_features;
1.1 root 7793: #ifdef TARGET_X86_64
7794: dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7795: dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7796: #endif
7797: dc->flags = flags;
7798: dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7799: (flags & HF_INHIBIT_IRQ_MASK)
7800: #ifndef CONFIG_SOFTMMU
7801: || (flags & HF_SOFTMMU_MASK)
7802: #endif
7803: );
7804: #if 0
7805: /* check addseg logic */
7806: if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7807: printf("ERROR addseg\n");
7808: #endif
7809:
1.1.1.7 root 7810: cpu_T[0] = tcg_temp_new();
7811: cpu_T[1] = tcg_temp_new();
7812: cpu_A0 = tcg_temp_new();
7813: cpu_T3 = tcg_temp_new();
7814:
7815: cpu_tmp0 = tcg_temp_new();
7816: cpu_tmp1_i64 = tcg_temp_new_i64();
7817: cpu_tmp2_i32 = tcg_temp_new_i32();
7818: cpu_tmp3_i32 = tcg_temp_new_i32();
7819: cpu_tmp4 = tcg_temp_new();
7820: cpu_tmp5 = tcg_temp_new();
7821: cpu_ptr0 = tcg_temp_new_ptr();
7822: cpu_ptr1 = tcg_temp_new_ptr();
7823:
1.1 root 7824: gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7825:
7826: dc->is_jmp = DISAS_NEXT;
7827: pc_ptr = pc_start;
7828: lj = -1;
1.1.1.7 root 7829: num_insns = 0;
7830: max_insns = tb->cflags & CF_COUNT_MASK;
7831: if (max_insns == 0)
7832: max_insns = CF_COUNT_MASK;
1.1 root 7833:
1.1.1.7 root 7834: gen_icount_start();
1.1 root 7835: for(;;) {
1.1.1.9 root 7836: if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
7837: QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1.1.1.8 root 7838: if (bp->pc == pc_ptr &&
7839: !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
1.1 root 7840: gen_debug(dc, pc_ptr - dc->cs_base);
7841: break;
7842: }
7843: }
7844: }
7845: if (search_pc) {
7846: j = gen_opc_ptr - gen_opc_buf;
7847: if (lj < j) {
7848: lj++;
7849: while (lj < j)
7850: gen_opc_instr_start[lj++] = 0;
7851: }
7852: gen_opc_pc[lj] = pc_ptr;
7853: gen_opc_cc_op[lj] = dc->cc_op;
7854: gen_opc_instr_start[lj] = 1;
1.1.1.7 root 7855: gen_opc_icount[lj] = num_insns;
1.1 root 7856: }
1.1.1.7 root 7857: if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7858: gen_io_start();
7859:
1.1 root 7860: pc_ptr = disas_insn(dc, pc_ptr);
1.1.1.7 root 7861: num_insns++;
1.1 root 7862: /* stop translation if indicated */
7863: if (dc->is_jmp)
7864: break;
7865: /* if single step mode, we generate only one instruction and
7866: generate an exception */
7867: /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7868: the flag and abort the translation to give the irqs a
7869: change to be happen */
1.1.1.6 root 7870: if (dc->tf || dc->singlestep_enabled ||
1.1.1.7 root 7871: (flags & HF_INHIBIT_IRQ_MASK)) {
1.1 root 7872: gen_jmp_im(pc_ptr - dc->cs_base);
7873: gen_eob(dc);
7874: break;
7875: }
7876: /* if too long translation, stop generation too */
7877: if (gen_opc_ptr >= gen_opc_end ||
1.1.1.7 root 7878: (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7879: num_insns >= max_insns) {
1.1 root 7880: gen_jmp_im(pc_ptr - dc->cs_base);
7881: gen_eob(dc);
7882: break;
7883: }
1.1.1.8 root 7884: if (singlestep) {
7885: gen_jmp_im(pc_ptr - dc->cs_base);
7886: gen_eob(dc);
7887: break;
7888: }
1.1 root 7889: }
1.1.1.7 root 7890: if (tb->cflags & CF_LAST_IO)
7891: gen_io_end();
7892: gen_icount_end(tb, num_insns);
1.1 root 7893: *gen_opc_ptr = INDEX_op_end;
7894: /* we don't forget to fill the last values */
7895: if (search_pc) {
7896: j = gen_opc_ptr - gen_opc_buf;
7897: lj++;
7898: while (lj <= j)
7899: gen_opc_instr_start[lj++] = 0;
7900: }
1.1.1.6 root 7901:
1.1 root 7902: #ifdef DEBUG_DISAS
1.1.1.7 root 7903: log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP);
7904: if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1.1 root 7905: int disas_flags;
1.1.1.7 root 7906: qemu_log("----------------\n");
7907: qemu_log("IN: %s\n", lookup_symbol(pc_start));
1.1 root 7908: #ifdef TARGET_X86_64
7909: if (dc->code64)
7910: disas_flags = 2;
7911: else
7912: #endif
7913: disas_flags = !dc->code32;
1.1.1.7 root 7914: log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
7915: qemu_log("\n");
1.1 root 7916: }
7917: #endif
7918:
1.1.1.7 root 7919: if (!search_pc) {
1.1 root 7920: tb->size = pc_ptr - pc_start;
1.1.1.7 root 7921: tb->icount = num_insns;
7922: }
1.1 root 7923: }
7924:
1.1.1.7 root 7925: void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
1.1 root 7926: {
1.1.1.7 root 7927: gen_intermediate_code_internal(env, tb, 0);
1.1 root 7928: }
7929:
1.1.1.7 root 7930: void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
1.1 root 7931: {
1.1.1.7 root 7932: gen_intermediate_code_internal(env, tb, 1);
1.1 root 7933: }
7934:
1.1.1.7 root 7935: void gen_pc_load(CPUState *env, TranslationBlock *tb,
7936: unsigned long searched_pc, int pc_pos, void *puc)
7937: {
7938: int cc_op;
7939: #ifdef DEBUG_DISAS
7940: if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
7941: int i;
7942: qemu_log("RESTORE:\n");
7943: for(i = 0;i <= pc_pos; i++) {
7944: if (gen_opc_instr_start[i]) {
7945: qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7946: }
7947: }
7948: qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7949: searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7950: (uint32_t)tb->cs_base);
7951: }
7952: #endif
7953: env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7954: cc_op = gen_opc_cc_op[pc_pos];
7955: if (cc_op != CC_OP_DYNAMIC)
7956: env->cc_op = cc_op;
7957: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.