File:  [Qemu by Fabrice Bellard] / qemu / target-lm32 / README
Revision (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 19:03:03 2018 UTC (3 years, 7 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu1101, qemu1001, qemu1000, qemu0151, HEAD
qemu 0.15.1

    1: LatticeMico32 target
    2: --------------------
    4: General
    5: -------
    6: All opcodes including the JUART CSRs are supported.
    9: JTAG UART
   10: ---------
   11: JTAG UART is routed to a serial console device. For the current boards it
   12: is the second one. Ie to enable it in the qemu virtual console window use
   13: the following command line parameters:
   14:   -serial vc -serial vc
   15: This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
   16: available as virtual consoles.
   19: Programmatically terminate the emulator
   20: ----------------------------------------
   21: Originally neither the LatticeMico32 nor its peripherals support a
   22: mechanism to shut down the machine. Emulation aware programs can write to a
   23: to a special register within the system control block to shut down the
   24: virtual machine.  For more details see hw/lm32_sys.c. The lm32-evr is the
   25: first BSP which instantiate this model. A (32 bit) write to 0xfff0000
   26: causes a vm shutdown.
   29: Special instructions
   30: --------------------
   31: The translation recognizes one special instruction to halt the cpu:
   32:   and r0, r0, r0
   33: On real hardware this instruction is a nop. It is not used by GCC and
   34: should (hopefully) not be used within hand-crafted assembly.
   35: Insert this instruction in your idle loop to reduce the cpu load on the
   36: host.
   39: Ignoring the MSB of the address bus
   40: -----------------------------------
   41: Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
   42: area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
   43: 0x80000000-0xffffffff is not cached and used to access IO devices. This
   44: behaviour can be enabled with:
   45:   cpu_lm32_set_phys_msb_ignore(env, 1);