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1.1 root 1: /*
2: * QEMU MicroBlaze CPU
3: *
4: * Copyright (c) 2009 Edgar E. Iglesias
5: * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6: * Copyright (c) 2012 SUSE LINUX Products GmbH
7: *
8: * This library is free software; you can redistribute it and/or
9: * modify it under the terms of the GNU Lesser General Public
10: * License as published by the Free Software Foundation; either
11: * version 2.1 of the License, or (at your option) any later version.
12: *
13: * This library is distributed in the hope that it will be useful,
14: * but WITHOUT ANY WARRANTY; without even the implied warranty of
15: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16: * Lesser General Public License for more details.
17: *
18: * You should have received a copy of the GNU Lesser General Public
19: * License along with this library; if not, see
20: * <http://www.gnu.org/licenses/lgpl-2.1.html>
21: */
22:
23: #include "cpu.h"
24: #include "qemu-common.h"
25:
26:
27: /* CPUClass::reset() */
28: static void mb_cpu_reset(CPUState *s)
29: {
30: MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
31: MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
32: CPUMBState *env = &cpu->env;
33:
34: if (qemu_loglevel_mask(CPU_LOG_RESET)) {
35: qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
36: log_cpu_state(env, 0);
37: }
38:
39: mcc->parent_reset(s);
40:
41: memset(env, 0, offsetof(CPUMBState, breakpoints));
42: tlb_flush(env, 1);
43:
44: /* Disable stack protector. */
45: env->shr = ~0;
46:
47: env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
48: | PVR0_USE_BARREL_MASK \
49: | PVR0_USE_DIV_MASK \
50: | PVR0_USE_HW_MUL_MASK \
51: | PVR0_USE_EXC_MASK \
52: | PVR0_USE_ICACHE_MASK \
53: | PVR0_USE_DCACHE_MASK \
54: | PVR0_USE_MMU \
55: | (0xb << 8);
56: env->pvr.regs[2] = PVR2_D_OPB_MASK \
57: | PVR2_D_LMB_MASK \
58: | PVR2_I_OPB_MASK \
59: | PVR2_I_LMB_MASK \
60: | PVR2_USE_MSR_INSTR \
61: | PVR2_USE_PCMP_INSTR \
62: | PVR2_USE_BARREL_MASK \
63: | PVR2_USE_DIV_MASK \
64: | PVR2_USE_HW_MUL_MASK \
65: | PVR2_USE_MUL64_MASK \
66: | PVR2_USE_FPU_MASK \
67: | PVR2_USE_FPU2_MASK \
68: | PVR2_FPU_EXC_MASK \
69: | 0;
70: env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
71: env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
72:
73: #if defined(CONFIG_USER_ONLY)
74: /* start in user mode with interrupts enabled. */
75: env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
76: env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
77: #else
78: env->sregs[SR_MSR] = 0;
79: mmu_init(&env->mmu);
80: env->mmu.c_mmu = 3;
81: env->mmu.c_mmu_tlb_access = 3;
82: env->mmu.c_mmu_zones = 16;
83: #endif
84: }
85:
86: static void mb_cpu_initfn(Object *obj)
87: {
88: MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
89: CPUMBState *env = &cpu->env;
90:
91: cpu_exec_init(env);
92:
93: set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
94: }
95:
96: static void mb_cpu_class_init(ObjectClass *oc, void *data)
97: {
98: CPUClass *cc = CPU_CLASS(oc);
99: MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
100:
101: mcc->parent_reset = cc->reset;
102: cc->reset = mb_cpu_reset;
103: }
104:
105: static const TypeInfo mb_cpu_type_info = {
106: .name = TYPE_MICROBLAZE_CPU,
107: .parent = TYPE_CPU,
108: .instance_size = sizeof(MicroBlazeCPU),
109: .instance_init = mb_cpu_initfn,
110: .class_size = sizeof(MicroBlazeCPUClass),
111: .class_init = mb_cpu_class_init,
112: };
113:
114: static void mb_cpu_register_types(void)
115: {
116: type_register_static(&mb_cpu_type_info);
117: }
118:
119: type_init(mb_cpu_register_types)
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