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Annotation of qemu/target-microblaze/cpu.h, revision 1.1

1.1     ! root        1: /*
        !             2:  *  MicroBlaze virtual CPU header
        !             3:  *
        !             4:  *  Copyright (c) 2009 Edgar E. Iglesias
        !             5:  *
        !             6:  * This library is free software; you can redistribute it and/or
        !             7:  * modify it under the terms of the GNU Lesser General Public
        !             8:  * License as published by the Free Software Foundation; either
        !             9:  * version 2 of the License, or (at your option) any later version.
        !            10:  *
        !            11:  * This library is distributed in the hope that it will be useful,
        !            12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
        !            13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
        !            14:  * General Public License for more details.
        !            15:  *
        !            16:  * You should have received a copy of the GNU Lesser General Public
        !            17:  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
        !            18:  */
        !            19: #ifndef CPU_MICROBLAZE_H
        !            20: #define CPU_MICROBLAZE_H
        !            21: 
        !            22: #define TARGET_LONG_BITS 32
        !            23: 
        !            24: #define CPUState struct CPUMBState
        !            25: 
        !            26: #include "cpu-defs.h"
        !            27: struct CPUMBState;
        !            28: #if !defined(CONFIG_USER_ONLY)
        !            29: #include "mmu.h"
        !            30: #endif
        !            31: 
        !            32: #define TARGET_HAS_ICE 1
        !            33: 
        !            34: #define ELF_MACHINE    EM_XILINX_MICROBLAZE
        !            35: 
        !            36: #define EXCP_NMI        1
        !            37: #define EXCP_MMU        2
        !            38: #define EXCP_IRQ        3
        !            39: #define EXCP_BREAK      4
        !            40: #define EXCP_HW_BREAK   5
        !            41: 
        !            42: /* Register aliases. R0 - R15 */
        !            43: #define R_SP     1
        !            44: #define SR_PC    0
        !            45: #define SR_MSR   1
        !            46: #define SR_EAR   3
        !            47: #define SR_ESR   5
        !            48: #define SR_FSR   7
        !            49: #define SR_BTR   0xb
        !            50: #define SR_EDR   0xd
        !            51: 
        !            52: /* MSR flags.  */
        !            53: #define MSR_BE  (1<<0) /* 0x001 */
        !            54: #define MSR_IE  (1<<1) /* 0x002 */
        !            55: #define MSR_C   (1<<2) /* 0x004 */
        !            56: #define MSR_BIP (1<<3) /* 0x008 */
        !            57: #define MSR_FSL (1<<4) /* 0x010 */
        !            58: #define MSR_ICE (1<<5) /* 0x020 */
        !            59: #define MSR_DZ  (1<<6) /* 0x040 */
        !            60: #define MSR_DCE (1<<7) /* 0x080 */
        !            61: #define MSR_EE  (1<<8) /* 0x100 */
        !            62: #define MSR_EIP (1<<9) /* 0x200 */
        !            63: #define MSR_CC  (1<<31)
        !            64: 
        !            65: /* Machine State Register (MSR) Fields */
        !            66: #define MSR_UM (1<<11) /* User Mode */
        !            67: #define MSR_UMS        (1<<12) /* User Mode Save */
        !            68: #define MSR_VM (1<<13) /* Virtual Mode */
        !            69: #define MSR_VMS        (1<<14) /* Virtual Mode Save */
        !            70: 
        !            71: #define MSR_KERNEL      MSR_EE|MSR_VM
        !            72: //#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
        !            73: #define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
        !            74: //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
        !            75: 
        !            76: /* Exception State Register (ESR) Fields */
        !            77: #define          ESR_DIZ       (1<<11) /* Zone Protection */
        !            78: #define          ESR_S         (1<<10) /* Store instruction */
        !            79: 
        !            80: 
        !            81: 
        !            82: /* Version reg.  */
        !            83: /* Basic PVR mask */
        !            84: #define PVR0_PVR_FULL_MASK              0x80000000
        !            85: #define PVR0_USE_BARREL_MASK            0x40000000
        !            86: #define PVR0_USE_DIV_MASK               0x20000000
        !            87: #define PVR0_USE_HW_MUL_MASK            0x10000000
        !            88: #define PVR0_USE_FPU_MASK               0x08000000
        !            89: #define PVR0_USE_EXC_MASK               0x04000000
        !            90: #define PVR0_USE_ICACHE_MASK            0x02000000
        !            91: #define PVR0_USE_DCACHE_MASK            0x01000000
        !            92: #define PVR0_USE_MMU                    0x00800000      /* new */
        !            93: #define PVR0_VERSION_MASK               0x0000FF00
        !            94: #define PVR0_USER1_MASK                 0x000000FF
        !            95: 
        !            96: /* User 2 PVR mask */
        !            97: #define PVR1_USER2_MASK                 0xFFFFFFFF
        !            98: 
        !            99: /* Configuration PVR masks */
        !           100: #define PVR2_D_OPB_MASK                 0x80000000
        !           101: #define PVR2_D_LMB_MASK                 0x40000000
        !           102: #define PVR2_I_OPB_MASK                 0x20000000
        !           103: #define PVR2_I_LMB_MASK                 0x10000000
        !           104: #define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
        !           105: #define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
        !           106: #define PVR2_D_PLB_MASK                 0x02000000      /* new */
        !           107: #define PVR2_I_PLB_MASK                 0x01000000      /* new */
        !           108: #define PVR2_INTERCONNECT               0x00800000      /* new */
        !           109: #define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
        !           110: #define PVR2_USE_FSL_EXC                0x00040000      /* new */
        !           111: #define PVR2_USE_MSR_INSTR              0x00020000
        !           112: #define PVR2_USE_PCMP_INSTR             0x00010000
        !           113: #define PVR2_AREA_OPTIMISED             0x00008000
        !           114: #define PVR2_USE_BARREL_MASK            0x00004000
        !           115: #define PVR2_USE_DIV_MASK               0x00002000
        !           116: #define PVR2_USE_HW_MUL_MASK            0x00001000
        !           117: #define PVR2_USE_FPU_MASK               0x00000800
        !           118: #define PVR2_USE_MUL64_MASK             0x00000400
        !           119: #define PVR2_USE_FPU2_MASK              0x00000200      /* new */
        !           120: #define PVR2_USE_IPLBEXC                0x00000100
        !           121: #define PVR2_USE_DPLBEXC                0x00000080
        !           122: #define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
        !           123: #define PVR2_UNALIGNED_EXC_MASK         0x00000020
        !           124: #define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
        !           125: #define PVR2_IOPB_BUS_EXC_MASK          0x00000008
        !           126: #define PVR2_DOPB_BUS_EXC_MASK          0x00000004
        !           127: #define PVR2_DIV_ZERO_EXC_MASK          0x00000002
        !           128: #define PVR2_FPU_EXC_MASK               0x00000001
        !           129: 
        !           130: /* Debug and exception PVR masks */
        !           131: #define PVR3_DEBUG_ENABLED_MASK         0x80000000
        !           132: #define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
        !           133: #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
        !           134: #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
        !           135: #define PVR3_FSL_LINKS_MASK             0x00000380
        !           136: 
        !           137: /* ICache config PVR masks */
        !           138: #define PVR4_USE_ICACHE_MASK            0x80000000
        !           139: #define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
        !           140: #define PVR4_ICACHE_USE_FSL_MASK        0x02000000
        !           141: #define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
        !           142: #define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
        !           143: #define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000
        !           144: 
        !           145: /* DCache config PVR masks */
        !           146: #define PVR5_USE_DCACHE_MASK            0x80000000
        !           147: #define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
        !           148: #define PVR5_DCACHE_USE_FSL_MASK        0x02000000
        !           149: #define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
        !           150: #define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
        !           151: #define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
        !           152: 
        !           153: /* ICache base address PVR mask */
        !           154: #define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
        !           155: 
        !           156: /* ICache high address PVR mask */
        !           157: #define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF
        !           158: 
        !           159: /* DCache base address PVR mask */
        !           160: #define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF
        !           161: 
        !           162: /* DCache high address PVR mask */
        !           163: #define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF
        !           164: 
        !           165: /* Target family PVR mask */
        !           166: #define PVR10_TARGET_FAMILY_MASK        0xFF000000
        !           167: 
        !           168: /* MMU descrtiption */
        !           169: #define PVR11_USE_MMU                   0xC0000000
        !           170: #define PVR11_MMU_ITLB_SIZE             0x38000000
        !           171: #define PVR11_MMU_DTLB_SIZE             0x07000000
        !           172: #define PVR11_MMU_TLB_ACCESS            0x00C00000
        !           173: #define PVR11_MMU_ZONES                 0x003C0000
        !           174: /* MSR Reset value PVR mask */
        !           175: #define PVR11_MSR_RESET_VALUE_MASK      0x000007FF
        !           176: 
        !           177: 
        !           178: 
        !           179: /* CPU flags.  */
        !           180: 
        !           181: /* Condition codes.  */
        !           182: #define CC_GE  5
        !           183: #define CC_GT  4
        !           184: #define CC_LE  3
        !           185: #define CC_LT  2
        !           186: #define CC_NE  1
        !           187: #define CC_EQ  0
        !           188: 
        !           189: #define NB_MMU_MODES    3
        !           190: typedef struct CPUMBState {
        !           191:     uint32_t debug;
        !           192:     uint32_t btaken;
        !           193:     uint32_t btarget;
        !           194:     uint32_t bimm;
        !           195: 
        !           196:     uint32_t imm;
        !           197:     uint32_t regs[33];
        !           198:     uint32_t sregs[24];
        !           199: 
        !           200:     /* Internal flags.  */
        !           201: #define IMM_FLAG       4       
        !           202: #define DRTI_FLAG      (1 << 16)
        !           203: #define DRTE_FLAG      (1 << 17)
        !           204: #define DRTB_FLAG      (1 << 18)
        !           205: #define D_FLAG         (1 << 19)  /* Bit in ESR.  */
        !           206: /* TB dependant CPUState.  */
        !           207: #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
        !           208:     uint32_t iflags;
        !           209: 
        !           210:     struct {
        !           211:         uint32_t regs[16];
        !           212:     } pvr;
        !           213: 
        !           214: #if !defined(CONFIG_USER_ONLY)
        !           215:     /* Unified MMU.  */
        !           216:     struct microblaze_mmu mmu;
        !           217: #endif
        !           218: 
        !           219:     CPU_COMMON
        !           220: } CPUMBState;
        !           221: 
        !           222: CPUState *cpu_mb_init(const char *cpu_model);
        !           223: int cpu_mb_exec(CPUState *s);
        !           224: void cpu_mb_close(CPUState *s);
        !           225: void do_interrupt(CPUState *env);
        !           226: /* you can call this signal handler from your SIGBUS and SIGSEGV
        !           227:    signal handlers to inform the virtual CPU of exceptions. non zero
        !           228:    is returned if the signal was handled by the virtual CPU.  */
        !           229: int cpu_mb_signal_handler(int host_signum, void *pinfo,
        !           230:                           void *puc);
        !           231: 
        !           232: enum {
        !           233:     CC_OP_DYNAMIC, /* Use env->cc_op  */
        !           234:     CC_OP_FLAGS,
        !           235:     CC_OP_CMP,
        !           236: };
        !           237: 
        !           238: /* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
        !           239: #define TARGET_PAGE_BITS 12
        !           240: #define MMAP_SHIFT TARGET_PAGE_BITS
        !           241: 
        !           242: #define cpu_init cpu_mb_init
        !           243: #define cpu_exec cpu_mb_exec
        !           244: #define cpu_gen_code cpu_mb_gen_code
        !           245: #define cpu_signal_handler cpu_mb_signal_handler
        !           246: 
        !           247: #define CPU_SAVE_VERSION 1
        !           248: 
        !           249: /* MMU modes definitions */
        !           250: #define MMU_MODE0_SUFFIX _nommu
        !           251: #define MMU_MODE1_SUFFIX _kernel
        !           252: #define MMU_MODE2_SUFFIX _user
        !           253: #define MMU_NOMMU_IDX   0
        !           254: #define MMU_KERNEL_IDX  1
        !           255: #define MMU_USER_IDX    2
        !           256: /* See NB_MMU_MODES further up the file.  */
        !           257: 
        !           258: static inline int cpu_mmu_index (CPUState *env)
        !           259: {
        !           260:         /* Are we in nommu mode?.  */
        !           261:         if (!(env->sregs[SR_MSR] & MSR_VM))
        !           262:             return MMU_NOMMU_IDX;
        !           263: 
        !           264:        if (env->sregs[SR_MSR] & MSR_UM)
        !           265:             return MMU_USER_IDX;
        !           266:         return MMU_KERNEL_IDX;
        !           267: }
        !           268: 
        !           269: int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
        !           270:                             int mmu_idx, int is_softmmu);
        !           271: 
        !           272: #if defined(CONFIG_USER_ONLY)
        !           273: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
        !           274: {
        !           275:     if (newsp)
        !           276:         env->regs[R_SP] = newsp;
        !           277:     env->regs[3] = 0;
        !           278: }
        !           279: #endif
        !           280: 
        !           281: static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
        !           282: {
        !           283: }
        !           284: 
        !           285: static inline int cpu_interrupts_enabled(CPUState *env)
        !           286: {
        !           287:     return env->sregs[SR_MSR] & MSR_IE;
        !           288: }
        !           289: 
        !           290: #include "cpu-all.h"
        !           291: #include "exec-all.h"
        !           292: 
        !           293: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
        !           294: {
        !           295:     env->sregs[SR_PC] = tb->pc;
        !           296: }
        !           297: 
        !           298: static inline target_ulong cpu_get_pc(CPUState *env)
        !           299: {
        !           300:     return env->sregs[SR_PC];
        !           301: }
        !           302: 
        !           303: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
        !           304:                                         target_ulong *cs_base, int *flags)
        !           305: {
        !           306:     *pc = env->sregs[SR_PC];
        !           307:     *cs_base = 0;
        !           308:     *flags = env->iflags & IFLAGS_TB_MASK;
        !           309: }
        !           310: #endif

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