![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to cpu.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / target-microblaze|
Return to cpu.h CVS log | Up to [Qemu by Fabrice Bellard] / qemu / target-microblaze |
1.1 root 1: /*
2: * MicroBlaze virtual CPU header
3: *
4: * Copyright (c) 2009 Edgar E. Iglesias
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18: */
19: #ifndef CPU_MICROBLAZE_H
20: #define CPU_MICROBLAZE_H
21:
22: #define TARGET_LONG_BITS 32
23:
24: #define CPUState struct CPUMBState
25:
26: #include "cpu-defs.h"
1.1.1.4 ! root 27: #include "softfloat.h"
1.1 root 28: struct CPUMBState;
29: #if !defined(CONFIG_USER_ONLY)
30: #include "mmu.h"
31: #endif
32:
33: #define TARGET_HAS_ICE 1
34:
1.1.1.3 root 35: #define ELF_MACHINE EM_MICROBLAZE
1.1 root 36:
37: #define EXCP_NMI 1
38: #define EXCP_MMU 2
39: #define EXCP_IRQ 3
40: #define EXCP_BREAK 4
41: #define EXCP_HW_BREAK 5
1.1.1.2 root 42: #define EXCP_HW_EXCP 6
1.1 root 43:
44: /* Register aliases. R0 - R15 */
45: #define R_SP 1
46: #define SR_PC 0
47: #define SR_MSR 1
48: #define SR_EAR 3
49: #define SR_ESR 5
50: #define SR_FSR 7
51: #define SR_BTR 0xb
52: #define SR_EDR 0xd
53:
54: /* MSR flags. */
55: #define MSR_BE (1<<0) /* 0x001 */
56: #define MSR_IE (1<<1) /* 0x002 */
57: #define MSR_C (1<<2) /* 0x004 */
58: #define MSR_BIP (1<<3) /* 0x008 */
59: #define MSR_FSL (1<<4) /* 0x010 */
60: #define MSR_ICE (1<<5) /* 0x020 */
61: #define MSR_DZ (1<<6) /* 0x040 */
62: #define MSR_DCE (1<<7) /* 0x080 */
63: #define MSR_EE (1<<8) /* 0x100 */
64: #define MSR_EIP (1<<9) /* 0x200 */
65: #define MSR_CC (1<<31)
66:
67: /* Machine State Register (MSR) Fields */
68: #define MSR_UM (1<<11) /* User Mode */
69: #define MSR_UMS (1<<12) /* User Mode Save */
70: #define MSR_VM (1<<13) /* Virtual Mode */
71: #define MSR_VMS (1<<14) /* Virtual Mode Save */
72:
73: #define MSR_KERNEL MSR_EE|MSR_VM
74: //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
75: #define MSR_KERNEL_VMS MSR_EE|MSR_VMS
76: //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
77:
78: /* Exception State Register (ESR) Fields */
79: #define ESR_DIZ (1<<11) /* Zone Protection */
80: #define ESR_S (1<<10) /* Store instruction */
81:
1.1.1.2 root 82: #define ESR_EC_FSL 0
83: #define ESR_EC_UNALIGNED_DATA 1
84: #define ESR_EC_ILLEGAL_OP 2
85: #define ESR_EC_INSN_BUS 3
86: #define ESR_EC_DATA_BUS 4
87: #define ESR_EC_DIVZERO 5
88: #define ESR_EC_FPU 6
89: #define ESR_EC_PRIVINSN 7
90: #define ESR_EC_DATA_STORAGE 8
91: #define ESR_EC_INSN_STORAGE 9
92: #define ESR_EC_DATA_TLB 10
93: #define ESR_EC_INSN_TLB 11
1.1 root 94:
1.1.1.4 ! root 95: /* Floating Point Status Register (FSR) Bits */
! 96: #define FSR_IO (1<<4) /* Invalid operation */
! 97: #define FSR_DZ (1<<3) /* Divide-by-zero */
! 98: #define FSR_OF (1<<2) /* Overflow */
! 99: #define FSR_UF (1<<1) /* Underflow */
! 100: #define FSR_DO (1<<0) /* Denormalized operand error */
! 101:
1.1 root 102: /* Version reg. */
103: /* Basic PVR mask */
104: #define PVR0_PVR_FULL_MASK 0x80000000
105: #define PVR0_USE_BARREL_MASK 0x40000000
106: #define PVR0_USE_DIV_MASK 0x20000000
107: #define PVR0_USE_HW_MUL_MASK 0x10000000
108: #define PVR0_USE_FPU_MASK 0x08000000
109: #define PVR0_USE_EXC_MASK 0x04000000
110: #define PVR0_USE_ICACHE_MASK 0x02000000
111: #define PVR0_USE_DCACHE_MASK 0x01000000
112: #define PVR0_USE_MMU 0x00800000 /* new */
113: #define PVR0_VERSION_MASK 0x0000FF00
114: #define PVR0_USER1_MASK 0x000000FF
115:
116: /* User 2 PVR mask */
117: #define PVR1_USER2_MASK 0xFFFFFFFF
118:
119: /* Configuration PVR masks */
120: #define PVR2_D_OPB_MASK 0x80000000
121: #define PVR2_D_LMB_MASK 0x40000000
122: #define PVR2_I_OPB_MASK 0x20000000
123: #define PVR2_I_LMB_MASK 0x10000000
124: #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
125: #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
126: #define PVR2_D_PLB_MASK 0x02000000 /* new */
127: #define PVR2_I_PLB_MASK 0x01000000 /* new */
128: #define PVR2_INTERCONNECT 0x00800000 /* new */
129: #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
130: #define PVR2_USE_FSL_EXC 0x00040000 /* new */
131: #define PVR2_USE_MSR_INSTR 0x00020000
132: #define PVR2_USE_PCMP_INSTR 0x00010000
133: #define PVR2_AREA_OPTIMISED 0x00008000
134: #define PVR2_USE_BARREL_MASK 0x00004000
135: #define PVR2_USE_DIV_MASK 0x00002000
136: #define PVR2_USE_HW_MUL_MASK 0x00001000
137: #define PVR2_USE_FPU_MASK 0x00000800
138: #define PVR2_USE_MUL64_MASK 0x00000400
139: #define PVR2_USE_FPU2_MASK 0x00000200 /* new */
140: #define PVR2_USE_IPLBEXC 0x00000100
141: #define PVR2_USE_DPLBEXC 0x00000080
142: #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
143: #define PVR2_UNALIGNED_EXC_MASK 0x00000020
144: #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
145: #define PVR2_IOPB_BUS_EXC_MASK 0x00000008
146: #define PVR2_DOPB_BUS_EXC_MASK 0x00000004
147: #define PVR2_DIV_ZERO_EXC_MASK 0x00000002
148: #define PVR2_FPU_EXC_MASK 0x00000001
149:
150: /* Debug and exception PVR masks */
151: #define PVR3_DEBUG_ENABLED_MASK 0x80000000
152: #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
153: #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
154: #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
155: #define PVR3_FSL_LINKS_MASK 0x00000380
156:
157: /* ICache config PVR masks */
158: #define PVR4_USE_ICACHE_MASK 0x80000000
159: #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
160: #define PVR4_ICACHE_USE_FSL_MASK 0x02000000
161: #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
162: #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
163: #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
164:
165: /* DCache config PVR masks */
166: #define PVR5_USE_DCACHE_MASK 0x80000000
167: #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
168: #define PVR5_DCACHE_USE_FSL_MASK 0x02000000
169: #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
170: #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
171: #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
172:
173: /* ICache base address PVR mask */
174: #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
175:
176: /* ICache high address PVR mask */
177: #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
178:
179: /* DCache base address PVR mask */
180: #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
181:
182: /* DCache high address PVR mask */
183: #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
184:
185: /* Target family PVR mask */
186: #define PVR10_TARGET_FAMILY_MASK 0xFF000000
187:
188: /* MMU descrtiption */
189: #define PVR11_USE_MMU 0xC0000000
190: #define PVR11_MMU_ITLB_SIZE 0x38000000
191: #define PVR11_MMU_DTLB_SIZE 0x07000000
192: #define PVR11_MMU_TLB_ACCESS 0x00C00000
193: #define PVR11_MMU_ZONES 0x003C0000
194: /* MSR Reset value PVR mask */
195: #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
196:
197:
198:
199: /* CPU flags. */
200:
201: /* Condition codes. */
202: #define CC_GE 5
203: #define CC_GT 4
204: #define CC_LE 3
205: #define CC_LT 2
206: #define CC_NE 1
207: #define CC_EQ 0
208:
209: #define NB_MMU_MODES 3
210: typedef struct CPUMBState {
211: uint32_t debug;
212: uint32_t btaken;
213: uint32_t btarget;
214: uint32_t bimm;
215:
216: uint32_t imm;
217: uint32_t regs[33];
218: uint32_t sregs[24];
1.1.1.4 ! root 219: float_status fp_status;
1.1 root 220:
221: /* Internal flags. */
1.1.1.2 root 222: #define IMM_FLAG 4
223: #define MSR_EE_FLAG (1 << 8)
1.1 root 224: #define DRTI_FLAG (1 << 16)
225: #define DRTE_FLAG (1 << 17)
226: #define DRTB_FLAG (1 << 18)
227: #define D_FLAG (1 << 19) /* Bit in ESR. */
228: /* TB dependant CPUState. */
1.1.1.3 root 229: #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
1.1 root 230: uint32_t iflags;
231:
232: struct {
233: uint32_t regs[16];
234: } pvr;
235:
236: #if !defined(CONFIG_USER_ONLY)
237: /* Unified MMU. */
238: struct microblaze_mmu mmu;
239: #endif
240:
241: CPU_COMMON
242: } CPUMBState;
243:
244: CPUState *cpu_mb_init(const char *cpu_model);
245: int cpu_mb_exec(CPUState *s);
246: void cpu_mb_close(CPUState *s);
247: void do_interrupt(CPUState *env);
248: /* you can call this signal handler from your SIGBUS and SIGSEGV
249: signal handlers to inform the virtual CPU of exceptions. non zero
250: is returned if the signal was handled by the virtual CPU. */
251: int cpu_mb_signal_handler(int host_signum, void *pinfo,
252: void *puc);
253:
254: enum {
255: CC_OP_DYNAMIC, /* Use env->cc_op */
256: CC_OP_FLAGS,
257: CC_OP_CMP,
258: };
259:
260: /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
261: #define TARGET_PAGE_BITS 12
262: #define MMAP_SHIFT TARGET_PAGE_BITS
263:
1.1.1.3 root 264: #define TARGET_PHYS_ADDR_SPACE_BITS 32
265: #define TARGET_VIRT_ADDR_SPACE_BITS 32
266:
1.1 root 267: #define cpu_init cpu_mb_init
268: #define cpu_exec cpu_mb_exec
269: #define cpu_gen_code cpu_mb_gen_code
270: #define cpu_signal_handler cpu_mb_signal_handler
271:
272: #define CPU_SAVE_VERSION 1
273:
274: /* MMU modes definitions */
275: #define MMU_MODE0_SUFFIX _nommu
276: #define MMU_MODE1_SUFFIX _kernel
277: #define MMU_MODE2_SUFFIX _user
278: #define MMU_NOMMU_IDX 0
279: #define MMU_KERNEL_IDX 1
280: #define MMU_USER_IDX 2
281: /* See NB_MMU_MODES further up the file. */
282:
283: static inline int cpu_mmu_index (CPUState *env)
284: {
285: /* Are we in nommu mode?. */
286: if (!(env->sregs[SR_MSR] & MSR_VM))
287: return MMU_NOMMU_IDX;
288:
289: if (env->sregs[SR_MSR] & MSR_UM)
290: return MMU_USER_IDX;
291: return MMU_KERNEL_IDX;
292: }
293:
294: int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
295: int mmu_idx, int is_softmmu);
1.1.1.2 root 296: #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
1.1 root 297:
298: #if defined(CONFIG_USER_ONLY)
299: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
300: {
301: if (newsp)
302: env->regs[R_SP] = newsp;
303: env->regs[3] = 0;
304: }
305: #endif
306:
307: static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
308: {
309: }
310:
311: static inline int cpu_interrupts_enabled(CPUState *env)
312: {
313: return env->sregs[SR_MSR] & MSR_IE;
314: }
315:
316: #include "cpu-all.h"
317:
318: static inline target_ulong cpu_get_pc(CPUState *env)
319: {
320: return env->sregs[SR_PC];
321: }
322:
323: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
324: target_ulong *cs_base, int *flags)
325: {
326: *pc = env->sregs[SR_PC];
327: *cs_base = 0;
1.1.1.3 root 328: *flags = (env->iflags & IFLAGS_TB_MASK) |
329: (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
1.1 root 330: }
1.1.1.2 root 331:
1.1.1.3 root 332: #if !defined(CONFIG_USER_ONLY)
1.1.1.2 root 333: void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
334: int is_asi, int size);
1.1 root 335: #endif
1.1.1.3 root 336: #endif
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.