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1.1 root 1: /*
2: * MicroBlaze virtual CPU header
3: *
4: * Copyright (c) 2009 Edgar E. Iglesias
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18: */
19: #ifndef CPU_MICROBLAZE_H
20: #define CPU_MICROBLAZE_H
21:
22: #define TARGET_LONG_BITS 32
23:
24: #define CPUState struct CPUMBState
25:
26: #include "cpu-defs.h"
1.1.1.4 root 27: #include "softfloat.h"
1.1 root 28: struct CPUMBState;
29: #if !defined(CONFIG_USER_ONLY)
30: #include "mmu.h"
31: #endif
32:
33: #define TARGET_HAS_ICE 1
34:
1.1.1.3 root 35: #define ELF_MACHINE EM_MICROBLAZE
1.1 root 36:
37: #define EXCP_NMI 1
38: #define EXCP_MMU 2
39: #define EXCP_IRQ 3
40: #define EXCP_BREAK 4
41: #define EXCP_HW_BREAK 5
1.1.1.2 root 42: #define EXCP_HW_EXCP 6
1.1 root 43:
1.1.1.5 ! root 44: /* MicroBlaze-specific interrupt pending bits. */
! 45: #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
! 46:
1.1 root 47: /* Register aliases. R0 - R15 */
48: #define R_SP 1
49: #define SR_PC 0
50: #define SR_MSR 1
51: #define SR_EAR 3
52: #define SR_ESR 5
53: #define SR_FSR 7
54: #define SR_BTR 0xb
55: #define SR_EDR 0xd
56:
57: /* MSR flags. */
58: #define MSR_BE (1<<0) /* 0x001 */
59: #define MSR_IE (1<<1) /* 0x002 */
60: #define MSR_C (1<<2) /* 0x004 */
61: #define MSR_BIP (1<<3) /* 0x008 */
62: #define MSR_FSL (1<<4) /* 0x010 */
63: #define MSR_ICE (1<<5) /* 0x020 */
64: #define MSR_DZ (1<<6) /* 0x040 */
65: #define MSR_DCE (1<<7) /* 0x080 */
66: #define MSR_EE (1<<8) /* 0x100 */
67: #define MSR_EIP (1<<9) /* 0x200 */
68: #define MSR_CC (1<<31)
69:
70: /* Machine State Register (MSR) Fields */
71: #define MSR_UM (1<<11) /* User Mode */
72: #define MSR_UMS (1<<12) /* User Mode Save */
73: #define MSR_VM (1<<13) /* Virtual Mode */
74: #define MSR_VMS (1<<14) /* Virtual Mode Save */
75:
76: #define MSR_KERNEL MSR_EE|MSR_VM
77: //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
78: #define MSR_KERNEL_VMS MSR_EE|MSR_VMS
79: //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
80:
81: /* Exception State Register (ESR) Fields */
82: #define ESR_DIZ (1<<11) /* Zone Protection */
83: #define ESR_S (1<<10) /* Store instruction */
84:
1.1.1.5 ! root 85: #define ESR_ESS_FSL_OFFSET 5
! 86:
1.1.1.2 root 87: #define ESR_EC_FSL 0
88: #define ESR_EC_UNALIGNED_DATA 1
89: #define ESR_EC_ILLEGAL_OP 2
90: #define ESR_EC_INSN_BUS 3
91: #define ESR_EC_DATA_BUS 4
92: #define ESR_EC_DIVZERO 5
93: #define ESR_EC_FPU 6
94: #define ESR_EC_PRIVINSN 7
95: #define ESR_EC_DATA_STORAGE 8
96: #define ESR_EC_INSN_STORAGE 9
97: #define ESR_EC_DATA_TLB 10
98: #define ESR_EC_INSN_TLB 11
1.1.1.5 ! root 99: #define ESR_EC_MASK 31
1.1 root 100:
1.1.1.4 root 101: /* Floating Point Status Register (FSR) Bits */
102: #define FSR_IO (1<<4) /* Invalid operation */
103: #define FSR_DZ (1<<3) /* Divide-by-zero */
104: #define FSR_OF (1<<2) /* Overflow */
105: #define FSR_UF (1<<1) /* Underflow */
106: #define FSR_DO (1<<0) /* Denormalized operand error */
107:
1.1 root 108: /* Version reg. */
109: /* Basic PVR mask */
110: #define PVR0_PVR_FULL_MASK 0x80000000
111: #define PVR0_USE_BARREL_MASK 0x40000000
112: #define PVR0_USE_DIV_MASK 0x20000000
113: #define PVR0_USE_HW_MUL_MASK 0x10000000
114: #define PVR0_USE_FPU_MASK 0x08000000
115: #define PVR0_USE_EXC_MASK 0x04000000
116: #define PVR0_USE_ICACHE_MASK 0x02000000
117: #define PVR0_USE_DCACHE_MASK 0x01000000
118: #define PVR0_USE_MMU 0x00800000 /* new */
1.1.1.5 ! root 119: #define PVR0_USE_BTC 0x00400000
! 120: #define PVR0_ENDI 0x00200000
! 121: #define PVR0_FAULT 0x00100000
1.1 root 122: #define PVR0_VERSION_MASK 0x0000FF00
123: #define PVR0_USER1_MASK 0x000000FF
124:
125: /* User 2 PVR mask */
126: #define PVR1_USER2_MASK 0xFFFFFFFF
127:
128: /* Configuration PVR masks */
129: #define PVR2_D_OPB_MASK 0x80000000
130: #define PVR2_D_LMB_MASK 0x40000000
131: #define PVR2_I_OPB_MASK 0x20000000
132: #define PVR2_I_LMB_MASK 0x10000000
133: #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
134: #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
135: #define PVR2_D_PLB_MASK 0x02000000 /* new */
136: #define PVR2_I_PLB_MASK 0x01000000 /* new */
137: #define PVR2_INTERCONNECT 0x00800000 /* new */
138: #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
139: #define PVR2_USE_FSL_EXC 0x00040000 /* new */
140: #define PVR2_USE_MSR_INSTR 0x00020000
141: #define PVR2_USE_PCMP_INSTR 0x00010000
142: #define PVR2_AREA_OPTIMISED 0x00008000
143: #define PVR2_USE_BARREL_MASK 0x00004000
144: #define PVR2_USE_DIV_MASK 0x00002000
145: #define PVR2_USE_HW_MUL_MASK 0x00001000
146: #define PVR2_USE_FPU_MASK 0x00000800
147: #define PVR2_USE_MUL64_MASK 0x00000400
148: #define PVR2_USE_FPU2_MASK 0x00000200 /* new */
149: #define PVR2_USE_IPLBEXC 0x00000100
150: #define PVR2_USE_DPLBEXC 0x00000080
151: #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
152: #define PVR2_UNALIGNED_EXC_MASK 0x00000020
153: #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
154: #define PVR2_IOPB_BUS_EXC_MASK 0x00000008
155: #define PVR2_DOPB_BUS_EXC_MASK 0x00000004
156: #define PVR2_DIV_ZERO_EXC_MASK 0x00000002
157: #define PVR2_FPU_EXC_MASK 0x00000001
158:
159: /* Debug and exception PVR masks */
160: #define PVR3_DEBUG_ENABLED_MASK 0x80000000
161: #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
162: #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
163: #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
164: #define PVR3_FSL_LINKS_MASK 0x00000380
165:
166: /* ICache config PVR masks */
167: #define PVR4_USE_ICACHE_MASK 0x80000000
168: #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
169: #define PVR4_ICACHE_USE_FSL_MASK 0x02000000
170: #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
171: #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
172: #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
173:
174: /* DCache config PVR masks */
175: #define PVR5_USE_DCACHE_MASK 0x80000000
176: #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
177: #define PVR5_DCACHE_USE_FSL_MASK 0x02000000
178: #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
179: #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
180: #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
1.1.1.5 ! root 181: #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
1.1 root 182:
183: /* ICache base address PVR mask */
184: #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
185:
186: /* ICache high address PVR mask */
187: #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
188:
189: /* DCache base address PVR mask */
190: #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
191:
192: /* DCache high address PVR mask */
193: #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
194:
195: /* Target family PVR mask */
196: #define PVR10_TARGET_FAMILY_MASK 0xFF000000
197:
198: /* MMU descrtiption */
199: #define PVR11_USE_MMU 0xC0000000
200: #define PVR11_MMU_ITLB_SIZE 0x38000000
201: #define PVR11_MMU_DTLB_SIZE 0x07000000
202: #define PVR11_MMU_TLB_ACCESS 0x00C00000
1.1.1.5 ! root 203: #define PVR11_MMU_ZONES 0x003E0000
1.1 root 204: /* MSR Reset value PVR mask */
205: #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
206:
207:
208:
209: /* CPU flags. */
210:
211: /* Condition codes. */
212: #define CC_GE 5
213: #define CC_GT 4
214: #define CC_LE 3
215: #define CC_LT 2
216: #define CC_NE 1
217: #define CC_EQ 0
218:
219: #define NB_MMU_MODES 3
1.1.1.5 ! root 220:
! 221: #define STREAM_EXCEPTION (1 << 0)
! 222: #define STREAM_ATOMIC (1 << 1)
! 223: #define STREAM_TEST (1 << 2)
! 224: #define STREAM_CONTROL (1 << 3)
! 225: #define STREAM_NONBLOCK (1 << 4)
! 226:
1.1 root 227: typedef struct CPUMBState {
228: uint32_t debug;
229: uint32_t btaken;
230: uint32_t btarget;
231: uint32_t bimm;
232:
233: uint32_t imm;
234: uint32_t regs[33];
235: uint32_t sregs[24];
1.1.1.4 root 236: float_status fp_status;
1.1 root 237:
238: /* Internal flags. */
1.1.1.2 root 239: #define IMM_FLAG 4
240: #define MSR_EE_FLAG (1 << 8)
1.1 root 241: #define DRTI_FLAG (1 << 16)
242: #define DRTE_FLAG (1 << 17)
243: #define DRTB_FLAG (1 << 18)
244: #define D_FLAG (1 << 19) /* Bit in ESR. */
245: /* TB dependant CPUState. */
1.1.1.3 root 246: #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
1.1 root 247: uint32_t iflags;
248:
249: struct {
250: uint32_t regs[16];
251: } pvr;
252:
253: #if !defined(CONFIG_USER_ONLY)
254: /* Unified MMU. */
255: struct microblaze_mmu mmu;
256: #endif
257:
258: CPU_COMMON
259: } CPUMBState;
260:
261: CPUState *cpu_mb_init(const char *cpu_model);
262: int cpu_mb_exec(CPUState *s);
263: void cpu_mb_close(CPUState *s);
264: void do_interrupt(CPUState *env);
265: /* you can call this signal handler from your SIGBUS and SIGSEGV
266: signal handlers to inform the virtual CPU of exceptions. non zero
267: is returned if the signal was handled by the virtual CPU. */
268: int cpu_mb_signal_handler(int host_signum, void *pinfo,
269: void *puc);
270:
271: enum {
272: CC_OP_DYNAMIC, /* Use env->cc_op */
273: CC_OP_FLAGS,
274: CC_OP_CMP,
275: };
276:
277: /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
278: #define TARGET_PAGE_BITS 12
279: #define MMAP_SHIFT TARGET_PAGE_BITS
280:
1.1.1.3 root 281: #define TARGET_PHYS_ADDR_SPACE_BITS 32
282: #define TARGET_VIRT_ADDR_SPACE_BITS 32
283:
1.1 root 284: #define cpu_init cpu_mb_init
285: #define cpu_exec cpu_mb_exec
286: #define cpu_gen_code cpu_mb_gen_code
287: #define cpu_signal_handler cpu_mb_signal_handler
288:
289: #define CPU_SAVE_VERSION 1
290:
291: /* MMU modes definitions */
292: #define MMU_MODE0_SUFFIX _nommu
293: #define MMU_MODE1_SUFFIX _kernel
294: #define MMU_MODE2_SUFFIX _user
295: #define MMU_NOMMU_IDX 0
296: #define MMU_KERNEL_IDX 1
297: #define MMU_USER_IDX 2
298: /* See NB_MMU_MODES further up the file. */
299:
300: static inline int cpu_mmu_index (CPUState *env)
301: {
302: /* Are we in nommu mode?. */
303: if (!(env->sregs[SR_MSR] & MSR_VM))
304: return MMU_NOMMU_IDX;
305:
306: if (env->sregs[SR_MSR] & MSR_UM)
307: return MMU_USER_IDX;
308: return MMU_KERNEL_IDX;
309: }
310:
311: int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
312: int mmu_idx, int is_softmmu);
1.1.1.2 root 313: #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
1.1 root 314:
315: #if defined(CONFIG_USER_ONLY)
316: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
317: {
318: if (newsp)
319: env->regs[R_SP] = newsp;
320: env->regs[3] = 0;
321: }
322: #endif
323:
324: static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
325: {
326: }
327:
328: static inline int cpu_interrupts_enabled(CPUState *env)
329: {
330: return env->sregs[SR_MSR] & MSR_IE;
331: }
332:
333: #include "cpu-all.h"
334:
335: static inline target_ulong cpu_get_pc(CPUState *env)
336: {
337: return env->sregs[SR_PC];
338: }
339:
340: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
341: target_ulong *cs_base, int *flags)
342: {
343: *pc = env->sregs[SR_PC];
344: *cs_base = 0;
1.1.1.3 root 345: *flags = (env->iflags & IFLAGS_TB_MASK) |
346: (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
1.1 root 347: }
1.1.1.2 root 348:
1.1.1.3 root 349: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 ! root 350: void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
! 351: int is_write, int is_exec, int is_asi, int size);
1.1 root 352: #endif
1.1.1.5 ! root 353:
! 354: static inline bool cpu_has_work(CPUState *env)
! 355: {
! 356: return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
! 357: }
! 358:
! 359: #include "exec-all.h"
! 360:
! 361: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
! 362: {
! 363: env->sregs[SR_PC] = tb->pc;
! 364: }
! 365:
1.1.1.3 root 366: #endif
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