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1.1 root 1: /*
2: * MicroBlaze virtual CPU header
3: *
4: * Copyright (c) 2009 Edgar E. Iglesias
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18: */
19: #ifndef CPU_MICROBLAZE_H
20: #define CPU_MICROBLAZE_H
21:
22: #define TARGET_LONG_BITS 32
23:
24: #define CPUState struct CPUMBState
25:
26: #include "cpu-defs.h"
1.1.1.4 root 27: #include "softfloat.h"
1.1 root 28: struct CPUMBState;
29: #if !defined(CONFIG_USER_ONLY)
30: #include "mmu.h"
31: #endif
32:
33: #define TARGET_HAS_ICE 1
34:
1.1.1.3 root 35: #define ELF_MACHINE EM_MICROBLAZE
1.1 root 36:
37: #define EXCP_NMI 1
38: #define EXCP_MMU 2
39: #define EXCP_IRQ 3
40: #define EXCP_BREAK 4
41: #define EXCP_HW_BREAK 5
1.1.1.2 root 42: #define EXCP_HW_EXCP 6
1.1 root 43:
1.1.1.5 root 44: /* MicroBlaze-specific interrupt pending bits. */
45: #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
46:
1.1 root 47: /* Register aliases. R0 - R15 */
48: #define R_SP 1
49: #define SR_PC 0
50: #define SR_MSR 1
51: #define SR_EAR 3
52: #define SR_ESR 5
53: #define SR_FSR 7
54: #define SR_BTR 0xb
55: #define SR_EDR 0xd
56:
57: /* MSR flags. */
58: #define MSR_BE (1<<0) /* 0x001 */
59: #define MSR_IE (1<<1) /* 0x002 */
60: #define MSR_C (1<<2) /* 0x004 */
61: #define MSR_BIP (1<<3) /* 0x008 */
62: #define MSR_FSL (1<<4) /* 0x010 */
63: #define MSR_ICE (1<<5) /* 0x020 */
64: #define MSR_DZ (1<<6) /* 0x040 */
65: #define MSR_DCE (1<<7) /* 0x080 */
66: #define MSR_EE (1<<8) /* 0x100 */
67: #define MSR_EIP (1<<9) /* 0x200 */
1.1.1.6 ! root 68: #define MSR_PVR (1<<10) /* 0x400 */
1.1 root 69: #define MSR_CC (1<<31)
70:
71: /* Machine State Register (MSR) Fields */
72: #define MSR_UM (1<<11) /* User Mode */
73: #define MSR_UMS (1<<12) /* User Mode Save */
74: #define MSR_VM (1<<13) /* Virtual Mode */
75: #define MSR_VMS (1<<14) /* Virtual Mode Save */
76:
77: #define MSR_KERNEL MSR_EE|MSR_VM
78: //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
79: #define MSR_KERNEL_VMS MSR_EE|MSR_VMS
80: //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
81:
82: /* Exception State Register (ESR) Fields */
83: #define ESR_DIZ (1<<11) /* Zone Protection */
84: #define ESR_S (1<<10) /* Store instruction */
85:
1.1.1.5 root 86: #define ESR_ESS_FSL_OFFSET 5
87:
1.1.1.2 root 88: #define ESR_EC_FSL 0
89: #define ESR_EC_UNALIGNED_DATA 1
90: #define ESR_EC_ILLEGAL_OP 2
91: #define ESR_EC_INSN_BUS 3
92: #define ESR_EC_DATA_BUS 4
93: #define ESR_EC_DIVZERO 5
94: #define ESR_EC_FPU 6
95: #define ESR_EC_PRIVINSN 7
96: #define ESR_EC_DATA_STORAGE 8
97: #define ESR_EC_INSN_STORAGE 9
98: #define ESR_EC_DATA_TLB 10
99: #define ESR_EC_INSN_TLB 11
1.1.1.5 root 100: #define ESR_EC_MASK 31
1.1 root 101:
1.1.1.4 root 102: /* Floating Point Status Register (FSR) Bits */
103: #define FSR_IO (1<<4) /* Invalid operation */
104: #define FSR_DZ (1<<3) /* Divide-by-zero */
105: #define FSR_OF (1<<2) /* Overflow */
106: #define FSR_UF (1<<1) /* Underflow */
107: #define FSR_DO (1<<0) /* Denormalized operand error */
108:
1.1 root 109: /* Version reg. */
110: /* Basic PVR mask */
111: #define PVR0_PVR_FULL_MASK 0x80000000
112: #define PVR0_USE_BARREL_MASK 0x40000000
113: #define PVR0_USE_DIV_MASK 0x20000000
114: #define PVR0_USE_HW_MUL_MASK 0x10000000
115: #define PVR0_USE_FPU_MASK 0x08000000
116: #define PVR0_USE_EXC_MASK 0x04000000
117: #define PVR0_USE_ICACHE_MASK 0x02000000
118: #define PVR0_USE_DCACHE_MASK 0x01000000
119: #define PVR0_USE_MMU 0x00800000 /* new */
1.1.1.5 root 120: #define PVR0_USE_BTC 0x00400000
121: #define PVR0_ENDI 0x00200000
122: #define PVR0_FAULT 0x00100000
1.1 root 123: #define PVR0_VERSION_MASK 0x0000FF00
124: #define PVR0_USER1_MASK 0x000000FF
125:
126: /* User 2 PVR mask */
127: #define PVR1_USER2_MASK 0xFFFFFFFF
128:
129: /* Configuration PVR masks */
130: #define PVR2_D_OPB_MASK 0x80000000
131: #define PVR2_D_LMB_MASK 0x40000000
132: #define PVR2_I_OPB_MASK 0x20000000
133: #define PVR2_I_LMB_MASK 0x10000000
134: #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
135: #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
136: #define PVR2_D_PLB_MASK 0x02000000 /* new */
137: #define PVR2_I_PLB_MASK 0x01000000 /* new */
138: #define PVR2_INTERCONNECT 0x00800000 /* new */
139: #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
140: #define PVR2_USE_FSL_EXC 0x00040000 /* new */
141: #define PVR2_USE_MSR_INSTR 0x00020000
142: #define PVR2_USE_PCMP_INSTR 0x00010000
143: #define PVR2_AREA_OPTIMISED 0x00008000
144: #define PVR2_USE_BARREL_MASK 0x00004000
145: #define PVR2_USE_DIV_MASK 0x00002000
146: #define PVR2_USE_HW_MUL_MASK 0x00001000
147: #define PVR2_USE_FPU_MASK 0x00000800
148: #define PVR2_USE_MUL64_MASK 0x00000400
149: #define PVR2_USE_FPU2_MASK 0x00000200 /* new */
150: #define PVR2_USE_IPLBEXC 0x00000100
151: #define PVR2_USE_DPLBEXC 0x00000080
152: #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
153: #define PVR2_UNALIGNED_EXC_MASK 0x00000020
154: #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
155: #define PVR2_IOPB_BUS_EXC_MASK 0x00000008
156: #define PVR2_DOPB_BUS_EXC_MASK 0x00000004
157: #define PVR2_DIV_ZERO_EXC_MASK 0x00000002
158: #define PVR2_FPU_EXC_MASK 0x00000001
159:
160: /* Debug and exception PVR masks */
161: #define PVR3_DEBUG_ENABLED_MASK 0x80000000
162: #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
163: #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
164: #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
165: #define PVR3_FSL_LINKS_MASK 0x00000380
166:
167: /* ICache config PVR masks */
168: #define PVR4_USE_ICACHE_MASK 0x80000000
169: #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
170: #define PVR4_ICACHE_USE_FSL_MASK 0x02000000
171: #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
172: #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
173: #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
174:
175: /* DCache config PVR masks */
176: #define PVR5_USE_DCACHE_MASK 0x80000000
177: #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
178: #define PVR5_DCACHE_USE_FSL_MASK 0x02000000
179: #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
180: #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
181: #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
1.1.1.5 root 182: #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
1.1 root 183:
184: /* ICache base address PVR mask */
185: #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
186:
187: /* ICache high address PVR mask */
188: #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
189:
190: /* DCache base address PVR mask */
191: #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
192:
193: /* DCache high address PVR mask */
194: #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
195:
196: /* Target family PVR mask */
197: #define PVR10_TARGET_FAMILY_MASK 0xFF000000
198:
199: /* MMU descrtiption */
200: #define PVR11_USE_MMU 0xC0000000
201: #define PVR11_MMU_ITLB_SIZE 0x38000000
202: #define PVR11_MMU_DTLB_SIZE 0x07000000
203: #define PVR11_MMU_TLB_ACCESS 0x00C00000
1.1.1.5 root 204: #define PVR11_MMU_ZONES 0x003E0000
1.1 root 205: /* MSR Reset value PVR mask */
206: #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
207:
208:
209:
210: /* CPU flags. */
211:
212: /* Condition codes. */
213: #define CC_GE 5
214: #define CC_GT 4
215: #define CC_LE 3
216: #define CC_LT 2
217: #define CC_NE 1
218: #define CC_EQ 0
219:
220: #define NB_MMU_MODES 3
1.1.1.5 root 221:
222: #define STREAM_EXCEPTION (1 << 0)
223: #define STREAM_ATOMIC (1 << 1)
224: #define STREAM_TEST (1 << 2)
225: #define STREAM_CONTROL (1 << 3)
226: #define STREAM_NONBLOCK (1 << 4)
227:
1.1 root 228: typedef struct CPUMBState {
229: uint32_t debug;
230: uint32_t btaken;
231: uint32_t btarget;
232: uint32_t bimm;
233:
234: uint32_t imm;
235: uint32_t regs[33];
236: uint32_t sregs[24];
1.1.1.4 root 237: float_status fp_status;
1.1 root 238:
239: /* Internal flags. */
1.1.1.2 root 240: #define IMM_FLAG 4
241: #define MSR_EE_FLAG (1 << 8)
1.1 root 242: #define DRTI_FLAG (1 << 16)
243: #define DRTE_FLAG (1 << 17)
244: #define DRTB_FLAG (1 << 18)
245: #define D_FLAG (1 << 19) /* Bit in ESR. */
246: /* TB dependant CPUState. */
1.1.1.3 root 247: #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
1.1 root 248: uint32_t iflags;
249:
250: struct {
251: uint32_t regs[16];
252: } pvr;
253:
254: #if !defined(CONFIG_USER_ONLY)
255: /* Unified MMU. */
256: struct microblaze_mmu mmu;
257: #endif
258:
259: CPU_COMMON
260: } CPUMBState;
261:
262: CPUState *cpu_mb_init(const char *cpu_model);
263: int cpu_mb_exec(CPUState *s);
264: void cpu_mb_close(CPUState *s);
265: void do_interrupt(CPUState *env);
266: /* you can call this signal handler from your SIGBUS and SIGSEGV
267: signal handlers to inform the virtual CPU of exceptions. non zero
268: is returned if the signal was handled by the virtual CPU. */
269: int cpu_mb_signal_handler(int host_signum, void *pinfo,
270: void *puc);
271:
272: enum {
273: CC_OP_DYNAMIC, /* Use env->cc_op */
274: CC_OP_FLAGS,
275: CC_OP_CMP,
276: };
277:
278: /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
279: #define TARGET_PAGE_BITS 12
280: #define MMAP_SHIFT TARGET_PAGE_BITS
281:
1.1.1.3 root 282: #define TARGET_PHYS_ADDR_SPACE_BITS 32
283: #define TARGET_VIRT_ADDR_SPACE_BITS 32
284:
1.1 root 285: #define cpu_init cpu_mb_init
286: #define cpu_exec cpu_mb_exec
287: #define cpu_gen_code cpu_mb_gen_code
288: #define cpu_signal_handler cpu_mb_signal_handler
289:
290: #define CPU_SAVE_VERSION 1
291:
292: /* MMU modes definitions */
293: #define MMU_MODE0_SUFFIX _nommu
294: #define MMU_MODE1_SUFFIX _kernel
295: #define MMU_MODE2_SUFFIX _user
296: #define MMU_NOMMU_IDX 0
297: #define MMU_KERNEL_IDX 1
298: #define MMU_USER_IDX 2
299: /* See NB_MMU_MODES further up the file. */
300:
301: static inline int cpu_mmu_index (CPUState *env)
302: {
303: /* Are we in nommu mode?. */
304: if (!(env->sregs[SR_MSR] & MSR_VM))
305: return MMU_NOMMU_IDX;
306:
307: if (env->sregs[SR_MSR] & MSR_UM)
308: return MMU_USER_IDX;
309: return MMU_KERNEL_IDX;
310: }
311:
312: int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
1.1.1.6 ! root 313: int mmu_idx);
1.1.1.2 root 314: #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
1.1 root 315:
316: #if defined(CONFIG_USER_ONLY)
317: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
318: {
319: if (newsp)
320: env->regs[R_SP] = newsp;
321: env->regs[3] = 0;
322: }
323: #endif
324:
325: static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
326: {
327: }
328:
329: static inline int cpu_interrupts_enabled(CPUState *env)
330: {
331: return env->sregs[SR_MSR] & MSR_IE;
332: }
333:
334: #include "cpu-all.h"
335:
336: static inline target_ulong cpu_get_pc(CPUState *env)
337: {
338: return env->sregs[SR_PC];
339: }
340:
341: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
342: target_ulong *cs_base, int *flags)
343: {
344: *pc = env->sregs[SR_PC];
345: *cs_base = 0;
1.1.1.3 root 346: *flags = (env->iflags & IFLAGS_TB_MASK) |
347: (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
1.1 root 348: }
1.1.1.2 root 349:
1.1.1.3 root 350: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 351: void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
352: int is_write, int is_exec, int is_asi, int size);
1.1 root 353: #endif
1.1.1.5 root 354:
355: static inline bool cpu_has_work(CPUState *env)
356: {
357: return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
358: }
359:
360: #include "exec-all.h"
361:
362: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
363: {
364: env->sregs[SR_PC] = tb->pc;
365: }
366:
1.1.1.3 root 367: #endif
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