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1.1 root 1: /*
2: * Microblaze MMU emulation for qemu.
3: *
4: * Copyright (c) 2009 Edgar E. Iglesias
1.1.1.5 ! root 5: * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
1.1 root 6: *
7: * This library is free software; you can redistribute it and/or
8: * modify it under the terms of the GNU Lesser General Public
9: * License as published by the Free Software Foundation; either
10: * version 2 of the License, or (at your option) any later version.
11: *
12: * This library is distributed in the hope that it will be useful,
13: * but WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15: * Lesser General Public License for more details.
16: *
17: * You should have received a copy of the GNU Lesser General Public
18: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19: */
20:
21: #include "cpu.h"
22:
23: #define D(x)
24:
25: static unsigned int tlb_decode_size(unsigned int f)
26: {
27: static const unsigned int sizes[] = {
28: 1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
29: 1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
30: };
31: assert(f < ARRAY_SIZE(sizes));
32: return sizes[f];
33: }
34:
1.1.1.5 ! root 35: static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
1.1 root 36: {
37: struct microblaze_mmu *mmu = &env->mmu;
38: unsigned int tlb_size;
39: uint32_t tlb_tag, end, t;
40:
41: t = mmu->rams[RAM_TAG][idx];
42: if (!(t & TLB_VALID))
43: return;
44:
45: tlb_tag = t & TLB_EPN_MASK;
46: tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
47: end = tlb_tag + tlb_size;
48:
49: while (tlb_tag < end) {
50: tlb_flush_page(env, tlb_tag);
51: tlb_tag += TARGET_PAGE_SIZE;
52: }
53: }
54:
1.1.1.5 ! root 55: static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
1.1 root 56: {
57: struct microblaze_mmu *mmu = &env->mmu;
58: unsigned int i;
1.1.1.3 root 59: uint32_t t;
1.1 root 60:
61: if (newpid & ~0xff)
62: qemu_log("Illegal rpid=%x\n", newpid);
63:
64: for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
65: /* Lookup and decode. */
66: t = mmu->rams[RAM_TAG][i];
67: if (t & TLB_VALID) {
68: if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
69: mmu_flush_idx(env, i);
70: }
71: }
72: }
73:
74: /* rw - 0 = read, 1 = write, 2 = fetch. */
75: unsigned int mmu_translate(struct microblaze_mmu *mmu,
76: struct microblaze_mmu_lookup *lu,
77: target_ulong vaddr, int rw, int mmu_idx)
78: {
79: unsigned int i, hit = 0;
80: unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
81: unsigned int tlb_size;
82: uint32_t tlb_tag, tlb_rpn, mask, t0;
83:
84: lu->err = ERR_MISS;
85: for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
86: uint32_t t, d;
87:
88: /* Lookup and decode. */
89: t = mmu->rams[RAM_TAG][i];
90: D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
91: if (t & TLB_VALID) {
92: tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
93: if (tlb_size < TARGET_PAGE_SIZE) {
94: qemu_log("%d pages not supported\n", tlb_size);
95: abort();
96: }
97:
98: mask = ~(tlb_size - 1);
99: tlb_tag = t & TLB_EPN_MASK;
100: if ((vaddr & mask) != (tlb_tag & mask)) {
101: D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
102: i, vaddr & mask, tlb_tag & mask));
103: continue;
104: }
105: if (mmu->tids[i]
106: && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
107: D(qemu_log("TLB %d pid=%x != tid=%x\n",
108: i, mmu->regs[MMU_R_PID], mmu->tids[i]));
109: continue;
110: }
111:
112: /* Bring in the data part. */
113: d = mmu->rams[RAM_DATA][i];
114: tlb_ex = d & TLB_EX;
115: tlb_wr = d & TLB_WR;
116:
117: /* Now lets see if there is a zone that overrides the protbits. */
118: tlb_zsel = (d >> 4) & 0xf;
119: t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
120: t0 &= 0x3;
1.1.1.2 root 121:
122: if (tlb_zsel > mmu->c_mmu_zones) {
123: qemu_log("tlb zone select out of range! %d\n", tlb_zsel);
124: t0 = 1; /* Ignore. */
125: }
126:
127: if (mmu->c_mmu == 1) {
128: t0 = 1; /* Zones are disabled. */
129: }
130:
1.1 root 131: switch (t0) {
132: case 0:
133: if (mmu_idx == MMU_USER_IDX)
134: continue;
135: break;
136: case 2:
137: if (mmu_idx != MMU_USER_IDX) {
138: tlb_ex = 1;
139: tlb_wr = 1;
140: }
141: break;
142: case 3:
143: tlb_ex = 1;
144: tlb_wr = 1;
145: break;
1.1.1.2 root 146: default: break;
1.1 root 147: }
148:
149: lu->err = ERR_PROT;
150: lu->prot = PAGE_READ;
151: if (tlb_wr)
152: lu->prot |= PAGE_WRITE;
153: else if (rw == 1)
154: goto done;
155: if (tlb_ex)
156: lu->prot |=PAGE_EXEC;
157: else if (rw == 2) {
158: goto done;
159: }
160:
161: tlb_rpn = d & TLB_RPN_MASK;
162:
163: lu->vaddr = tlb_tag;
164: lu->paddr = tlb_rpn;
165: lu->size = tlb_size;
166: lu->err = ERR_HIT;
167: lu->idx = i;
168: hit = 1;
169: goto done;
170: }
171: }
172: done:
173: D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
174: vaddr, rw, tlb_wr, tlb_ex, hit));
175: return hit;
176: }
177:
178: /* Writes/reads to the MMU's special regs end up here. */
1.1.1.5 ! root 179: uint32_t mmu_read(CPUMBState *env, uint32_t rn)
1.1 root 180: {
181: unsigned int i;
182: uint32_t r;
183:
1.1.1.2 root 184: if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
185: qemu_log("MMU access on MMU-less system\n");
186: return 0;
187: }
188:
1.1 root 189: switch (rn) {
190: /* Reads to HI/LO trig reads from the mmu rams. */
191: case MMU_R_TLBLO:
192: case MMU_R_TLBHI:
1.1.1.2 root 193: if (!(env->mmu.c_mmu_tlb_access & 1)) {
194: qemu_log("Invalid access to MMU reg %d\n", rn);
195: return 0;
196: }
197:
1.1 root 198: i = env->mmu.regs[MMU_R_TLBX] & 0xff;
199: r = env->mmu.rams[rn & 1][i];
200: if (rn == MMU_R_TLBHI)
201: env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
202: break;
1.1.1.2 root 203: case MMU_R_PID:
204: case MMU_R_ZPR:
205: if (!(env->mmu.c_mmu_tlb_access & 1)) {
206: qemu_log("Invalid access to MMU reg %d\n", rn);
207: return 0;
208: }
209: r = env->mmu.regs[rn];
210: break;
1.1 root 211: default:
212: r = env->mmu.regs[rn];
213: break;
214: }
215: D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
216: return r;
217: }
218:
1.1.1.5 ! root 219: void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
1.1 root 220: {
221: unsigned int i;
222: D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
223:
1.1.1.2 root 224: if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
225: qemu_log("MMU access on MMU-less system\n");
226: return;
227: }
228:
1.1 root 229: switch (rn) {
230: /* Writes to HI/LO trig writes to the mmu rams. */
231: case MMU_R_TLBLO:
232: case MMU_R_TLBHI:
233: i = env->mmu.regs[MMU_R_TLBX] & 0xff;
234: if (rn == MMU_R_TLBHI) {
235: if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
236: qemu_log("invalidating index %x at pc=%x\n",
237: i, env->sregs[SR_PC]);
238: env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
239: mmu_flush_idx(env, i);
240: }
241: env->mmu.rams[rn & 1][i] = v;
242:
243: D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v));
244: break;
245: case MMU_R_ZPR:
1.1.1.2 root 246: if (env->mmu.c_mmu_tlb_access <= 1) {
247: qemu_log("Invalid access to MMU reg %d\n", rn);
248: return;
249: }
250:
1.1 root 251: /* Changes to the zone protection reg flush the QEMU TLB.
252: Fortunately, these are very uncommon. */
253: if (v != env->mmu.regs[rn]) {
254: tlb_flush(env, 1);
255: }
256: env->mmu.regs[rn] = v;
257: break;
258: case MMU_R_PID:
1.1.1.2 root 259: if (env->mmu.c_mmu_tlb_access <= 1) {
260: qemu_log("Invalid access to MMU reg %d\n", rn);
261: return;
262: }
263:
1.1 root 264: if (v != env->mmu.regs[rn]) {
265: mmu_change_pid(env, v);
266: env->mmu.regs[rn] = v;
267: }
268: break;
269: case MMU_R_TLBSX:
270: {
271: struct microblaze_mmu_lookup lu;
272: int hit;
1.1.1.2 root 273:
274: if (env->mmu.c_mmu_tlb_access <= 1) {
275: qemu_log("Invalid access to MMU reg %d\n", rn);
276: return;
277: }
278:
1.1 root 279: hit = mmu_translate(&env->mmu, &lu,
280: v & TLB_EPN_MASK, 0, cpu_mmu_index(env));
281: if (hit) {
282: env->mmu.regs[MMU_R_TLBX] = lu.idx;
283: } else
284: env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
285: break;
286: }
287: default:
288: env->mmu.regs[rn] = v;
289: break;
290: }
291: }
292:
293: void mmu_init(struct microblaze_mmu *mmu)
294: {
1.1.1.2 root 295: int i;
296: for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
297: mmu->regs[i] = 0;
298: }
1.1 root 299: }
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