--- qemu/target-mips/TODO	2018/04/24 16:49:34	1.1.1.2
+++ qemu/target-mips/TODO	2018/04/24 19:52:18	1.1.1.5
@@ -4,7 +4,6 @@ Unsolved issues/bugs in the mips/mipsel
 General
 -------
 - Unimplemented ASEs:
-  - MIPS16
   - MDMX
   - SmartMIPS
   - DSP r1
@@ -17,7 +16,7 @@ General
   Existing documentation is x86-centric.
 - Reverse endianness bit not implemented
 - The TLB emulation is very inefficient:
-  Qemu's softmmu implements a x86-style MMU, with separate entries
+  QEMU's softmmu implements a x86-style MMU, with separate entries
   for read/write/execute, a TLB index which is just a modulo of the
   virtual address, and a set of TLBs for each user/kernel/supervisor
   MMU mode.
@@ -26,9 +25,10 @@ General
   up to 256 ASID tags as additional matching criterion (which roughly
   equates to 256 MMU modes). It also has a global flag which causes
   entries to match regardless of ASID.
-  To cope with these differences, Qemu currently flushes the TLB at
+  To cope with these differences, QEMU currently flushes the TLB at
   each ASID change. Using the MMU modes to implement ASIDs hinges on
   implementing the global bit efficiently.
+- save/restore of the CPU state is not implemented (see machine.c).
 
 MIPS64
 ------
@@ -36,7 +36,8 @@ MIPS64
 
 "Generic" 4Kc system emulation
 ------------------------------
-- Doesn't correspond to any real hardware.
+- Doesn't correspond to any real hardware. Should be removed some day,
+  U-Boot is the last remaining user.
 
 PICA 61 system emulation
 ------------------------
@@ -45,7 +46,7 @@ PICA 61 system emulation
 MALTA system emulation
 ----------------------
 - We fake firmware support instead of doing the real thing
-- Real firmware falls over when trying to init RAM, presumably due
-  to lacking system controller emulation.
+- Real firmware (YAMON) falls over when trying to init RAM, presumably
+  due to lacking system controller emulation.
 - Bonito system controller not implemented
 - MSC1 system controller not implemented