Return to cpu.h CVS log

Up to [Qemu by Fabrice Bellard] / qemu / target-mips

Annotation of qemu/target-mips/cpu.h, revision 1.1

1.1     ! root        1: #if !defined (__MIPS_CPU_H__)
        !             2: #define __MIPS_CPU_H__
        !             3: 
        !             4: #include "mips-defs.h"
        !             5: #include "cpu-defs.h"
        !             6: #include "config.h"
        !             7: #include "softfloat.h"
        !             8: 
        !             9: typedef union fpr_t fpr_t;
        !            10: union fpr_t {
        !            11:     double d;
        !            12:     float  f;
        !            13:     uint32_t u[2];
        !            14: };
        !            15: 
        !            16: #if defined(MIPS_USES_R4K_TLB)
        !            17: typedef struct tlb_t tlb_t;
        !            18: struct tlb_t {
        !            19:     target_ulong VPN;
        !            20:     target_ulong end;
        !            21:     uint8_t ASID;
        !            22:     uint8_t G;
        !            23:     uint8_t C[2];
        !            24:     uint8_t V[2];
        !            25:     uint8_t D[2];
        !            26:     target_ulong PFN[2];
        !            27: };
        !            28: #endif
        !            29: 
        !            30: typedef struct CPUMIPSState CPUMIPSState;
        !            31: struct CPUMIPSState {
        !            32:     /* General integer registers */
        !            33:     target_ulong gpr[32];
        !            34:     /* Special registers */
        !            35:     target_ulong PC;
        !            36:     uint32_t HI, LO;
        !            37:     uint32_t DCR; /* ? */
        !            38: #if defined(MIPS_USES_FPU)
        !            39:     /* Floating point registers */
        !            40:     fpr_t fpr[16];
        !            41:     /* Floating point special purpose registers */
        !            42:     uint32_t fcr0;
        !            43:     uint32_t fcr25;
        !            44:     uint32_t fcr26;
        !            45:     uint32_t fcr28;
        !            46:     uint32_t fcsr;
        !            47: #endif
        !            48: #if defined(MIPS_USES_R4K_TLB)
        !            49:     tlb_t tlb[16];
        !            50: #endif
        !            51:     uint32_t CP0_index;
        !            52:     uint32_t CP0_random;
        !            53:     uint32_t CP0_EntryLo0;
        !            54:     uint32_t CP0_EntryLo1;
        !            55:     uint32_t CP0_Context;
        !            56:     uint32_t CP0_PageMask;
        !            57:     uint32_t CP0_Wired;
        !            58:     uint32_t CP0_BadVAddr;
        !            59:     uint32_t CP0_Count;
        !            60:     uint32_t CP0_EntryHi;
        !            61:     uint32_t CP0_Compare;
        !            62:     uint32_t CP0_Status;
        !            63: #define CP0St_CU3   31
        !            64: #define CP0St_CU2   30
        !            65: #define CP0St_CU1   29
        !            66: #define CP0St_CU0   28
        !            67: #define CP0St_RP    27
        !            68: #define CP0St_RE    25
        !            69: #define CP0St_BEV   22
        !            70: #define CP0St_TS    21
        !            71: #define CP0St_SR    20
        !            72: #define CP0St_NMI   19
        !            73: #define CP0St_IM    8
        !            74: #define CP0St_UM    4
        !            75: #define CP0St_ERL   2
        !            76: #define CP0St_EXL   1
        !            77: #define CP0St_IE    0
        !            78:     uint32_t CP0_Cause;
        !            79: #define CP0Ca_IV   23
        !            80:     uint32_t CP0_EPC;
        !            81:     uint32_t CP0_PRid;
        !            82:     uint32_t CP0_Config0;
        !            83: #define CP0C0_M    31
        !            84: #define CP0C0_K23  28
        !            85: #define CP0C0_KU   25
        !            86: #define CP0C0_MDU  20
        !            87: #define CP0C0_MM   17
        !            88: #define CP0C0_BM   16
        !            89: #define CP0C0_BE   15
        !            90: #define CP0C0_AT   13
        !            91: #define CP0C0_AR   10
        !            92: #define CP0C0_MT   7
        !            93: #define CP0C0_K0   0
        !            94:     uint32_t CP0_Config1;
        !            95: #define CP0C1_MMU  25
        !            96: #define CP0C1_IS   22
        !            97: #define CP0C1_IL   19
        !            98: #define CP0C1_IA   16
        !            99: #define CP0C1_DS   13
        !           100: #define CP0C1_DL   10
        !           101: #define CP0C1_DA   7
        !           102: #define CP0C1_PC   4
        !           103: #define CP0C1_WR   3
        !           104: #define CP0C1_CA   2
        !           105: #define CP0C1_EP   1
        !           106: #define CP0C1_FP   0
        !           107:     uint32_t CP0_LLAddr;
        !           108:     uint32_t CP0_WatchLo;
        !           109:     uint32_t CP0_WatchHi;
        !           110:     uint32_t CP0_Debug;
        !           111: #define CPDB_DBD   31
        !           112: #define CP0DB_DM   30
        !           113: #define CP0DB_LSNM 28
        !           114: #define CP0DB_Doze 27
        !           115: #define CP0DB_Halt 26
        !           116: #define CP0DB_CNT  25
        !           117: #define CP0DB_IBEP 24
        !           118: #define CP0DB_DBEP 21
        !           119: #define CP0DB_IEXI 20
        !           120: #define CP0DB_VER  15
        !           121: #define CP0DB_DEC  10
        !           122: #define CP0DB_SSt  8
        !           123: #define CP0DB_DINT 5
        !           124: #define CP0DB_DIB  4
        !           125: #define CP0DB_DDBS 3
        !           126: #define CP0DB_DDBL 2
        !           127: #define CP0DB_DBp  1
        !           128: #define CP0DB_DSS  0
        !           129:     uint32_t CP0_DEPC;
        !           130:     uint32_t CP0_TagLo;
        !           131:     uint32_t CP0_DataLo;
        !           132:     uint32_t CP0_ErrorEPC;
        !           133:     uint32_t CP0_DESAVE;
        !           134:     /* Qemu */
        !           135: #if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)
        !           136:     double ft0, ft1, ft2;
        !           137: #endif
        !           138:     struct QEMUTimer *timer; /* Internal timer */
        !           139:     int interrupt_request;
        !           140:     jmp_buf jmp_env;
        !           141:     int exception_index;
        !           142:     int error_code;
        !           143:     int user_mode_only; /* user mode only simulation */
        !           144:     uint32_t hflags;    /* CPU State */
        !           145:     /* TMASK defines different execution modes */
        !           146: #define MIPS_HFLAGS_TMASK 0x00FF
        !           147: #define MIPS_HFLAG_MODE   0x001F /* execution modes                    */
        !           148: #define MIPS_HFLAG_UM     0x0001 /* user mode                          */
        !           149: #define MIPS_HFLAG_ERL    0x0002 /* Error mode                         */
        !           150: #define MIPS_HFLAG_EXL    0x0004 /* Exception mode                     */
        !           151: #define MIPS_HFLAG_DM     0x0008 /* Debug mode                         */
        !           152: #define MIPS_HFLAG_SM     0x0010 /* Supervisor mode                    */
        !           153: #define MIPS_HFLAG_RE     0x0040 /* Reversed endianness                */
        !           154: #define MIPS_HFLAG_DS     0x0080 /* In / out of delay slot             */
        !           155:     /* Those flags keep the branch state if the translation is interrupted
        !           156:      * between the branch instruction and the delay slot
        !           157:      */
        !           158: #define MIPS_HFLAG_BMASK  0x0F00
        !           159: #define MIPS_HFLAG_B      0x0100 /* Unconditional branch               */
        !           160: #define MIPS_HFLAG_BC     0x0200 /* Conditional branch                 */
        !           161: #define MIPS_HFLAG_BL     0x0400 /* Likely branch                      */
        !           162: #define MIPS_HFLAG_BR     0x0800 /* branch to register (can't link TB) */
        !           163:     target_ulong btarget;        /* Jump / branch target               */
        !           164:     int bcond;                   /* Branch condition (if needed)       */
        !           165:     struct TranslationBlock *current_tb; /* currently executing TB  */
        !           166:     /* soft mmu support */
        !           167:     /* in order to avoid passing too many arguments to the memory
        !           168:        write helpers, we store some rarely used information in the CPU
        !           169:        context) */
        !           170:     target_ulong mem_write_pc; /* host pc at which the memory was
        !           171:                                    written */
        !           172:     unsigned long mem_write_vaddr; /* target virtual addr at which the
        !           173:                                       memory was written */
        !           174:     /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
        !           175:     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
        !           176:     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
        !           177:     /* ice debug support */
        !           178:     target_ulong breakpoints[MAX_BREAKPOINTS];
        !           179:     int nb_breakpoints;
        !           180:     int singlestep_enabled; /* XXX: should use CPU single step mode instead */
        !           181:     /* user data */
        !           182:     void *opaque;
        !           183: };
        !           184: 
        !           185: #include "cpu-all.h"
        !           186: 
        !           187: /* Memory access type :
        !           188:  * may be needed for precise access rights control and precise exceptions.
        !           189:  */
        !           190: enum {
        !           191:     /* 1 bit to define user level / supervisor access */
        !           192:     ACCESS_USER  = 0x00,
        !           193:     ACCESS_SUPER = 0x01,
        !           194:     /* 1 bit to indicate direction */
        !           195:     ACCESS_STORE = 0x02,
        !           196:     /* Type of instruction that generated the access */
        !           197:     ACCESS_CODE  = 0x10, /* Code fetch access                */
        !           198:     ACCESS_INT   = 0x20, /* Integer load/store access        */
        !           199:     ACCESS_FLOAT = 0x30, /* floating point load/store access */
        !           200: };
        !           201: 
        !           202: /* Exceptions */
        !           203: enum {
        !           204:     EXCP_NONE          = -1,
        !           205:     EXCP_RESET         = 0,
        !           206:     EXCP_SRESET,
        !           207:     EXCP_DSS,
        !           208:     EXCP_DINT,
        !           209:     EXCP_NMI,
        !           210:     EXCP_MCHECK,
        !           211:     EXCP_EXT_INTERRUPT,
        !           212:     EXCP_DFWATCH,
        !           213:     EXCP_DIB, /* 8 */
        !           214:     EXCP_IWATCH,
        !           215:     EXCP_AdEL,
        !           216:     EXCP_AdES,
        !           217:     EXCP_TLBF,
        !           218:     EXCP_IBE,
        !           219:     EXCP_DBp,
        !           220:     EXCP_SYSCALL,
        !           221:     EXCP_BREAK,
        !           222:     EXCP_CpU, /* 16 */
        !           223:     EXCP_RI,
        !           224:     EXCP_OVERFLOW,
        !           225:     EXCP_TRAP,
        !           226:     EXCP_DDBS,
        !           227:     EXCP_DWATCH,
        !           228:     EXCP_LAE, /* 22 */
        !           229:     EXCP_SAE,
        !           230:     EXCP_LTLBL,
        !           231:     EXCP_TLBL,
        !           232:     EXCP_TLBS,
        !           233:     EXCP_DBE,
        !           234:     EXCP_DDBL,
        !           235:     EXCP_MTCP0         = 0x104, /* mtmsr instruction:               */
        !           236:                                 /* may change privilege level       */
        !           237:     EXCP_BRANCH        = 0x108, /* branch instruction               */
        !           238:     EXCP_ERET          = 0x10C, /* return from interrupt            */
        !           239:     EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
        !           240:     EXCP_FLUSH         = 0x109,
        !           241: };
        !           242: 
        !           243: int cpu_mips_exec(CPUMIPSState *s);
        !           244: CPUMIPSState *cpu_mips_init(void);
        !           245: uint32_t cpu_mips_get_clock (void);
        !           246: 
        !           247: #endif /* !defined (__MIPS_CPU_H__) */

This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.