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1.1 root 1: #if !defined (__MIPS_CPU_H__)
2: #define __MIPS_CPU_H__
3:
1.1.1.14 root 4: //#define DEBUG_OP
5:
1.1.1.2 root 6: #define TARGET_HAS_ICE 1
7:
1.1.1.5 root 8: #define ELF_MACHINE EM_MIPS
9:
1.1.1.15! root 10: #define CPUArchState struct CPUMIPSState
1.1.1.8 root 11:
1.1.1.4 root 12: #include "config.h"
1.1.1.12 root 13: #include "qemu-common.h"
1.1 root 14: #include "mips-defs.h"
15: #include "cpu-defs.h"
16: #include "softfloat.h"
17:
1.1.1.6 root 18: struct CPUMIPSState;
19:
20: typedef struct r4k_tlb_t r4k_tlb_t;
21: struct r4k_tlb_t {
22: target_ulong VPN;
23: uint32_t PageMask;
24: uint_fast8_t ASID;
25: uint_fast16_t G:1;
26: uint_fast16_t C0:3;
27: uint_fast16_t C1:3;
28: uint_fast16_t V0:1;
29: uint_fast16_t V1:1;
30: uint_fast16_t D0:1;
31: uint_fast16_t D1:1;
32: target_ulong PFN[2];
33: };
34:
1.1.1.11 root 35: #if !defined(CONFIG_USER_ONLY)
1.1.1.6 root 36: typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
37: struct CPUMIPSTLBContext {
38: uint32_t nb_tlb;
39: uint32_t tlb_in_use;
1.1.1.9 root 40: int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
1.1.1.8 root 41: void (*helper_tlbwi) (void);
42: void (*helper_tlbwr) (void);
43: void (*helper_tlbp) (void);
44: void (*helper_tlbr) (void);
1.1.1.6 root 45: union {
46: struct {
47: r4k_tlb_t tlb[MIPS_TLB_MAX];
48: } r4k;
49: } mmu;
50: };
1.1.1.11 root 51: #endif
1.1.1.5 root 52:
1.1 root 53: typedef union fpr_t fpr_t;
54: union fpr_t {
1.1.1.4 root 55: float64 fd; /* ieee double precision */
56: float32 fs[2];/* ieee single precision */
1.1.1.6 root 57: uint64_t d; /* binary double fixed-point */
1.1.1.4 root 58: uint32_t w[2]; /* binary single fixed-point */
1.1 root 59: };
1.1.1.4 root 60: /* define FP_ENDIAN_IDX to access the same location
1.1.1.13 root 61: * in the fpr_t union regardless of the host endianness
1.1.1.4 root 62: */
1.1.1.9 root 63: #if defined(HOST_WORDS_BIGENDIAN)
1.1.1.4 root 64: # define FP_ENDIAN_IDX 1
65: #else
66: # define FP_ENDIAN_IDX 0
67: #endif
1.1 root 68:
1.1.1.6 root 69: typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
70: struct CPUMIPSFPUContext {
1.1 root 71: /* Floating point registers */
1.1.1.6 root 72: fpr_t fpr[32];
1.1.1.4 root 73: float_status fp_status;
1.1.1.6 root 74: /* fpu implementation/revision register (fir) */
1.1 root 75: uint32_t fcr0;
1.1.1.6 root 76: #define FCR0_F64 22
77: #define FCR0_L 21
78: #define FCR0_W 20
79: #define FCR0_3D 19
80: #define FCR0_PS 18
81: #define FCR0_D 17
82: #define FCR0_S 16
83: #define FCR0_PRID 8
84: #define FCR0_REV 0
1.1.1.4 root 85: /* fcsr */
86: uint32_t fcr31;
1.1.1.7 root 87: #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
88: #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
89: #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
1.1.1.6 root 90: #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
91: #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
92: #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
93: #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
94: #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
95: #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
96: #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
1.1.1.4 root 97: #define FP_INEXACT 1
98: #define FP_UNDERFLOW 2
99: #define FP_OVERFLOW 4
100: #define FP_DIV0 8
101: #define FP_INVALID 16
102: #define FP_UNIMPLEMENTED 32
1.1.1.6 root 103: };
104:
105: #define NB_MMU_MODES 3
106:
107: typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
108: struct CPUMIPSMVPContext {
109: int32_t CP0_MVPControl;
110: #define CP0MVPCo_CPA 3
111: #define CP0MVPCo_STLB 2
112: #define CP0MVPCo_VPC 1
113: #define CP0MVPCo_EVP 0
114: int32_t CP0_MVPConf0;
115: #define CP0MVPC0_M 31
116: #define CP0MVPC0_TLBS 29
117: #define CP0MVPC0_GS 28
118: #define CP0MVPC0_PCP 27
119: #define CP0MVPC0_PTLBE 16
120: #define CP0MVPC0_TCA 15
121: #define CP0MVPC0_PVPE 10
122: #define CP0MVPC0_PTC 0
123: int32_t CP0_MVPConf1;
124: #define CP0MVPC1_CIM 31
125: #define CP0MVPC1_CIF 30
126: #define CP0MVPC1_PCX 20
127: #define CP0MVPC1_PCP2 10
128: #define CP0MVPC1_PCP1 0
129: };
130:
131: typedef struct mips_def_t mips_def_t;
132:
133: #define MIPS_SHADOW_SET_MAX 16
134: #define MIPS_TC_MAX 5
1.1.1.7 root 135: #define MIPS_FPU_MAX 1
1.1.1.6 root 136: #define MIPS_DSP_ACC 4
137:
1.1.1.7 root 138: typedef struct TCState TCState;
139: struct TCState {
140: target_ulong gpr[32];
141: target_ulong PC;
142: target_ulong HI[MIPS_DSP_ACC];
143: target_ulong LO[MIPS_DSP_ACC];
144: target_ulong ACX[MIPS_DSP_ACC];
145: target_ulong DSPControl;
146: int32_t CP0_TCStatus;
147: #define CP0TCSt_TCU3 31
148: #define CP0TCSt_TCU2 30
149: #define CP0TCSt_TCU1 29
150: #define CP0TCSt_TCU0 28
151: #define CP0TCSt_TMX 27
152: #define CP0TCSt_RNST 23
153: #define CP0TCSt_TDS 21
154: #define CP0TCSt_DT 20
155: #define CP0TCSt_DA 15
156: #define CP0TCSt_A 13
157: #define CP0TCSt_TKSU 11
158: #define CP0TCSt_IXMT 10
159: #define CP0TCSt_TASID 0
160: int32_t CP0_TCBind;
161: #define CP0TCBd_CurTC 21
162: #define CP0TCBd_TBE 17
163: #define CP0TCBd_CurVPE 0
164: target_ulong CP0_TCHalt;
165: target_ulong CP0_TCContext;
166: target_ulong CP0_TCSchedule;
167: target_ulong CP0_TCScheFBack;
168: int32_t CP0_Debug_tcstatus;
169: };
170:
1.1.1.6 root 171: typedef struct CPUMIPSState CPUMIPSState;
172: struct CPUMIPSState {
1.1.1.7 root 173: TCState active_tc;
174: CPUMIPSFPUContext active_fpu;
1.1.1.6 root 175:
176: uint32_t current_tc;
1.1.1.7 root 177: uint32_t current_fpu;
1.1.1.6 root 178:
179: uint32_t SEGBITS;
180: uint32_t PABITS;
1.1.1.7 root 181: target_ulong SEGMask;
1.1.1.6 root 182: target_ulong PAMask;
183:
1.1.1.5 root 184: int32_t CP0_Index;
1.1.1.6 root 185: /* CP0_MVP* are per MVP registers. */
1.1.1.5 root 186: int32_t CP0_Random;
1.1.1.6 root 187: int32_t CP0_VPEControl;
188: #define CP0VPECo_YSI 21
189: #define CP0VPECo_GSI 20
190: #define CP0VPECo_EXCPT 16
191: #define CP0VPECo_TE 15
192: #define CP0VPECo_TargTC 0
193: int32_t CP0_VPEConf0;
194: #define CP0VPEC0_M 31
195: #define CP0VPEC0_XTC 21
196: #define CP0VPEC0_TCS 19
197: #define CP0VPEC0_SCS 18
198: #define CP0VPEC0_DSC 17
199: #define CP0VPEC0_ICS 16
200: #define CP0VPEC0_MVP 1
201: #define CP0VPEC0_VPA 0
202: int32_t CP0_VPEConf1;
203: #define CP0VPEC1_NCX 20
204: #define CP0VPEC1_NCP2 10
205: #define CP0VPEC1_NCP1 0
206: target_ulong CP0_YQMask;
207: target_ulong CP0_VPESchedule;
208: target_ulong CP0_VPEScheFBack;
209: int32_t CP0_VPEOpt;
210: #define CP0VPEOpt_IWX7 15
211: #define CP0VPEOpt_IWX6 14
212: #define CP0VPEOpt_IWX5 13
213: #define CP0VPEOpt_IWX4 12
214: #define CP0VPEOpt_IWX3 11
215: #define CP0VPEOpt_IWX2 10
216: #define CP0VPEOpt_IWX1 9
217: #define CP0VPEOpt_IWX0 8
218: #define CP0VPEOpt_DWX7 7
219: #define CP0VPEOpt_DWX6 6
220: #define CP0VPEOpt_DWX5 5
221: #define CP0VPEOpt_DWX4 4
222: #define CP0VPEOpt_DWX3 3
223: #define CP0VPEOpt_DWX2 2
224: #define CP0VPEOpt_DWX1 1
225: #define CP0VPEOpt_DWX0 0
1.1.1.5 root 226: target_ulong CP0_EntryLo0;
227: target_ulong CP0_EntryLo1;
228: target_ulong CP0_Context;
229: int32_t CP0_PageMask;
230: int32_t CP0_PageGrain;
231: int32_t CP0_Wired;
1.1.1.6 root 232: int32_t CP0_SRSConf0_rw_bitmask;
233: int32_t CP0_SRSConf0;
234: #define CP0SRSC0_M 31
235: #define CP0SRSC0_SRS3 20
236: #define CP0SRSC0_SRS2 10
237: #define CP0SRSC0_SRS1 0
238: int32_t CP0_SRSConf1_rw_bitmask;
239: int32_t CP0_SRSConf1;
240: #define CP0SRSC1_M 31
241: #define CP0SRSC1_SRS6 20
242: #define CP0SRSC1_SRS5 10
243: #define CP0SRSC1_SRS4 0
244: int32_t CP0_SRSConf2_rw_bitmask;
245: int32_t CP0_SRSConf2;
246: #define CP0SRSC2_M 31
247: #define CP0SRSC2_SRS9 20
248: #define CP0SRSC2_SRS8 10
249: #define CP0SRSC2_SRS7 0
250: int32_t CP0_SRSConf3_rw_bitmask;
251: int32_t CP0_SRSConf3;
252: #define CP0SRSC3_M 31
253: #define CP0SRSC3_SRS12 20
254: #define CP0SRSC3_SRS11 10
255: #define CP0SRSC3_SRS10 0
256: int32_t CP0_SRSConf4_rw_bitmask;
257: int32_t CP0_SRSConf4;
258: #define CP0SRSC4_SRS15 20
259: #define CP0SRSC4_SRS14 10
260: #define CP0SRSC4_SRS13 0
1.1.1.5 root 261: int32_t CP0_HWREna;
262: target_ulong CP0_BadVAddr;
263: int32_t CP0_Count;
264: target_ulong CP0_EntryHi;
265: int32_t CP0_Compare;
266: int32_t CP0_Status;
1.1 root 267: #define CP0St_CU3 31
268: #define CP0St_CU2 30
269: #define CP0St_CU1 29
270: #define CP0St_CU0 28
271: #define CP0St_RP 27
1.1.1.4 root 272: #define CP0St_FR 26
1.1 root 273: #define CP0St_RE 25
1.1.1.5 root 274: #define CP0St_MX 24
275: #define CP0St_PX 23
1.1 root 276: #define CP0St_BEV 22
277: #define CP0St_TS 21
278: #define CP0St_SR 20
279: #define CP0St_NMI 19
280: #define CP0St_IM 8
1.1.1.5 root 281: #define CP0St_KX 7
282: #define CP0St_SX 6
283: #define CP0St_UX 5
1.1.1.6 root 284: #define CP0St_KSU 3
1.1 root 285: #define CP0St_ERL 2
286: #define CP0St_EXL 1
287: #define CP0St_IE 0
1.1.1.5 root 288: int32_t CP0_IntCtl;
1.1.1.6 root 289: #define CP0IntCtl_IPTI 29
290: #define CP0IntCtl_IPPC1 26
291: #define CP0IntCtl_VS 5
1.1.1.5 root 292: int32_t CP0_SRSCtl;
1.1.1.6 root 293: #define CP0SRSCtl_HSS 26
294: #define CP0SRSCtl_EICSS 18
295: #define CP0SRSCtl_ESS 12
296: #define CP0SRSCtl_PSS 6
297: #define CP0SRSCtl_CSS 0
1.1.1.5 root 298: int32_t CP0_SRSMap;
1.1.1.6 root 299: #define CP0SRSMap_SSV7 28
300: #define CP0SRSMap_SSV6 24
301: #define CP0SRSMap_SSV5 20
302: #define CP0SRSMap_SSV4 16
303: #define CP0SRSMap_SSV3 12
304: #define CP0SRSMap_SSV2 8
305: #define CP0SRSMap_SSV1 4
306: #define CP0SRSMap_SSV0 0
1.1.1.5 root 307: int32_t CP0_Cause;
308: #define CP0Ca_BD 31
309: #define CP0Ca_TI 30
310: #define CP0Ca_CE 28
311: #define CP0Ca_DC 27
312: #define CP0Ca_PCI 26
1.1 root 313: #define CP0Ca_IV 23
1.1.1.5 root 314: #define CP0Ca_WP 22
315: #define CP0Ca_IP 8
316: #define CP0Ca_IP_mask 0x0000FF00
317: #define CP0Ca_EC 2
318: target_ulong CP0_EPC;
319: int32_t CP0_PRid;
320: int32_t CP0_EBase;
321: int32_t CP0_Config0;
1.1 root 322: #define CP0C0_M 31
323: #define CP0C0_K23 28
324: #define CP0C0_KU 25
325: #define CP0C0_MDU 20
326: #define CP0C0_MM 17
327: #define CP0C0_BM 16
328: #define CP0C0_BE 15
329: #define CP0C0_AT 13
330: #define CP0C0_AR 10
331: #define CP0C0_MT 7
1.1.1.5 root 332: #define CP0C0_VI 3
1.1 root 333: #define CP0C0_K0 0
1.1.1.5 root 334: int32_t CP0_Config1;
335: #define CP0C1_M 31
1.1 root 336: #define CP0C1_MMU 25
337: #define CP0C1_IS 22
338: #define CP0C1_IL 19
339: #define CP0C1_IA 16
340: #define CP0C1_DS 13
341: #define CP0C1_DL 10
342: #define CP0C1_DA 7
1.1.1.5 root 343: #define CP0C1_C2 6
344: #define CP0C1_MD 5
1.1 root 345: #define CP0C1_PC 4
346: #define CP0C1_WR 3
347: #define CP0C1_CA 2
348: #define CP0C1_EP 1
349: #define CP0C1_FP 0
1.1.1.5 root 350: int32_t CP0_Config2;
351: #define CP0C2_M 31
352: #define CP0C2_TU 28
353: #define CP0C2_TS 24
354: #define CP0C2_TL 20
355: #define CP0C2_TA 16
356: #define CP0C2_SU 12
357: #define CP0C2_SS 8
358: #define CP0C2_SL 4
359: #define CP0C2_SA 0
360: int32_t CP0_Config3;
361: #define CP0C3_M 31
1.1.1.11 root 362: #define CP0C3_ISA_ON_EXC 16
1.1.1.5 root 363: #define CP0C3_DSPP 10
364: #define CP0C3_LPA 7
365: #define CP0C3_VEIC 6
366: #define CP0C3_VInt 5
367: #define CP0C3_SP 4
368: #define CP0C3_MT 2
369: #define CP0C3_SM 1
370: #define CP0C3_TL 0
1.1.1.6 root 371: int32_t CP0_Config6;
372: int32_t CP0_Config7;
373: /* XXX: Maybe make LLAddr per-TC? */
1.1.1.9 root 374: target_ulong lladdr;
1.1.1.8 root 375: target_ulong llval;
376: target_ulong llnewval;
377: target_ulong llreg;
1.1.1.9 root 378: target_ulong CP0_LLAddr_rw_bitmask;
379: int CP0_LLAddr_shift;
1.1.1.6 root 380: target_ulong CP0_WatchLo[8];
381: int32_t CP0_WatchHi[8];
1.1.1.5 root 382: target_ulong CP0_XContext;
383: int32_t CP0_Framemask;
384: int32_t CP0_Debug;
1.1.1.6 root 385: #define CP0DB_DBD 31
1.1 root 386: #define CP0DB_DM 30
387: #define CP0DB_LSNM 28
388: #define CP0DB_Doze 27
389: #define CP0DB_Halt 26
390: #define CP0DB_CNT 25
391: #define CP0DB_IBEP 24
392: #define CP0DB_DBEP 21
393: #define CP0DB_IEXI 20
394: #define CP0DB_VER 15
395: #define CP0DB_DEC 10
396: #define CP0DB_SSt 8
397: #define CP0DB_DINT 5
398: #define CP0DB_DIB 4
399: #define CP0DB_DDBS 3
400: #define CP0DB_DDBL 2
401: #define CP0DB_DBp 1
402: #define CP0DB_DSS 0
1.1.1.5 root 403: target_ulong CP0_DEPC;
404: int32_t CP0_Performance0;
405: int32_t CP0_TagLo;
406: int32_t CP0_DataLo;
407: int32_t CP0_TagHi;
408: int32_t CP0_DataHi;
409: target_ulong CP0_ErrorEPC;
410: int32_t CP0_DESAVE;
1.1.1.7 root 411: /* We waste some space so we can handle shadow registers like TCs. */
412: TCState tcs[MIPS_SHADOW_SET_MAX];
413: CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
1.1.1.15! root 414: /* QEMU */
1.1 root 415: int error_code;
416: uint32_t hflags; /* CPU State */
417: /* TMASK defines different execution modes */
1.1.1.11 root 418: #define MIPS_HFLAG_TMASK 0x007FF
419: #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
1.1.1.6 root 420: /* The KSU flags must be the lowest bits in hflags. The flag order
421: must be the same as defined for CP0 Status. This allows to use
422: the bits as the value of mmu_idx. */
1.1.1.11 root 423: #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
424: #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
425: #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
426: #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
427: #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
428: #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
429: #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
430: #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
431: #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
1.1.1.6 root 432: /* True if the MIPS IV COP1X instructions can be used. This also
433: controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
434: and RSQRT.D. */
1.1.1.11 root 435: #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
436: #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
437: #define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */
438: #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
439: #define MIPS_HFLAG_M16_SHIFT 10
1.1.1.2 root 440: /* If translation is interrupted between the branch instruction and
441: * the delay slot, record what type of branch it is so that we can
442: * resume translation properly. It might be possible to reduce
443: * this from three bits to two. */
1.1.1.11 root 444: #define MIPS_HFLAG_BMASK_BASE 0x03800
445: #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
446: #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
447: #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
448: #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
449: /* Extra flags about the current pending branch. */
450: #define MIPS_HFLAG_BMASK_EXT 0x3C000
451: #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
452: #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
453: #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
454: #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */
455: #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1.1 root 456: target_ulong btarget; /* Jump / branch target */
1.1.1.8 root 457: target_ulong bcond; /* Branch condition (if needed) */
1.1.1.2 root 458:
1.1.1.5 root 459: int SYNCI_Step; /* Address step size for SYNCI */
460: int CCRes; /* Cycle count resolution/divisor */
1.1.1.6 root 461: uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
462: uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
463: int insn_flags; /* Supported instruction set */
464:
1.1.1.7 root 465: target_ulong tls_value; /* For usermode emulation */
1.1.1.5 root 466:
1.1.1.2 root 467: CPU_COMMON
1.1.1.5 root 468:
1.1.1.9 root 469: CPUMIPSMVPContext *mvp;
1.1.1.11 root 470: #if !defined(CONFIG_USER_ONLY)
1.1.1.9 root 471: CPUMIPSTLBContext *tlb;
1.1.1.11 root 472: #endif
1.1.1.9 root 473:
1.1.1.6 root 474: const mips_def_t *cpu_model;
475: void *irq[8];
1.1.1.5 root 476: struct QEMUTimer *timer; /* Internal timer */
1.1 root 477: };
478:
1.1.1.15! root 479: #include "cpu-qom.h"
! 480:
1.1.1.11 root 481: #if !defined(CONFIG_USER_ONLY)
1.1.1.9 root 482: int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
1.1.1.6 root 483: target_ulong address, int rw, int access_type);
1.1.1.9 root 484: int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
1.1.1.6 root 485: target_ulong address, int rw, int access_type);
1.1.1.9 root 486: int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
1.1.1.6 root 487: target_ulong address, int rw, int access_type);
1.1.1.8 root 488: void r4k_helper_tlbwi (void);
489: void r4k_helper_tlbwr (void);
490: void r4k_helper_tlbp (void);
491: void r4k_helper_tlbr (void);
1.1.1.6 root 492:
1.1.1.15! root 493: void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr,
1.1.1.13 root 494: int is_write, int is_exec, int unused, int size);
1.1.1.11 root 495: #endif
496:
1.1.1.12 root 497: void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1.1.1.6 root 498:
499: #define cpu_init cpu_mips_init
500: #define cpu_exec cpu_mips_exec
501: #define cpu_gen_code cpu_mips_gen_code
502: #define cpu_signal_handler cpu_mips_signal_handler
503: #define cpu_list mips_cpu_list
504:
1.1.1.7 root 505: #define CPU_SAVE_VERSION 3
506:
1.1.1.6 root 507: /* MMU modes definitions. We carefully match the indices with our
508: hflags layout. */
509: #define MMU_MODE0_SUFFIX _kernel
510: #define MMU_MODE1_SUFFIX _super
511: #define MMU_MODE2_SUFFIX _user
512: #define MMU_USER_IDX 2
1.1.1.15! root 513: static inline int cpu_mmu_index (CPUMIPSState *env)
1.1.1.6 root 514: {
515: return env->hflags & MIPS_HFLAG_KSU;
516: }
517:
1.1.1.15! root 518: static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp)
1.1.1.7 root 519: {
520: if (newsp)
521: env->active_tc.gpr[29] = newsp;
522: env->active_tc.gpr[7] = 0;
523: env->active_tc.gpr[2] = 0;
524: }
525:
1.1.1.15! root 526: static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
1.1.1.12 root 527: {
528: int32_t pending;
529: int32_t status;
530: int r;
531:
532: if (!(env->CP0_Status & (1 << CP0St_IE)) ||
533: (env->CP0_Status & (1 << CP0St_EXL)) ||
534: (env->CP0_Status & (1 << CP0St_ERL)) ||
1.1.1.14 root 535: /* Note that the TCStatus IXMT field is initialized to zero,
536: and only MT capable cores can set it to one. So we don't
537: need to check for MT capabilities here. */
538: (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
1.1.1.12 root 539: (env->hflags & MIPS_HFLAG_DM)) {
540: /* Interrupts are disabled */
541: return 0;
542: }
543:
544: pending = env->CP0_Cause & CP0Ca_IP_mask;
545: status = env->CP0_Status & CP0Ca_IP_mask;
546:
547: if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
548: /* A MIPS configured with a vectorizing external interrupt controller
549: will feed a vector into the Cause pending lines. The core treats
550: the status lines as a vector level, not as indiviual masks. */
551: r = pending > status;
552: } else {
553: /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
554: treats the pending lines as individual interrupt lines, the status
555: lines are individual masks. */
556: r = pending & status;
557: }
558: return r;
559: }
560:
1.1 root 561: #include "cpu-all.h"
562:
563: /* Memory access type :
564: * may be needed for precise access rights control and precise exceptions.
565: */
566: enum {
567: /* 1 bit to define user level / supervisor access */
568: ACCESS_USER = 0x00,
569: ACCESS_SUPER = 0x01,
570: /* 1 bit to indicate direction */
571: ACCESS_STORE = 0x02,
572: /* Type of instruction that generated the access */
573: ACCESS_CODE = 0x10, /* Code fetch access */
574: ACCESS_INT = 0x20, /* Integer load/store access */
575: ACCESS_FLOAT = 0x30, /* floating point load/store access */
576: };
577:
578: /* Exceptions */
579: enum {
580: EXCP_NONE = -1,
581: EXCP_RESET = 0,
582: EXCP_SRESET,
583: EXCP_DSS,
584: EXCP_DINT,
1.1.1.6 root 585: EXCP_DDBL,
586: EXCP_DDBS,
1.1 root 587: EXCP_NMI,
588: EXCP_MCHECK,
1.1.1.6 root 589: EXCP_EXT_INTERRUPT, /* 8 */
1.1 root 590: EXCP_DFWATCH,
1.1.1.6 root 591: EXCP_DIB,
1.1 root 592: EXCP_IWATCH,
593: EXCP_AdEL,
594: EXCP_AdES,
595: EXCP_TLBF,
596: EXCP_IBE,
1.1.1.6 root 597: EXCP_DBp, /* 16 */
1.1 root 598: EXCP_SYSCALL,
1.1.1.6 root 599: EXCP_BREAK,
1.1.1.2 root 600: EXCP_CpU,
1.1 root 601: EXCP_RI,
602: EXCP_OVERFLOW,
603: EXCP_TRAP,
1.1.1.6 root 604: EXCP_FPE,
605: EXCP_DWATCH, /* 24 */
1.1 root 606: EXCP_LTLBL,
607: EXCP_TLBL,
608: EXCP_TLBS,
609: EXCP_DBE,
1.1.1.6 root 610: EXCP_THREAD,
611: EXCP_MDMX,
612: EXCP_C2E,
613: EXCP_CACHE, /* 32 */
614:
615: EXCP_LAST = EXCP_CACHE,
1.1 root 616: };
1.1.1.8 root 617: /* Dummy exception for conditional stores. */
618: #define EXCP_SC 0x100
1.1 root 619:
1.1.1.14 root 620: /*
621: * This is an interrnally generated WAKE request line.
622: * It is driven by the CPU itself. Raised when the MT
623: * block wants to wake a VPE from an inactive state and
624: * cleared when VPE goes from active to inactive.
625: */
626: #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
627:
1.1 root 628: int cpu_mips_exec(CPUMIPSState *s);
1.1.1.6 root 629: CPUMIPSState *cpu_mips_init(const char *cpu_model);
630: int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
1.1 root 631:
1.1.1.7 root 632: /* mips_timer.c */
1.1.1.15! root 633: uint32_t cpu_mips_get_random (CPUMIPSState *env);
! 634: uint32_t cpu_mips_get_count (CPUMIPSState *env);
! 635: void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
! 636: void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
! 637: void cpu_mips_start_count(CPUMIPSState *env);
! 638: void cpu_mips_stop_count(CPUMIPSState *env);
1.1.1.7 root 639:
640: /* mips_int.c */
1.1.1.15! root 641: void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1.1.1.7 root 642:
643: /* helper.c */
1.1.1.15! root 644: int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
1.1.1.14 root 645: int mmu_idx);
1.1.1.9 root 646: #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
1.1.1.15! root 647: void do_interrupt (CPUMIPSState *env);
1.1.1.11 root 648: #if !defined(CONFIG_USER_ONLY)
1.1.1.15! root 649: void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
! 650: target_phys_addr_t cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
1.1.1.10 root 651: int rw);
1.1.1.11 root 652: #endif
1.1.1.7 root 653:
1.1.1.15! root 654: static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
1.1.1.7 root 655: target_ulong *cs_base, int *flags)
656: {
657: *pc = env->active_tc.PC;
658: *cs_base = 0;
659: *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
660: }
661:
1.1.1.15! root 662: static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls)
1.1.1.8 root 663: {
664: env->tls_value = newtls;
665: }
666:
1.1.1.15! root 667: static inline int mips_vpe_active(CPUMIPSState *env)
1.1.1.14 root 668: {
669: int active = 1;
670:
671: /* Check that the VPE is enabled. */
672: if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
673: active = 0;
674: }
1.1.1.15! root 675: /* Check that the VPE is activated. */
1.1.1.14 root 676: if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
677: active = 0;
678: }
679:
680: /* Now verify that there are active thread contexts in the VPE.
681:
682: This assumes the CPU model will internally reschedule threads
683: if the active one goes to sleep. If there are no threads available
684: the active one will be in a sleeping state, and we can turn off
685: the entire VPE. */
686: if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
687: /* TC is not activated. */
688: active = 0;
689: }
690: if (env->active_tc.CP0_TCHalt & 1) {
691: /* TC is in halt state. */
692: active = 0;
693: }
694:
695: return active;
696: }
697:
1.1.1.15! root 698: static inline int cpu_has_work(CPUMIPSState *env)
1.1.1.13 root 699: {
700: int has_work = 0;
701:
702: /* It is implementation dependent if non-enabled interrupts
703: wake-up the CPU, however most of the implementations only
704: check for interrupts that can be taken. */
705: if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
706: cpu_mips_hw_interrupts_pending(env)) {
707: has_work = 1;
708: }
709:
1.1.1.14 root 710: /* MIPS-MT has the ability to halt the CPU. */
711: if (env->CP0_Config3 & (1 << CP0C3_MT)) {
712: /* The QEMU model will issue an _WAKE request whenever the CPUs
713: should be woken up. */
714: if (env->interrupt_request & CPU_INTERRUPT_WAKE) {
715: has_work = 1;
716: }
717:
718: if (!mips_vpe_active(env)) {
719: has_work = 0;
720: }
721: }
1.1.1.13 root 722: return has_work;
723: }
724:
725: #include "exec-all.h"
726:
1.1.1.15! root 727: static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
1.1.1.13 root 728: {
729: env->active_tc.PC = tb->pc;
730: env->hflags &= ~MIPS_HFLAG_BMASK;
731: env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
732: }
733:
1.1 root 734: #endif /* !defined (__MIPS_CPU_H__) */
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