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1.1 root 1: #if !defined (__MIPS_CPU_H__)
2: #define __MIPS_CPU_H__
3:
1.1.1.2 ! root 4: #define TARGET_HAS_ICE 1
! 5:
1.1 root 6: #include "mips-defs.h"
7: #include "cpu-defs.h"
8: #include "config.h"
9: #include "softfloat.h"
10:
11: typedef union fpr_t fpr_t;
12: union fpr_t {
13: double d;
14: float f;
15: uint32_t u[2];
16: };
17:
18: #if defined(MIPS_USES_R4K_TLB)
19: typedef struct tlb_t tlb_t;
20: struct tlb_t {
21: target_ulong VPN;
22: target_ulong end;
1.1.1.2 ! root 23: target_ulong end2;
1.1 root 24: uint8_t ASID;
25: uint8_t G;
26: uint8_t C[2];
27: uint8_t V[2];
28: uint8_t D[2];
29: target_ulong PFN[2];
30: };
31: #endif
32:
33: typedef struct CPUMIPSState CPUMIPSState;
34: struct CPUMIPSState {
35: /* General integer registers */
36: target_ulong gpr[32];
37: /* Special registers */
38: target_ulong PC;
39: uint32_t HI, LO;
40: uint32_t DCR; /* ? */
41: #if defined(MIPS_USES_FPU)
42: /* Floating point registers */
43: fpr_t fpr[16];
44: /* Floating point special purpose registers */
45: uint32_t fcr0;
46: uint32_t fcr25;
47: uint32_t fcr26;
48: uint32_t fcr28;
49: uint32_t fcsr;
50: #endif
51: #if defined(MIPS_USES_R4K_TLB)
52: tlb_t tlb[16];
53: #endif
54: uint32_t CP0_index;
55: uint32_t CP0_random;
56: uint32_t CP0_EntryLo0;
57: uint32_t CP0_EntryLo1;
58: uint32_t CP0_Context;
59: uint32_t CP0_PageMask;
60: uint32_t CP0_Wired;
61: uint32_t CP0_BadVAddr;
62: uint32_t CP0_Count;
63: uint32_t CP0_EntryHi;
64: uint32_t CP0_Compare;
65: uint32_t CP0_Status;
66: #define CP0St_CU3 31
67: #define CP0St_CU2 30
68: #define CP0St_CU1 29
69: #define CP0St_CU0 28
70: #define CP0St_RP 27
71: #define CP0St_RE 25
72: #define CP0St_BEV 22
73: #define CP0St_TS 21
74: #define CP0St_SR 20
75: #define CP0St_NMI 19
76: #define CP0St_IM 8
77: #define CP0St_UM 4
78: #define CP0St_ERL 2
79: #define CP0St_EXL 1
80: #define CP0St_IE 0
81: uint32_t CP0_Cause;
82: #define CP0Ca_IV 23
83: uint32_t CP0_EPC;
84: uint32_t CP0_PRid;
85: uint32_t CP0_Config0;
86: #define CP0C0_M 31
87: #define CP0C0_K23 28
88: #define CP0C0_KU 25
89: #define CP0C0_MDU 20
90: #define CP0C0_MM 17
91: #define CP0C0_BM 16
92: #define CP0C0_BE 15
93: #define CP0C0_AT 13
94: #define CP0C0_AR 10
95: #define CP0C0_MT 7
96: #define CP0C0_K0 0
97: uint32_t CP0_Config1;
98: #define CP0C1_MMU 25
99: #define CP0C1_IS 22
100: #define CP0C1_IL 19
101: #define CP0C1_IA 16
102: #define CP0C1_DS 13
103: #define CP0C1_DL 10
104: #define CP0C1_DA 7
105: #define CP0C1_PC 4
106: #define CP0C1_WR 3
107: #define CP0C1_CA 2
108: #define CP0C1_EP 1
109: #define CP0C1_FP 0
110: uint32_t CP0_LLAddr;
111: uint32_t CP0_WatchLo;
112: uint32_t CP0_WatchHi;
113: uint32_t CP0_Debug;
114: #define CPDB_DBD 31
115: #define CP0DB_DM 30
116: #define CP0DB_LSNM 28
117: #define CP0DB_Doze 27
118: #define CP0DB_Halt 26
119: #define CP0DB_CNT 25
120: #define CP0DB_IBEP 24
121: #define CP0DB_DBEP 21
122: #define CP0DB_IEXI 20
123: #define CP0DB_VER 15
124: #define CP0DB_DEC 10
125: #define CP0DB_SSt 8
126: #define CP0DB_DINT 5
127: #define CP0DB_DIB 4
128: #define CP0DB_DDBS 3
129: #define CP0DB_DDBL 2
130: #define CP0DB_DBp 1
131: #define CP0DB_DSS 0
132: uint32_t CP0_DEPC;
133: uint32_t CP0_TagLo;
134: uint32_t CP0_DataLo;
135: uint32_t CP0_ErrorEPC;
136: uint32_t CP0_DESAVE;
137: /* Qemu */
138: #if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)
139: double ft0, ft1, ft2;
140: #endif
141: struct QEMUTimer *timer; /* Internal timer */
142: int interrupt_request;
143: jmp_buf jmp_env;
144: int exception_index;
145: int error_code;
146: int user_mode_only; /* user mode only simulation */
147: uint32_t hflags; /* CPU State */
148: /* TMASK defines different execution modes */
149: #define MIPS_HFLAGS_TMASK 0x00FF
150: #define MIPS_HFLAG_MODE 0x001F /* execution modes */
151: #define MIPS_HFLAG_UM 0x0001 /* user mode */
152: #define MIPS_HFLAG_ERL 0x0002 /* Error mode */
153: #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
154: #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
155: #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
156: #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
1.1.1.2 ! root 157: /* If translation is interrupted between the branch instruction and
! 158: * the delay slot, record what type of branch it is so that we can
! 159: * resume translation properly. It might be possible to reduce
! 160: * this from three bits to two. */
! 161: #define MIPS_HFLAG_BMASK 0x0380
! 162: #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
! 163: #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
! 164: #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
! 165: #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
1.1 root 166: target_ulong btarget; /* Jump / branch target */
167: int bcond; /* Branch condition (if needed) */
1.1.1.2 ! root 168:
! 169: int halted; /* TRUE if the CPU is in suspend state */
! 170:
! 171: CPU_COMMON
1.1 root 172: };
173:
174: #include "cpu-all.h"
175:
176: /* Memory access type :
177: * may be needed for precise access rights control and precise exceptions.
178: */
179: enum {
180: /* 1 bit to define user level / supervisor access */
181: ACCESS_USER = 0x00,
182: ACCESS_SUPER = 0x01,
183: /* 1 bit to indicate direction */
184: ACCESS_STORE = 0x02,
185: /* Type of instruction that generated the access */
186: ACCESS_CODE = 0x10, /* Code fetch access */
187: ACCESS_INT = 0x20, /* Integer load/store access */
188: ACCESS_FLOAT = 0x30, /* floating point load/store access */
189: };
190:
191: /* Exceptions */
192: enum {
193: EXCP_NONE = -1,
194: EXCP_RESET = 0,
195: EXCP_SRESET,
196: EXCP_DSS,
197: EXCP_DINT,
198: EXCP_NMI,
199: EXCP_MCHECK,
200: EXCP_EXT_INTERRUPT,
201: EXCP_DFWATCH,
202: EXCP_DIB, /* 8 */
203: EXCP_IWATCH,
204: EXCP_AdEL,
205: EXCP_AdES,
206: EXCP_TLBF,
207: EXCP_IBE,
208: EXCP_DBp,
209: EXCP_SYSCALL,
1.1.1.2 ! root 210: EXCP_BREAK, /* 16 */
! 211: EXCP_CpU,
1.1 root 212: EXCP_RI,
213: EXCP_OVERFLOW,
214: EXCP_TRAP,
215: EXCP_DDBS,
216: EXCP_DWATCH,
1.1.1.2 ! root 217: EXCP_LAE,
! 218: EXCP_SAE, /* 24 */
1.1 root 219: EXCP_LTLBL,
220: EXCP_TLBL,
221: EXCP_TLBS,
222: EXCP_DBE,
223: EXCP_DDBL,
224: EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
225: /* may change privilege level */
226: EXCP_BRANCH = 0x108, /* branch instruction */
227: EXCP_ERET = 0x10C, /* return from interrupt */
228: EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
229: EXCP_FLUSH = 0x109,
230: };
231:
232: int cpu_mips_exec(CPUMIPSState *s);
233: CPUMIPSState *cpu_mips_init(void);
234: uint32_t cpu_mips_get_clock (void);
235:
236: #endif /* !defined (__MIPS_CPU_H__) */
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