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1.1 root 1: #if !defined (__MIPS_CPU_H__)
2: #define __MIPS_CPU_H__
3:
1.1.1.2 root 4: #define TARGET_HAS_ICE 1
5:
1.1 root 6: #include "mips-defs.h"
7: #include "cpu-defs.h"
8: #include "config.h"
9: #include "softfloat.h"
10:
11: typedef union fpr_t fpr_t;
12: union fpr_t {
13: double d;
14: float f;
15: uint32_t u[2];
16: };
17:
18: #if defined(MIPS_USES_R4K_TLB)
19: typedef struct tlb_t tlb_t;
20: struct tlb_t {
21: target_ulong VPN;
22: target_ulong end;
1.1.1.2 root 23: target_ulong end2;
1.1.1.3 ! root 24: uint_fast8_t ASID;
! 25: uint_fast16_t G:1;
! 26: uint_fast16_t C0:3;
! 27: uint_fast16_t C1:3;
! 28: uint_fast16_t V0:1;
! 29: uint_fast16_t V1:1;
! 30: uint_fast16_t D0:1;
! 31: uint_fast16_t D1:1;
1.1 root 32: target_ulong PFN[2];
33: };
34: #endif
35:
36: typedef struct CPUMIPSState CPUMIPSState;
37: struct CPUMIPSState {
38: /* General integer registers */
39: target_ulong gpr[32];
40: /* Special registers */
41: target_ulong PC;
42: uint32_t HI, LO;
43: uint32_t DCR; /* ? */
44: #if defined(MIPS_USES_FPU)
45: /* Floating point registers */
46: fpr_t fpr[16];
47: /* Floating point special purpose registers */
48: uint32_t fcr0;
49: uint32_t fcr25;
50: uint32_t fcr26;
51: uint32_t fcr28;
52: uint32_t fcsr;
53: #endif
54: #if defined(MIPS_USES_R4K_TLB)
55: tlb_t tlb[16];
56: #endif
57: uint32_t CP0_index;
58: uint32_t CP0_random;
59: uint32_t CP0_EntryLo0;
60: uint32_t CP0_EntryLo1;
61: uint32_t CP0_Context;
62: uint32_t CP0_PageMask;
63: uint32_t CP0_Wired;
64: uint32_t CP0_BadVAddr;
65: uint32_t CP0_Count;
66: uint32_t CP0_EntryHi;
67: uint32_t CP0_Compare;
68: uint32_t CP0_Status;
69: #define CP0St_CU3 31
70: #define CP0St_CU2 30
71: #define CP0St_CU1 29
72: #define CP0St_CU0 28
73: #define CP0St_RP 27
74: #define CP0St_RE 25
75: #define CP0St_BEV 22
76: #define CP0St_TS 21
77: #define CP0St_SR 20
78: #define CP0St_NMI 19
79: #define CP0St_IM 8
80: #define CP0St_UM 4
81: #define CP0St_ERL 2
82: #define CP0St_EXL 1
83: #define CP0St_IE 0
84: uint32_t CP0_Cause;
85: #define CP0Ca_IV 23
86: uint32_t CP0_EPC;
87: uint32_t CP0_PRid;
88: uint32_t CP0_Config0;
89: #define CP0C0_M 31
90: #define CP0C0_K23 28
91: #define CP0C0_KU 25
92: #define CP0C0_MDU 20
93: #define CP0C0_MM 17
94: #define CP0C0_BM 16
95: #define CP0C0_BE 15
96: #define CP0C0_AT 13
97: #define CP0C0_AR 10
98: #define CP0C0_MT 7
99: #define CP0C0_K0 0
100: uint32_t CP0_Config1;
101: #define CP0C1_MMU 25
102: #define CP0C1_IS 22
103: #define CP0C1_IL 19
104: #define CP0C1_IA 16
105: #define CP0C1_DS 13
106: #define CP0C1_DL 10
107: #define CP0C1_DA 7
108: #define CP0C1_PC 4
109: #define CP0C1_WR 3
110: #define CP0C1_CA 2
111: #define CP0C1_EP 1
112: #define CP0C1_FP 0
113: uint32_t CP0_LLAddr;
114: uint32_t CP0_WatchLo;
115: uint32_t CP0_WatchHi;
116: uint32_t CP0_Debug;
117: #define CPDB_DBD 31
118: #define CP0DB_DM 30
119: #define CP0DB_LSNM 28
120: #define CP0DB_Doze 27
121: #define CP0DB_Halt 26
122: #define CP0DB_CNT 25
123: #define CP0DB_IBEP 24
124: #define CP0DB_DBEP 21
125: #define CP0DB_IEXI 20
126: #define CP0DB_VER 15
127: #define CP0DB_DEC 10
128: #define CP0DB_SSt 8
129: #define CP0DB_DINT 5
130: #define CP0DB_DIB 4
131: #define CP0DB_DDBS 3
132: #define CP0DB_DDBL 2
133: #define CP0DB_DBp 1
134: #define CP0DB_DSS 0
135: uint32_t CP0_DEPC;
136: uint32_t CP0_TagLo;
137: uint32_t CP0_DataLo;
138: uint32_t CP0_ErrorEPC;
139: uint32_t CP0_DESAVE;
140: /* Qemu */
141: #if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)
142: double ft0, ft1, ft2;
143: #endif
144: struct QEMUTimer *timer; /* Internal timer */
145: int interrupt_request;
146: jmp_buf jmp_env;
147: int exception_index;
148: int error_code;
149: int user_mode_only; /* user mode only simulation */
150: uint32_t hflags; /* CPU State */
151: /* TMASK defines different execution modes */
1.1.1.3 ! root 152: #define MIPS_HFLAG_TMASK 0x007F
1.1 root 153: #define MIPS_HFLAG_MODE 0x001F /* execution modes */
154: #define MIPS_HFLAG_UM 0x0001 /* user mode */
155: #define MIPS_HFLAG_ERL 0x0002 /* Error mode */
156: #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
157: #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
158: #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
159: #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
1.1.1.2 root 160: /* If translation is interrupted between the branch instruction and
161: * the delay slot, record what type of branch it is so that we can
162: * resume translation properly. It might be possible to reduce
163: * this from three bits to two. */
164: #define MIPS_HFLAG_BMASK 0x0380
165: #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
166: #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
167: #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
168: #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
1.1 root 169: target_ulong btarget; /* Jump / branch target */
170: int bcond; /* Branch condition (if needed) */
1.1.1.2 root 171:
172: int halted; /* TRUE if the CPU is in suspend state */
173:
174: CPU_COMMON
1.1 root 175: };
176:
177: #include "cpu-all.h"
178:
179: /* Memory access type :
180: * may be needed for precise access rights control and precise exceptions.
181: */
182: enum {
183: /* 1 bit to define user level / supervisor access */
184: ACCESS_USER = 0x00,
185: ACCESS_SUPER = 0x01,
186: /* 1 bit to indicate direction */
187: ACCESS_STORE = 0x02,
188: /* Type of instruction that generated the access */
189: ACCESS_CODE = 0x10, /* Code fetch access */
190: ACCESS_INT = 0x20, /* Integer load/store access */
191: ACCESS_FLOAT = 0x30, /* floating point load/store access */
192: };
193:
194: /* Exceptions */
195: enum {
196: EXCP_NONE = -1,
197: EXCP_RESET = 0,
198: EXCP_SRESET,
199: EXCP_DSS,
200: EXCP_DINT,
201: EXCP_NMI,
202: EXCP_MCHECK,
203: EXCP_EXT_INTERRUPT,
204: EXCP_DFWATCH,
205: EXCP_DIB, /* 8 */
206: EXCP_IWATCH,
207: EXCP_AdEL,
208: EXCP_AdES,
209: EXCP_TLBF,
210: EXCP_IBE,
211: EXCP_DBp,
212: EXCP_SYSCALL,
1.1.1.2 root 213: EXCP_BREAK, /* 16 */
214: EXCP_CpU,
1.1 root 215: EXCP_RI,
216: EXCP_OVERFLOW,
217: EXCP_TRAP,
218: EXCP_DDBS,
219: EXCP_DWATCH,
1.1.1.2 root 220: EXCP_LAE,
221: EXCP_SAE, /* 24 */
1.1 root 222: EXCP_LTLBL,
223: EXCP_TLBL,
224: EXCP_TLBS,
225: EXCP_DBE,
226: EXCP_DDBL,
227: EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
228: /* may change privilege level */
229: EXCP_BRANCH = 0x108, /* branch instruction */
230: EXCP_ERET = 0x10C, /* return from interrupt */
231: EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
232: EXCP_FLUSH = 0x109,
233: };
234:
235: int cpu_mips_exec(CPUMIPSState *s);
236: CPUMIPSState *cpu_mips_init(void);
237: uint32_t cpu_mips_get_clock (void);
238:
239: #endif /* !defined (__MIPS_CPU_H__) */
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