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1.1 root 1: #if !defined (__MIPS_CPU_H__)
2: #define __MIPS_CPU_H__
3:
1.1.1.2 root 4: #define TARGET_HAS_ICE 1
5:
1.1.1.4 ! root 6: #include "config.h"
1.1 root 7: #include "mips-defs.h"
8: #include "cpu-defs.h"
9: #include "softfloat.h"
10:
1.1.1.4 ! root 11: // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
! 12: // XXX: move that elsewhere
! 13: #if defined(HOST_SOLARIS) && SOLARISREV < 10
! 14: typedef unsigned char uint_fast8_t;
! 15: typedef unsigned int uint_fast16_t;
! 16: #endif
! 17:
1.1 root 18: typedef union fpr_t fpr_t;
19: union fpr_t {
1.1.1.4 ! root 20: float64 fd; /* ieee double precision */
! 21: float32 fs[2];/* ieee single precision */
! 22: uint64_t d; /* binary single fixed-point */
! 23: uint32_t w[2]; /* binary single fixed-point */
1.1 root 24: };
1.1.1.4 ! root 25: /* define FP_ENDIAN_IDX to access the same location
! 26: * in the fpr_t union regardless of the host endianess
! 27: */
! 28: #if defined(WORDS_BIGENDIAN)
! 29: # define FP_ENDIAN_IDX 1
! 30: #else
! 31: # define FP_ENDIAN_IDX 0
! 32: #endif
1.1 root 33:
34: #if defined(MIPS_USES_R4K_TLB)
35: typedef struct tlb_t tlb_t;
36: struct tlb_t {
37: target_ulong VPN;
38: target_ulong end;
1.1.1.2 root 39: target_ulong end2;
1.1.1.3 root 40: uint_fast8_t ASID;
41: uint_fast16_t G:1;
42: uint_fast16_t C0:3;
43: uint_fast16_t C1:3;
44: uint_fast16_t V0:1;
45: uint_fast16_t V1:1;
46: uint_fast16_t D0:1;
47: uint_fast16_t D1:1;
1.1 root 48: target_ulong PFN[2];
49: };
50: #endif
51:
52: typedef struct CPUMIPSState CPUMIPSState;
53: struct CPUMIPSState {
54: /* General integer registers */
55: target_ulong gpr[32];
56: /* Special registers */
57: target_ulong PC;
58: uint32_t HI, LO;
59: uint32_t DCR; /* ? */
60: #if defined(MIPS_USES_FPU)
61: /* Floating point registers */
62: fpr_t fpr[16];
1.1.1.4 ! root 63: #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
! 64: #define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
! 65: #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
! 66: #define FPR_D(cpu, n) (FPR(cpu, n)->d)
! 67: #define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX])
! 68:
! 69: #ifndef USE_HOST_FLOAT_REGS
! 70: fpr_t ft0;
! 71: fpr_t ft1;
! 72: fpr_t ft2;
! 73: #endif
! 74: float_status fp_status;
! 75: /* fpu implementation/revision register */
1.1 root 76: uint32_t fcr0;
1.1.1.4 ! root 77: /* fcsr */
! 78: uint32_t fcr31;
! 79: #define SET_FP_COND(reg) do { (reg) |= (1<<23); } while(0)
! 80: #define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0)
! 81: #define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0)
! 82: #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
! 83: #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
! 84: #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
! 85: #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0)
! 86: #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v) << 7); } while(0)
! 87: #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v) << 2); } while(0)
! 88: #define FP_INEXACT 1
! 89: #define FP_UNDERFLOW 2
! 90: #define FP_OVERFLOW 4
! 91: #define FP_DIV0 8
! 92: #define FP_INVALID 16
! 93: #define FP_UNIMPLEMENTED 32
! 94:
1.1 root 95: #endif
96: #if defined(MIPS_USES_R4K_TLB)
1.1.1.4 ! root 97: tlb_t tlb[MIPS_TLB_NB];
1.1 root 98: #endif
99: uint32_t CP0_index;
100: uint32_t CP0_random;
101: uint32_t CP0_EntryLo0;
102: uint32_t CP0_EntryLo1;
103: uint32_t CP0_Context;
104: uint32_t CP0_PageMask;
105: uint32_t CP0_Wired;
106: uint32_t CP0_BadVAddr;
107: uint32_t CP0_Count;
108: uint32_t CP0_EntryHi;
109: uint32_t CP0_Compare;
110: uint32_t CP0_Status;
111: #define CP0St_CU3 31
112: #define CP0St_CU2 30
113: #define CP0St_CU1 29
114: #define CP0St_CU0 28
115: #define CP0St_RP 27
1.1.1.4 ! root 116: #define CP0St_FR 26
1.1 root 117: #define CP0St_RE 25
118: #define CP0St_BEV 22
119: #define CP0St_TS 21
120: #define CP0St_SR 20
121: #define CP0St_NMI 19
122: #define CP0St_IM 8
123: #define CP0St_UM 4
124: #define CP0St_ERL 2
125: #define CP0St_EXL 1
126: #define CP0St_IE 0
127: uint32_t CP0_Cause;
128: #define CP0Ca_IV 23
129: uint32_t CP0_EPC;
130: uint32_t CP0_PRid;
131: uint32_t CP0_Config0;
132: #define CP0C0_M 31
133: #define CP0C0_K23 28
134: #define CP0C0_KU 25
135: #define CP0C0_MDU 20
136: #define CP0C0_MM 17
137: #define CP0C0_BM 16
138: #define CP0C0_BE 15
139: #define CP0C0_AT 13
140: #define CP0C0_AR 10
141: #define CP0C0_MT 7
142: #define CP0C0_K0 0
143: uint32_t CP0_Config1;
144: #define CP0C1_MMU 25
145: #define CP0C1_IS 22
146: #define CP0C1_IL 19
147: #define CP0C1_IA 16
148: #define CP0C1_DS 13
149: #define CP0C1_DL 10
150: #define CP0C1_DA 7
151: #define CP0C1_PC 4
152: #define CP0C1_WR 3
153: #define CP0C1_CA 2
154: #define CP0C1_EP 1
155: #define CP0C1_FP 0
156: uint32_t CP0_LLAddr;
157: uint32_t CP0_WatchLo;
158: uint32_t CP0_WatchHi;
159: uint32_t CP0_Debug;
160: #define CPDB_DBD 31
161: #define CP0DB_DM 30
162: #define CP0DB_LSNM 28
163: #define CP0DB_Doze 27
164: #define CP0DB_Halt 26
165: #define CP0DB_CNT 25
166: #define CP0DB_IBEP 24
167: #define CP0DB_DBEP 21
168: #define CP0DB_IEXI 20
169: #define CP0DB_VER 15
170: #define CP0DB_DEC 10
171: #define CP0DB_SSt 8
172: #define CP0DB_DINT 5
173: #define CP0DB_DIB 4
174: #define CP0DB_DDBS 3
175: #define CP0DB_DDBL 2
176: #define CP0DB_DBp 1
177: #define CP0DB_DSS 0
178: uint32_t CP0_DEPC;
179: uint32_t CP0_TagLo;
180: uint32_t CP0_DataLo;
181: uint32_t CP0_ErrorEPC;
182: uint32_t CP0_DESAVE;
183: /* Qemu */
184: struct QEMUTimer *timer; /* Internal timer */
185: int interrupt_request;
186: jmp_buf jmp_env;
187: int exception_index;
188: int error_code;
189: int user_mode_only; /* user mode only simulation */
190: uint32_t hflags; /* CPU State */
191: /* TMASK defines different execution modes */
1.1.1.3 root 192: #define MIPS_HFLAG_TMASK 0x007F
1.1 root 193: #define MIPS_HFLAG_MODE 0x001F /* execution modes */
194: #define MIPS_HFLAG_UM 0x0001 /* user mode */
195: #define MIPS_HFLAG_ERL 0x0002 /* Error mode */
196: #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
197: #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
198: #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
199: #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
1.1.1.2 root 200: /* If translation is interrupted between the branch instruction and
201: * the delay slot, record what type of branch it is so that we can
202: * resume translation properly. It might be possible to reduce
203: * this from three bits to two. */
204: #define MIPS_HFLAG_BMASK 0x0380
205: #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
206: #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
207: #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
208: #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
1.1 root 209: target_ulong btarget; /* Jump / branch target */
210: int bcond; /* Branch condition (if needed) */
1.1.1.2 root 211:
212: int halted; /* TRUE if the CPU is in suspend state */
213:
214: CPU_COMMON
1.1 root 215: };
216:
217: #include "cpu-all.h"
218:
219: /* Memory access type :
220: * may be needed for precise access rights control and precise exceptions.
221: */
222: enum {
223: /* 1 bit to define user level / supervisor access */
224: ACCESS_USER = 0x00,
225: ACCESS_SUPER = 0x01,
226: /* 1 bit to indicate direction */
227: ACCESS_STORE = 0x02,
228: /* Type of instruction that generated the access */
229: ACCESS_CODE = 0x10, /* Code fetch access */
230: ACCESS_INT = 0x20, /* Integer load/store access */
231: ACCESS_FLOAT = 0x30, /* floating point load/store access */
232: };
233:
234: /* Exceptions */
235: enum {
236: EXCP_NONE = -1,
237: EXCP_RESET = 0,
238: EXCP_SRESET,
239: EXCP_DSS,
240: EXCP_DINT,
241: EXCP_NMI,
242: EXCP_MCHECK,
243: EXCP_EXT_INTERRUPT,
244: EXCP_DFWATCH,
245: EXCP_DIB, /* 8 */
246: EXCP_IWATCH,
247: EXCP_AdEL,
248: EXCP_AdES,
249: EXCP_TLBF,
250: EXCP_IBE,
251: EXCP_DBp,
252: EXCP_SYSCALL,
1.1.1.2 root 253: EXCP_BREAK, /* 16 */
254: EXCP_CpU,
1.1 root 255: EXCP_RI,
256: EXCP_OVERFLOW,
257: EXCP_TRAP,
258: EXCP_DDBS,
259: EXCP_DWATCH,
1.1.1.2 root 260: EXCP_LAE,
261: EXCP_SAE, /* 24 */
1.1 root 262: EXCP_LTLBL,
263: EXCP_TLBL,
264: EXCP_TLBS,
265: EXCP_DBE,
266: EXCP_DDBL,
267: EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
268: /* may change privilege level */
269: EXCP_BRANCH = 0x108, /* branch instruction */
270: EXCP_ERET = 0x10C, /* return from interrupt */
271: EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
272: EXCP_FLUSH = 0x109,
273: };
274:
275: int cpu_mips_exec(CPUMIPSState *s);
276: CPUMIPSState *cpu_mips_init(void);
277: uint32_t cpu_mips_get_clock (void);
278:
279: #endif /* !defined (__MIPS_CPU_H__) */
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