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Annotation of qemu/target-mips/exec.h, revision 1.1.1.11

1.1       root        1: #if !defined(__QEMU_MIPS_EXEC_H__)
                      2: #define __QEMU_MIPS_EXEC_H__
                      3: 
1.1.1.2   root        4: //#define DEBUG_OP
1.1       root        5: 
1.1.1.5   root        6: #include "config.h"
1.1       root        7: #include "mips-defs.h"
                      8: #include "dyngen-exec.h"
1.1.1.6   root        9: #include "cpu-defs.h"
1.1       root       10: 
                     11: register struct CPUMIPSState *env asm(AREG0);
                     12: 
                     13: #include "cpu.h"
                     14: 
                     15: #if !defined(CONFIG_USER_ONLY)
1.1.1.2   root       16: #include "softmmu_exec.h"
1.1       root       17: #endif /* !defined(CONFIG_USER_ONLY) */
                     18: 
1.1.1.7   root       19: static inline void compute_hflags(CPUState *env)
1.1.1.6   root       20: {
                     21:     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
1.1.1.7   root       22:                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
                     23:                      MIPS_HFLAG_UX);
1.1.1.6   root       24:     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
                     25:         !(env->CP0_Status & (1 << CP0St_ERL)) &&
                     26:         !(env->hflags & MIPS_HFLAG_DM)) {
                     27:         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
                     28:     }
                     29: #if defined(TARGET_MIPS64)
                     30:     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
                     31:         (env->CP0_Status & (1 << CP0St_PX)) ||
                     32:         (env->CP0_Status & (1 << CP0St_UX)))
                     33:         env->hflags |= MIPS_HFLAG_64;
1.1.1.7   root       34:     if (env->CP0_Status & (1 << CP0St_UX))
                     35:         env->hflags |= MIPS_HFLAG_UX;
1.1.1.6   root       36: #endif
                     37:     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
                     38:         !(env->hflags & MIPS_HFLAG_KSU))
                     39:         env->hflags |= MIPS_HFLAG_CP0;
                     40:     if (env->CP0_Status & (1 << CP0St_CU1))
                     41:         env->hflags |= MIPS_HFLAG_FPU;
                     42:     if (env->CP0_Status & (1 << CP0St_FR))
                     43:         env->hflags |= MIPS_HFLAG_F64;
                     44:     if (env->insn_flags & ISA_MIPS32R2) {
1.1.1.7   root       45:         if (env->active_fpu.fcr0 & (1 << FCR0_F64))
1.1.1.6   root       46:             env->hflags |= MIPS_HFLAG_COP1X;
                     47:     } else if (env->insn_flags & ISA_MIPS32) {
                     48:         if (env->hflags & MIPS_HFLAG_64)
                     49:             env->hflags |= MIPS_HFLAG_COP1X;
                     50:     } else if (env->insn_flags & ISA_MIPS4) {
                     51:         /* All supported MIPS IV CPUs use the XX (CU3) to enable
                     52:            and disable the MIPS IV extensions to the MIPS III ISA.
                     53:            Some other MIPS IV CPUs ignore the bit, so the check here
                     54:            would be too restrictive for them.  */
                     55:         if (env->CP0_Status & (1 << CP0St_CU3))
                     56:             env->hflags |= MIPS_HFLAG_COP1X;
                     57:     }
                     58: }
                     59: 
1.1       root       60: #endif /* !defined(__QEMU_MIPS_EXEC_H__) */

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