Annotation of qemu/target-mips/exec.h, revision 1.1.1.8

1.1       root        1: #if !defined(__QEMU_MIPS_EXEC_H__)
                      2: #define __QEMU_MIPS_EXEC_H__
                      3: 
1.1.1.2   root        4: //#define DEBUG_OP
1.1       root        5: 
1.1.1.5   root        6: #include "config.h"
1.1       root        7: #include "mips-defs.h"
                      8: #include "dyngen-exec.h"
1.1.1.6   root        9: #include "cpu-defs.h"
1.1       root       10: 
                     11: register struct CPUMIPSState *env asm(AREG0);
                     12: 
                     13: #include "cpu.h"
                     14: #include "exec-all.h"
                     15: 
                     16: #if !defined(CONFIG_USER_ONLY)
1.1.1.2   root       17: #include "softmmu_exec.h"
1.1       root       18: #endif /* !defined(CONFIG_USER_ONLY) */
                     19: 
1.1.1.4   root       20: void dump_fpu(CPUState *env);
1.1.1.6   root       21: void fpu_dump_state(CPUState *env, FILE *f,
1.1.1.4   root       22:                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
                     23:                     int flags);
1.1       root       24: 
                     25: void cpu_mips_clock_init (CPUState *env);
1.1.1.5   root       26: void cpu_mips_tlb_flush (CPUState *env, int flush_global);
1.1       root       27: 
1.1.1.7   root       28: static inline void env_to_regs(void)
1.1.1.6   root       29: {
                     30: }
                     31: 
1.1.1.7   root       32: static inline void regs_to_env(void)
1.1.1.6   root       33: {
                     34: }
                     35: 
1.1.1.8 ! root       36: static inline int cpu_has_work(CPUState *env)
        !            37: {
        !            38:     return (env->interrupt_request &
        !            39:             (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER));
        !            40: }
        !            41: 
        !            42: 
1.1.1.7   root       43: static inline int cpu_halted(CPUState *env)
1.1.1.6   root       44: {
                     45:     if (!env->halted)
                     46:         return 0;
1.1.1.8 ! root       47:     if (cpu_has_work(env)) {
1.1.1.6   root       48:         env->halted = 0;
                     49:         return 0;
                     50:     }
                     51:     return EXCP_HALTED;
                     52: }
                     53: 
1.1.1.7   root       54: static inline void compute_hflags(CPUState *env)
1.1.1.6   root       55: {
                     56:     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
1.1.1.7   root       57:                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
                     58:                      MIPS_HFLAG_UX);
1.1.1.6   root       59:     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
                     60:         !(env->CP0_Status & (1 << CP0St_ERL)) &&
                     61:         !(env->hflags & MIPS_HFLAG_DM)) {
                     62:         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
                     63:     }
                     64: #if defined(TARGET_MIPS64)
                     65:     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
                     66:         (env->CP0_Status & (1 << CP0St_PX)) ||
                     67:         (env->CP0_Status & (1 << CP0St_UX)))
                     68:         env->hflags |= MIPS_HFLAG_64;
1.1.1.7   root       69:     if (env->CP0_Status & (1 << CP0St_UX))
                     70:         env->hflags |= MIPS_HFLAG_UX;
1.1.1.6   root       71: #endif
                     72:     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
                     73:         !(env->hflags & MIPS_HFLAG_KSU))
                     74:         env->hflags |= MIPS_HFLAG_CP0;
                     75:     if (env->CP0_Status & (1 << CP0St_CU1))
                     76:         env->hflags |= MIPS_HFLAG_FPU;
                     77:     if (env->CP0_Status & (1 << CP0St_FR))
                     78:         env->hflags |= MIPS_HFLAG_F64;
                     79:     if (env->insn_flags & ISA_MIPS32R2) {
1.1.1.7   root       80:         if (env->active_fpu.fcr0 & (1 << FCR0_F64))
1.1.1.6   root       81:             env->hflags |= MIPS_HFLAG_COP1X;
                     82:     } else if (env->insn_flags & ISA_MIPS32) {
                     83:         if (env->hflags & MIPS_HFLAG_64)
                     84:             env->hflags |= MIPS_HFLAG_COP1X;
                     85:     } else if (env->insn_flags & ISA_MIPS4) {
                     86:         /* All supported MIPS IV CPUs use the XX (CU3) to enable
                     87:            and disable the MIPS IV extensions to the MIPS III ISA.
                     88:            Some other MIPS IV CPUs ignore the bit, so the check here
                     89:            would be too restrictive for them.  */
                     90:         if (env->CP0_Status & (1 << CP0St_CU3))
                     91:             env->hflags |= MIPS_HFLAG_COP1X;
                     92:     }
                     93: }
                     94: 
1.1       root       95: #endif /* !defined(__QEMU_MIPS_EXEC_H__) */

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