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Annotation of qemu/target-mips/exec.h, revision 1.1.1.9

1.1       root        1: #if !defined(__QEMU_MIPS_EXEC_H__)
                      2: #define __QEMU_MIPS_EXEC_H__
                      3: 
1.1.1.2   root        4: //#define DEBUG_OP
1.1       root        5: 
1.1.1.5   root        6: #include "config.h"
1.1       root        7: #include "mips-defs.h"
                      8: #include "dyngen-exec.h"
1.1.1.6   root        9: #include "cpu-defs.h"
1.1       root       10: 
                     11: register struct CPUMIPSState *env asm(AREG0);
                     12: 
                     13: #include "cpu.h"
                     14: #include "exec-all.h"
                     15: 
                     16: #if !defined(CONFIG_USER_ONLY)
1.1.1.2   root       17: #include "softmmu_exec.h"
1.1       root       18: #endif /* !defined(CONFIG_USER_ONLY) */
                     19: 
1.1.1.8   root       20: static inline int cpu_has_work(CPUState *env)
                     21: {
                     22:     return (env->interrupt_request &
                     23:             (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER));
                     24: }
                     25: 
                     26: 
1.1.1.7   root       27: static inline int cpu_halted(CPUState *env)
1.1.1.6   root       28: {
                     29:     if (!env->halted)
                     30:         return 0;
1.1.1.8   root       31:     if (cpu_has_work(env)) {
1.1.1.6   root       32:         env->halted = 0;
                     33:         return 0;
                     34:     }
                     35:     return EXCP_HALTED;
                     36: }
                     37: 
1.1.1.7   root       38: static inline void compute_hflags(CPUState *env)
1.1.1.6   root       39: {
                     40:     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
1.1.1.7   root       41:                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
                     42:                      MIPS_HFLAG_UX);
1.1.1.6   root       43:     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
                     44:         !(env->CP0_Status & (1 << CP0St_ERL)) &&
                     45:         !(env->hflags & MIPS_HFLAG_DM)) {
                     46:         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
                     47:     }
                     48: #if defined(TARGET_MIPS64)
                     49:     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
                     50:         (env->CP0_Status & (1 << CP0St_PX)) ||
                     51:         (env->CP0_Status & (1 << CP0St_UX)))
                     52:         env->hflags |= MIPS_HFLAG_64;
1.1.1.7   root       53:     if (env->CP0_Status & (1 << CP0St_UX))
                     54:         env->hflags |= MIPS_HFLAG_UX;
1.1.1.6   root       55: #endif
                     56:     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
                     57:         !(env->hflags & MIPS_HFLAG_KSU))
                     58:         env->hflags |= MIPS_HFLAG_CP0;
                     59:     if (env->CP0_Status & (1 << CP0St_CU1))
                     60:         env->hflags |= MIPS_HFLAG_FPU;
                     61:     if (env->CP0_Status & (1 << CP0St_FR))
                     62:         env->hflags |= MIPS_HFLAG_F64;
                     63:     if (env->insn_flags & ISA_MIPS32R2) {
1.1.1.7   root       64:         if (env->active_fpu.fcr0 & (1 << FCR0_F64))
1.1.1.6   root       65:             env->hflags |= MIPS_HFLAG_COP1X;
                     66:     } else if (env->insn_flags & ISA_MIPS32) {
                     67:         if (env->hflags & MIPS_HFLAG_64)
                     68:             env->hflags |= MIPS_HFLAG_COP1X;
                     69:     } else if (env->insn_flags & ISA_MIPS4) {
                     70:         /* All supported MIPS IV CPUs use the XX (CU3) to enable
                     71:            and disable the MIPS IV extensions to the MIPS III ISA.
                     72:            Some other MIPS IV CPUs ignore the bit, so the check here
                     73:            would be too restrictive for them.  */
                     74:         if (env->CP0_Status & (1 << CP0St_CU3))
                     75:             env->hflags |= MIPS_HFLAG_COP1X;
                     76:     }
                     77: }
                     78: 
1.1.1.9 ! root       79: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
        !            80: {
        !            81:     env->active_tc.PC = tb->pc;
        !            82:     env->hflags &= ~MIPS_HFLAG_BMASK;
        !            83:     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
        !            84: }
        !            85: 
1.1       root       86: #endif /* !defined(__QEMU_MIPS_EXEC_H__) */

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