File:  [Qemu by Fabrice Bellard] / qemu / target-mips / exec.h
Revision 1.1.1.7 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 16:55:02 2018 UTC (3 years, 3 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0105, qemu0104, qemu0103, qemu0102, qemu0101, qemu0100, HEAD
qemu 0.10.0

    1: #if !defined(__QEMU_MIPS_EXEC_H__)
    2: #define __QEMU_MIPS_EXEC_H__
    3: 
    4: //#define DEBUG_OP
    5: 
    6: #include "config.h"
    7: #include "mips-defs.h"
    8: #include "dyngen-exec.h"
    9: #include "cpu-defs.h"
   10: 
   11: register struct CPUMIPSState *env asm(AREG0);
   12: 
   13: #include "cpu.h"
   14: #include "exec-all.h"
   15: 
   16: #if !defined(CONFIG_USER_ONLY)
   17: #include "softmmu_exec.h"
   18: #endif /* !defined(CONFIG_USER_ONLY) */
   19: 
   20: void do_mtc0_status_debug(uint32_t old, uint32_t val);
   21: void do_mtc0_status_irqraise_debug(void);
   22: void dump_fpu(CPUState *env);
   23: void fpu_dump_state(CPUState *env, FILE *f,
   24:                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
   25:                     int flags);
   26: 
   27: void cpu_mips_clock_init (CPUState *env);
   28: void cpu_mips_tlb_flush (CPUState *env, int flush_global);
   29: 
   30: static inline void env_to_regs(void)
   31: {
   32: }
   33: 
   34: static inline void regs_to_env(void)
   35: {
   36: }
   37: 
   38: static inline int cpu_halted(CPUState *env)
   39: {
   40:     if (!env->halted)
   41:         return 0;
   42:     if (env->interrupt_request &
   43:         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
   44:         env->halted = 0;
   45:         return 0;
   46:     }
   47:     return EXCP_HALTED;
   48: }
   49: 
   50: static inline void compute_hflags(CPUState *env)
   51: {
   52:     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
   53:                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
   54:                      MIPS_HFLAG_UX);
   55:     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
   56:         !(env->CP0_Status & (1 << CP0St_ERL)) &&
   57:         !(env->hflags & MIPS_HFLAG_DM)) {
   58:         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
   59:     }
   60: #if defined(TARGET_MIPS64)
   61:     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
   62:         (env->CP0_Status & (1 << CP0St_PX)) ||
   63:         (env->CP0_Status & (1 << CP0St_UX)))
   64:         env->hflags |= MIPS_HFLAG_64;
   65:     if (env->CP0_Status & (1 << CP0St_UX))
   66:         env->hflags |= MIPS_HFLAG_UX;
   67: #endif
   68:     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
   69:         !(env->hflags & MIPS_HFLAG_KSU))
   70:         env->hflags |= MIPS_HFLAG_CP0;
   71:     if (env->CP0_Status & (1 << CP0St_CU1))
   72:         env->hflags |= MIPS_HFLAG_FPU;
   73:     if (env->CP0_Status & (1 << CP0St_FR))
   74:         env->hflags |= MIPS_HFLAG_F64;
   75:     if (env->insn_flags & ISA_MIPS32R2) {
   76:         if (env->active_fpu.fcr0 & (1 << FCR0_F64))
   77:             env->hflags |= MIPS_HFLAG_COP1X;
   78:     } else if (env->insn_flags & ISA_MIPS32) {
   79:         if (env->hflags & MIPS_HFLAG_64)
   80:             env->hflags |= MIPS_HFLAG_COP1X;
   81:     } else if (env->insn_flags & ISA_MIPS4) {
   82:         /* All supported MIPS IV CPUs use the XX (CU3) to enable
   83:            and disable the MIPS IV extensions to the MIPS III ISA.
   84:            Some other MIPS IV CPUs ignore the bit, so the check here
   85:            would be too restrictive for them.  */
   86:         if (env->CP0_Status & (1 << CP0St_CU3))
   87:             env->hflags |= MIPS_HFLAG_COP1X;
   88:     }
   89: }
   90: 
   91: #endif /* !defined(__QEMU_MIPS_EXEC_H__) */

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