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1.1 root 1: /* 1.1.1.3 ! root 2: * MIPS emulation micro-operations templates for floating point reg 1.1 root 3: * load & store for qemu. 1.1.1.3 ! root 4: * 1.1 root 5: * Copyright (c) 2006 Marius Groeger 6: * 7: * This library is free software; you can redistribute it and/or 8: * modify it under the terms of the GNU Lesser General Public 9: * License as published by the Free Software Foundation; either 10: * version 2 of the License, or (at your option) any later version. 11: * 12: * This library is distributed in the hope that it will be useful, 13: * but WITHOUT ANY WARRANTY; without even the implied warranty of 14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15: * Lesser General Public License for more details. 16: * 17: * You should have received a copy of the GNU Lesser General Public 18: * License along with this library; if not, write to the Free Software 19: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20: */ 21: 1.1.1.3 ! root 22: #if defined(FREG) 1.1 root 23: 1.1.1.3 ! root 24: #define OP_WLOAD_FREG(treg, tregname, FREG) \ ! 25: void glue(glue(op_load_fpr_,tregname), FREG) (void) \ ! 26: { \ ! 27: treg = env->fpu->fpr[FREG].w[FP_ENDIAN_IDX]; \ ! 28: FORCE_RET(); \ 1.1 root 29: } 30: 1.1.1.3 ! root 31: #define OP_WSTORE_FREG(treg, tregname, FREG) \ ! 32: void glue(glue(op_store_fpr_,tregname), FREG) (void) \ ! 33: { \ ! 34: env->fpu->fpr[FREG].w[FP_ENDIAN_IDX] = treg; \ ! 35: FORCE_RET(); \ 1.1 root 36: } 37: 1.1.1.3 ! root 38: /* WT0 = FREG.w: op_load_fpr_WT0_fprFREG */ ! 39: OP_WLOAD_FREG(WT0, WT0_fpr, FREG) ! 40: /* FREG.w = WT0: op_store_fpr_WT0_fprFREG */ ! 41: OP_WSTORE_FREG(WT0, WT0_fpr, FREG) ! 42: ! 43: OP_WLOAD_FREG(WT1, WT1_fpr, FREG) ! 44: OP_WSTORE_FREG(WT1, WT1_fpr, FREG) ! 45: ! 46: OP_WLOAD_FREG(WT2, WT2_fpr, FREG) ! 47: OP_WSTORE_FREG(WT2, WT2_fpr, FREG) ! 48: ! 49: #define OP_DLOAD_FREG(treg, tregname, FREG) \ ! 50: void glue(glue(op_load_fpr_,tregname), FREG) (void) \ ! 51: { \ ! 52: if (env->hflags & MIPS_HFLAG_F64) \ ! 53: treg = env->fpu->fpr[FREG].d; \ ! 54: else \ ! 55: treg = (uint64_t)(env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX]) << 32 | \ ! 56: env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX]; \ ! 57: FORCE_RET(); \ ! 58: } 1.1 root 59: 1.1.1.3 ! root 60: #define OP_DSTORE_FREG(treg, tregname, FREG) \ ! 61: void glue(glue(op_store_fpr_,tregname), FREG) (void) \ ! 62: { \ ! 63: if (env->hflags & MIPS_HFLAG_F64) \ ! 64: env->fpu->fpr[FREG].d = treg; \ ! 65: else { \ ! 66: env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX] = treg >> 32; \ ! 67: env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX] = treg; \ ! 68: } \ ! 69: FORCE_RET(); \ ! 70: } 1.1 root 71: 1.1.1.3 ! root 72: OP_DLOAD_FREG(DT0, DT0_fpr, FREG) ! 73: OP_DSTORE_FREG(DT0, DT0_fpr, FREG) 1.1 root 74: 1.1.1.3 ! root 75: OP_DLOAD_FREG(DT1, DT1_fpr, FREG) ! 76: OP_DSTORE_FREG(DT1, DT1_fpr, FREG) 1.1 root 77: 1.1.1.3 ! root 78: OP_DLOAD_FREG(DT2, DT2_fpr, FREG) ! 79: OP_DSTORE_FREG(DT2, DT2_fpr, FREG) 1.1 root 80: 1.1.1.3 ! root 81: #define OP_PSLOAD_FREG(treg, tregname, FREG) \ ! 82: void glue(glue(op_load_fpr_,tregname), FREG) (void) \ ! 83: { \ ! 84: treg = env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX]; \ ! 85: FORCE_RET(); \ 1.1 root 86: } 87: 1.1.1.3 ! root 88: #define OP_PSSTORE_FREG(treg, tregname, FREG) \ ! 89: void glue(glue(op_store_fpr_,tregname), FREG) (void) \ ! 90: { \ ! 91: env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX] = treg; \ ! 92: FORCE_RET(); \ 1.1 root 93: } 94: 1.1.1.3 ! root 95: OP_PSLOAD_FREG(WTH0, WTH0_fpr, FREG) ! 96: OP_PSSTORE_FREG(WTH0, WTH0_fpr, FREG) 1.1 root 97: 1.1.1.3 ! root 98: OP_PSLOAD_FREG(WTH1, WTH1_fpr, FREG) ! 99: OP_PSSTORE_FREG(WTH1, WTH1_fpr, FREG) 1.1 root 100: 1.1.1.3 ! root 101: OP_PSLOAD_FREG(WTH2, WTH2_fpr, FREG) ! 102: OP_PSSTORE_FREG(WTH2, WTH2_fpr, FREG) 1.1 root 103: 104: #endif 105: 106: #if defined (FTN) 107: 1.1.1.3 ! root 108: #define SET_RESET(treg, tregname) \ 1.1 root 109: void glue(op_set, tregname)(void) \ 1.1.1.3 ! root 110: { \ ! 111: treg = PARAM1; \ ! 112: FORCE_RET(); \ ! 113: } \ 1.1 root 114: void glue(op_reset, tregname)(void) \ 1.1.1.3 ! root 115: { \ ! 116: treg = 0; \ ! 117: FORCE_RET(); \ ! 118: } 1.1 root 119: 120: SET_RESET(WT0, _WT0) 121: SET_RESET(WT1, _WT1) 122: SET_RESET(WT2, _WT2) 123: SET_RESET(DT0, _DT0) 124: SET_RESET(DT1, _DT1) 125: SET_RESET(DT2, _DT2) 1.1.1.3 ! root 126: SET_RESET(WTH0, _WTH0) ! 127: SET_RESET(WTH1, _WTH1) ! 128: SET_RESET(WTH2, _WTH2) 1.1 root 129: 1.1.1.2 root 130: #undef SET_RESET 1.1 root 131: #endif
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