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1.1 root 1: /*
2: * MIPS emulation helpers for qemu.
1.1.1.6 root 3: *
1.1 root 4: * Copyright (c) 2004-2005 Jocelyn Mayer
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.8 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #include <stdarg.h>
20: #include <stdlib.h>
21: #include <stdio.h>
22: #include <string.h>
23: #include <inttypes.h>
24: #include <signal.h>
25:
26: #include "cpu.h"
27:
1.1.1.4 root 28: enum {
29: TLBRET_DIRTY = -4,
30: TLBRET_INVALID = -3,
31: TLBRET_NOMATCH = -2,
32: TLBRET_BADADDR = -1,
33: TLBRET_MATCH = 0
34: };
35:
1.1.1.11 root 36: #if !defined(CONFIG_USER_ONLY)
37:
1.1.1.6 root 38: /* no MMU emulation */
1.1.1.9 root 39: int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
1.1 root 40: target_ulong address, int rw, int access_type)
41: {
1.1.1.6 root 42: *physical = address;
43: *prot = PAGE_READ | PAGE_WRITE;
44: return TLBRET_MATCH;
45: }
46:
47: /* fixed mapping MMU emulation */
1.1.1.9 root 48: int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
1.1.1.6 root 49: target_ulong address, int rw, int access_type)
50: {
51: if (address <= (int32_t)0x7FFFFFFFUL) {
52: if (!(env->CP0_Status & (1 << CP0St_ERL)))
53: *physical = address + 0x40000000UL;
54: else
55: *physical = address;
56: } else if (address <= (int32_t)0xBFFFFFFFUL)
57: *physical = address & 0x1FFFFFFF;
58: else
59: *physical = address;
60:
61: *prot = PAGE_READ | PAGE_WRITE;
62: return TLBRET_MATCH;
63: }
64:
65: /* MIPS32/MIPS64 R4000-style MMU emulation */
1.1.1.9 root 66: int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
1.1.1.6 root 67: target_ulong address, int rw, int access_type)
68: {
69: uint8_t ASID = env->CP0_EntryHi & 0xFF;
1.1.1.5 root 70: int i;
71:
1.1.1.6 root 72: for (i = 0; i < env->tlb->tlb_in_use; i++) {
73: r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
1.1.1.5 root 74: /* 1k pages are not supported. */
1.1.1.6 root 75: target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1.1.1.5 root 76: target_ulong tag = address & ~mask;
1.1.1.6 root 77: target_ulong VPN = tlb->VPN & ~mask;
78: #if defined(TARGET_MIPS64)
79: tag &= env->SEGMask;
80: #endif
1.1 root 81:
82: /* Check ASID, virtual page number & size */
1.1.1.6 root 83: if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1.1 root 84: /* TLB match */
1.1.1.6 root 85: int n = !!(address & mask & ~(mask >> 1));
1.1 root 86: /* Check access rights */
1.1.1.6 root 87: if (!(n ? tlb->V1 : tlb->V0))
1.1.1.4 root 88: return TLBRET_INVALID;
1.1.1.6 root 89: if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
1.1.1.5 root 90: *physical = tlb->PFN[n] | (address & (mask >> 1));
1.1 root 91: *prot = PAGE_READ;
1.1.1.3 root 92: if (n ? tlb->D1 : tlb->D0)
1.1 root 93: *prot |= PAGE_WRITE;
1.1.1.4 root 94: return TLBRET_MATCH;
1.1 root 95: }
1.1.1.4 root 96: return TLBRET_DIRTY;
1.1 root 97: }
98: }
1.1.1.4 root 99: return TLBRET_NOMATCH;
1.1 root 100: }
101:
1.1.1.9 root 102: static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
1.1.1.4 root 103: int *prot, target_ulong address,
104: int rw, int access_type)
1.1 root 105: {
1.1.1.6 root 106: /* User mode can only access useg/xuseg */
1.1.1.4 root 107: int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
1.1.1.6 root 108: int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
109: int kernel_mode = !user_mode && !supervisor_mode;
110: #if defined(TARGET_MIPS64)
111: int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
112: int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
113: int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
114: #endif
1.1.1.4 root 115: int ret = TLBRET_MATCH;
116:
1.1 root 117: #if 0
1.1.1.7 root 118: qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
1.1 root 119: #endif
1.1.1.6 root 120:
121: if (address <= (int32_t)0x7FFFFFFFUL) {
122: /* useg */
123: if (env->CP0_Status & (1 << CP0St_ERL)) {
124: *physical = address & 0xFFFFFFFF;
1.1 root 125: *prot = PAGE_READ | PAGE_WRITE;
126: } else {
1.1.1.6 root 127: ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
1.1 root 128: }
1.1.1.6 root 129: #if defined(TARGET_MIPS64)
130: } else if (address < 0x4000000000000000ULL) {
131: /* xuseg */
1.1.1.7 root 132: if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
1.1.1.6 root 133: ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
1.1.1.7 root 134: } else {
135: ret = TLBRET_BADADDR;
1.1.1.6 root 136: }
137: } else if (address < 0x8000000000000000ULL) {
138: /* xsseg */
1.1.1.7 root 139: if ((supervisor_mode || kernel_mode) &&
140: SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
1.1.1.6 root 141: ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
1.1.1.7 root 142: } else {
143: ret = TLBRET_BADADDR;
1.1.1.6 root 144: }
145: } else if (address < 0xC000000000000000ULL) {
146: /* xkphys */
147: if (kernel_mode && KX &&
148: (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
149: *physical = address & env->PAMask;
150: *prot = PAGE_READ | PAGE_WRITE;
1.1.1.7 root 151: } else {
152: ret = TLBRET_BADADDR;
153: }
1.1.1.6 root 154: } else if (address < 0xFFFFFFFF80000000ULL) {
155: /* xkseg */
1.1.1.7 root 156: if (kernel_mode && KX &&
157: address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
1.1.1.6 root 158: ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
1.1.1.7 root 159: } else {
160: ret = TLBRET_BADADDR;
161: }
1.1.1.6 root 162: #endif
1.1.1.5 root 163: } else if (address < (int32_t)0xA0000000UL) {
1.1 root 164: /* kseg0 */
1.1.1.6 root 165: if (kernel_mode) {
166: *physical = address - (int32_t)0x80000000UL;
167: *prot = PAGE_READ | PAGE_WRITE;
168: } else {
169: ret = TLBRET_BADADDR;
170: }
1.1.1.5 root 171: } else if (address < (int32_t)0xC0000000UL) {
1.1 root 172: /* kseg1 */
1.1.1.6 root 173: if (kernel_mode) {
174: *physical = address - (int32_t)0xA0000000UL;
175: *prot = PAGE_READ | PAGE_WRITE;
176: } else {
177: ret = TLBRET_BADADDR;
178: }
1.1.1.5 root 179: } else if (address < (int32_t)0xE0000000UL) {
1.1.1.6 root 180: /* sseg (kseg2) */
181: if (supervisor_mode || kernel_mode) {
182: ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
183: } else {
184: ret = TLBRET_BADADDR;
185: }
1.1 root 186: } else {
187: /* kseg3 */
188: /* XXX: debug segment is not emulated */
1.1.1.6 root 189: if (kernel_mode) {
190: ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
191: } else {
192: ret = TLBRET_BADADDR;
193: }
1.1 root 194: }
195: #if 0
1.1.1.7 root 196: qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
197: address, rw, access_type, *physical, *prot, ret);
1.1 root 198: #endif
199:
200: return ret;
201: }
1.1.1.7 root 202: #endif
1.1 root 203:
1.1.1.9 root 204: static void raise_mmu_exception(CPUState *env, target_ulong address,
205: int rw, int tlb_error)
206: {
207: int exception = 0, error_code = 0;
208:
209: switch (tlb_error) {
210: default:
211: case TLBRET_BADADDR:
212: /* Reference to kernel address from user mode or supervisor mode */
213: /* Reference to supervisor address from user mode */
214: if (rw)
215: exception = EXCP_AdES;
216: else
217: exception = EXCP_AdEL;
218: break;
219: case TLBRET_NOMATCH:
220: /* No TLB match for a mapped address */
221: if (rw)
222: exception = EXCP_TLBS;
223: else
224: exception = EXCP_TLBL;
225: error_code = 1;
226: break;
227: case TLBRET_INVALID:
228: /* TLB match with no valid bit */
229: if (rw)
230: exception = EXCP_TLBS;
231: else
232: exception = EXCP_TLBL;
233: break;
234: case TLBRET_DIRTY:
235: /* TLB match but 'D' bit is cleared */
236: exception = EXCP_LTLBL;
237: break;
238:
239: }
240: /* Raise exception */
241: env->CP0_BadVAddr = address;
242: env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
243: ((address >> 9) & 0x007ffff0);
244: env->CP0_EntryHi =
245: (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
246: #if defined(TARGET_MIPS64)
247: env->CP0_EntryHi &= env->SEGMask;
248: env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
249: ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
250: ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
251: #endif
252: env->exception_index = exception;
253: env->error_code = error_code;
254: }
255:
1.1.1.11 root 256: #if !defined(CONFIG_USER_ONLY)
1.1.1.6 root 257: target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1.1 root 258: {
1.1.1.9 root 259: target_phys_addr_t phys_addr;
1.1 root 260: int prot;
261:
262: if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
263: return -1;
264: return phys_addr;
265: }
1.1.1.11 root 266: #endif
1.1 root 267:
268: int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1.1.1.14! root 269: int mmu_idx)
1.1 root 270: {
1.1.1.7 root 271: #if !defined(CONFIG_USER_ONLY)
1.1.1.9 root 272: target_phys_addr_t physical;
1.1 root 273: int prot;
274: int access_type;
1.1.1.13 root 275: #endif
1.1 root 276: int ret = 0;
277:
1.1.1.2 root 278: #if 0
1.1.1.7 root 279: log_cpu_state(env, 0);
1.1.1.2 root 280: #endif
1.1.1.14! root 281: qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n",
! 282: __func__, env->active_tc.PC, address, rw, mmu_idx);
1.1.1.2 root 283:
284: rw &= 1;
285:
1.1 root 286: /* data access */
1.1.1.13 root 287: #if !defined(CONFIG_USER_ONLY)
1.1 root 288: /* XXX: put correct access by using cpu_restore_state()
289: correctly */
290: access_type = ACCESS_INT;
291: ret = get_physical_address(env, &physical, &prot,
292: address, rw, access_type);
1.1.1.9 root 293: qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n",
1.1.1.7 root 294: __func__, address, ret, physical, prot);
1.1.1.4 root 295: if (ret == TLBRET_MATCH) {
1.1.1.13 root 296: tlb_set_page(env, address & TARGET_PAGE_MASK,
297: physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
298: mmu_idx, TARGET_PAGE_SIZE);
299: ret = 0;
1.1.1.7 root 300: } else if (ret < 0)
301: #endif
302: {
1.1.1.9 root 303: raise_mmu_exception(env, address, rw, ret);
1.1 root 304: ret = 1;
305: }
306:
307: return ret;
308: }
309:
1.1.1.9 root 310: #if !defined(CONFIG_USER_ONLY)
1.1.1.10 root 311: target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
1.1.1.9 root 312: {
313: target_phys_addr_t physical;
314: int prot;
315: int access_type;
316: int ret = 0;
317:
318: rw &= 1;
319:
320: /* data access */
321: access_type = ACCESS_INT;
322: ret = get_physical_address(env, &physical, &prot,
323: address, rw, access_type);
324: if (ret != TLBRET_MATCH) {
325: raise_mmu_exception(env, address, rw, ret);
1.1.1.10 root 326: return -1LL;
327: } else {
328: return physical;
1.1.1.9 root 329: }
330: }
331: #endif
332:
1.1.1.6 root 333: static const char * const excp_names[EXCP_LAST + 1] = {
334: [EXCP_RESET] = "reset",
335: [EXCP_SRESET] = "soft reset",
336: [EXCP_DSS] = "debug single step",
337: [EXCP_DINT] = "debug interrupt",
338: [EXCP_NMI] = "non-maskable interrupt",
339: [EXCP_MCHECK] = "machine check",
340: [EXCP_EXT_INTERRUPT] = "interrupt",
341: [EXCP_DFWATCH] = "deferred watchpoint",
342: [EXCP_DIB] = "debug instruction breakpoint",
343: [EXCP_IWATCH] = "instruction fetch watchpoint",
344: [EXCP_AdEL] = "address error load",
345: [EXCP_AdES] = "address error store",
346: [EXCP_TLBF] = "TLB refill",
347: [EXCP_IBE] = "instruction bus error",
348: [EXCP_DBp] = "debug breakpoint",
349: [EXCP_SYSCALL] = "syscall",
350: [EXCP_BREAK] = "break",
351: [EXCP_CpU] = "coprocessor unusable",
352: [EXCP_RI] = "reserved instruction",
353: [EXCP_OVERFLOW] = "arithmetic overflow",
354: [EXCP_TRAP] = "trap",
355: [EXCP_FPE] = "floating point",
356: [EXCP_DDBS] = "debug data break store",
357: [EXCP_DWATCH] = "data watchpoint",
358: [EXCP_LTLBL] = "TLB modify",
359: [EXCP_TLBL] = "TLB load",
360: [EXCP_TLBS] = "TLB store",
361: [EXCP_DBE] = "data bus error",
362: [EXCP_DDBL] = "debug data break load",
363: [EXCP_THREAD] = "thread",
364: [EXCP_MDMX] = "MDMX",
365: [EXCP_C2E] = "precise coprocessor 2",
366: [EXCP_CACHE] = "cache error",
367: };
368:
1.1.1.11 root 369: #if !defined(CONFIG_USER_ONLY)
370: static target_ulong exception_resume_pc (CPUState *env)
371: {
372: target_ulong bad_pc;
373: target_ulong isa_mode;
374:
375: isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
376: bad_pc = env->active_tc.PC | isa_mode;
377: if (env->hflags & MIPS_HFLAG_BMASK) {
378: /* If the exception was raised from a delay slot, come back to
379: the jump. */
380: bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
381: }
382:
383: return bad_pc;
384: }
385:
386: static void set_hflags_for_handler (CPUState *env)
387: {
388: /* Exception handlers are entered in 32-bit mode. */
389: env->hflags &= ~(MIPS_HFLAG_M16);
390: /* ...except that microMIPS lets you choose. */
391: if (env->insn_flags & ASE_MICROMIPS) {
392: env->hflags |= (!!(env->CP0_Config3
393: & (1 << CP0C3_ISA_ON_EXC))
394: << MIPS_HFLAG_M16_SHIFT);
395: }
396: }
397: #endif
398:
1.1 root 399: void do_interrupt (CPUState *env)
400: {
1.1.1.6 root 401: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 402: target_ulong offset;
1.1 root 403: int cause = -1;
1.1.1.6 root 404: const char *name;
1.1 root 405:
1.1.1.7 root 406: if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
1.1.1.6 root 407: if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
408: name = "unknown";
409: else
410: name = excp_names[env->exception_index];
411:
1.1.1.7 root 412: qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
413: __func__, env->active_tc.PC, env->CP0_EPC, name);
1.1 root 414: }
415: if (env->exception_index == EXCP_EXT_INTERRUPT &&
416: (env->hflags & MIPS_HFLAG_DM))
417: env->exception_index = EXCP_DINT;
418: offset = 0x180;
419: switch (env->exception_index) {
420: case EXCP_DSS:
421: env->CP0_Debug |= 1 << CP0DB_DSS;
422: /* Debug single step cannot be raised inside a delay slot and
1.1.1.7 root 423: resume will always occur on the next instruction
424: (but we assume the pc has always been updated during
425: code translation). */
1.1.1.11 root 426: env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
1.1 root 427: goto enter_debug_mode;
428: case EXCP_DINT:
429: env->CP0_Debug |= 1 << CP0DB_DINT;
430: goto set_DEPC;
431: case EXCP_DIB:
432: env->CP0_Debug |= 1 << CP0DB_DIB;
433: goto set_DEPC;
434: case EXCP_DBp:
435: env->CP0_Debug |= 1 << CP0DB_DBp;
436: goto set_DEPC;
437: case EXCP_DDBS:
438: env->CP0_Debug |= 1 << CP0DB_DDBS;
439: goto set_DEPC;
440: case EXCP_DDBL:
441: env->CP0_Debug |= 1 << CP0DB_DDBL;
442: set_DEPC:
1.1.1.11 root 443: env->CP0_DEPC = exception_resume_pc(env);
444: env->hflags &= ~MIPS_HFLAG_BMASK;
1.1.1.7 root 445: enter_debug_mode:
1.1.1.6 root 446: env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
447: env->hflags &= ~(MIPS_HFLAG_KSU);
1.1 root 448: /* EJTAG probe trap enable is not implemented... */
1.1.1.6 root 449: if (!(env->CP0_Status & (1 << CP0St_EXL)))
450: env->CP0_Cause &= ~(1 << CP0Ca_BD);
1.1.1.7 root 451: env->active_tc.PC = (int32_t)0xBFC00480;
1.1.1.11 root 452: set_hflags_for_handler(env);
1.1 root 453: break;
454: case EXCP_RESET:
1.1.1.5 root 455: cpu_reset(env);
456: break;
1.1 root 457: case EXCP_SRESET:
1.1.1.6 root 458: env->CP0_Status |= (1 << CP0St_SR);
459: memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
1.1 root 460: goto set_error_EPC;
461: case EXCP_NMI:
1.1.1.6 root 462: env->CP0_Status |= (1 << CP0St_NMI);
1.1.1.7 root 463: set_error_EPC:
1.1.1.11 root 464: env->CP0_ErrorEPC = exception_resume_pc(env);
465: env->hflags &= ~MIPS_HFLAG_BMASK;
1.1.1.6 root 466: env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
467: env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
468: env->hflags &= ~(MIPS_HFLAG_KSU);
469: if (!(env->CP0_Status & (1 << CP0St_EXL)))
470: env->CP0_Cause &= ~(1 << CP0Ca_BD);
1.1.1.7 root 471: env->active_tc.PC = (int32_t)0xBFC00000;
1.1.1.11 root 472: set_hflags_for_handler(env);
1.1 root 473: break;
474: case EXCP_EXT_INTERRUPT:
475: cause = 0;
476: if (env->CP0_Cause & (1 << CP0Ca_IV))
477: offset = 0x200;
1.1.1.12 root 478:
479: if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
480: /* Vectored Interrupts. */
481: unsigned int spacing;
482: unsigned int vector;
483: unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
484:
1.1.1.14! root 485: pending &= env->CP0_Status >> 8;
1.1.1.12 root 486: /* Compute the Vector Spacing. */
487: spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
488: spacing <<= 5;
489:
490: if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
491: /* For VInt mode, the MIPS computes the vector internally. */
1.1.1.14! root 492: for (vector = 7; vector > 0; vector--) {
! 493: if (pending & (1 << vector)) {
1.1.1.12 root 494: /* Found it. */
495: break;
496: }
497: }
498: } else {
499: /* For VEIC mode, the external interrupt controller feeds the
500: vector throught the CP0Cause IP lines. */
501: vector = pending;
502: }
503: offset = 0x200 + vector * spacing;
504: }
1.1 root 505: goto set_EPC;
1.1.1.6 root 506: case EXCP_LTLBL:
507: cause = 1;
508: goto set_EPC;
509: case EXCP_TLBL:
510: cause = 2;
511: if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
512: #if defined(TARGET_MIPS64)
513: int R = env->CP0_BadVAddr >> 62;
514: int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
515: int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
516: int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
517:
1.1.1.11 root 518: if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
519: (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
1.1.1.6 root 520: offset = 0x080;
521: else
522: #endif
523: offset = 0x000;
524: }
525: goto set_EPC;
526: case EXCP_TLBS:
527: cause = 3;
528: if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
529: #if defined(TARGET_MIPS64)
530: int R = env->CP0_BadVAddr >> 62;
531: int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
532: int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
533: int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
534:
1.1.1.11 root 535: if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
536: (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
1.1.1.6 root 537: offset = 0x080;
538: else
539: #endif
540: offset = 0x000;
541: }
1.1 root 542: goto set_EPC;
543: case EXCP_AdEL:
544: cause = 4;
545: goto set_EPC;
1.1.1.6 root 546: case EXCP_AdES:
547: cause = 5;
1.1 root 548: goto set_EPC;
549: case EXCP_IBE:
550: cause = 6;
551: goto set_EPC;
552: case EXCP_DBE:
553: cause = 7;
554: goto set_EPC;
555: case EXCP_SYSCALL:
556: cause = 8;
557: goto set_EPC;
558: case EXCP_BREAK:
559: cause = 9;
560: goto set_EPC;
561: case EXCP_RI:
562: cause = 10;
563: goto set_EPC;
564: case EXCP_CpU:
565: cause = 11;
1.1.1.6 root 566: env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
567: (env->error_code << CP0Ca_CE);
1.1 root 568: goto set_EPC;
569: case EXCP_OVERFLOW:
570: cause = 12;
571: goto set_EPC;
572: case EXCP_TRAP:
573: cause = 13;
574: goto set_EPC;
1.1.1.6 root 575: case EXCP_FPE:
576: cause = 15;
1.1 root 577: goto set_EPC;
1.1.1.6 root 578: case EXCP_C2E:
579: cause = 18;
1.1 root 580: goto set_EPC;
1.1.1.6 root 581: case EXCP_MDMX:
582: cause = 22;
583: goto set_EPC;
584: case EXCP_DWATCH:
585: cause = 23;
586: /* XXX: TODO: manage defered watch exceptions */
587: goto set_EPC;
588: case EXCP_MCHECK:
589: cause = 24;
590: goto set_EPC;
591: case EXCP_THREAD:
592: cause = 25;
593: goto set_EPC;
594: case EXCP_CACHE:
595: cause = 30;
596: if (env->CP0_Status & (1 << CP0St_BEV)) {
597: offset = 0x100;
1.1 root 598: } else {
1.1.1.6 root 599: offset = 0x20000100;
600: }
1.1.1.7 root 601: set_EPC:
1.1.1.6 root 602: if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1.1.1.11 root 603: env->CP0_EPC = exception_resume_pc(env);
1.1.1.6 root 604: if (env->hflags & MIPS_HFLAG_BMASK) {
605: env->CP0_Cause |= (1 << CP0Ca_BD);
606: } else {
607: env->CP0_Cause &= ~(1 << CP0Ca_BD);
608: }
609: env->CP0_Status |= (1 << CP0St_EXL);
610: env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
611: env->hflags &= ~(MIPS_HFLAG_KSU);
1.1 root 612: }
1.1.1.6 root 613: env->hflags &= ~MIPS_HFLAG_BMASK;
1.1.1.5 root 614: if (env->CP0_Status & (1 << CP0St_BEV)) {
1.1.1.7 root 615: env->active_tc.PC = (int32_t)0xBFC00200;
1.1.1.5 root 616: } else {
1.1.1.7 root 617: env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
1.1.1.5 root 618: }
1.1.1.7 root 619: env->active_tc.PC += offset;
1.1.1.11 root 620: set_hflags_for_handler(env);
1.1.1.6 root 621: env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
1.1 root 622: break;
623: default:
1.1.1.7 root 624: qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
1.1 root 625: printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
626: exit(1);
627: }
1.1.1.7 root 628: if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
629: qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
1.1.1.6 root 630: " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
1.1.1.7 root 631: __func__, env->active_tc.PC, env->CP0_EPC, cause,
1.1 root 632: env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
633: env->CP0_DEPC);
634: }
1.1.1.7 root 635: #endif
1.1 root 636: env->exception_index = EXCP_NONE;
637: }
1.1.1.5 root 638:
1.1.1.11 root 639: #if !defined(CONFIG_USER_ONLY)
1.1.1.6 root 640: void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
1.1.1.5 root 641: {
1.1.1.6 root 642: r4k_tlb_t *tlb;
1.1.1.5 root 643: target_ulong addr;
644: target_ulong end;
645: uint8_t ASID = env->CP0_EntryHi & 0xFF;
646: target_ulong mask;
647:
1.1.1.6 root 648: tlb = &env->tlb->mmu.r4k.tlb[idx];
649: /* The qemu TLB is flushed when the ASID changes, so no need to
1.1.1.5 root 650: flush these entries again. */
651: if (tlb->G == 0 && tlb->ASID != ASID) {
652: return;
653: }
654:
1.1.1.6 root 655: if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
1.1.1.5 root 656: /* For tlbwr, we can shadow the discarded entry into
1.1.1.7 root 657: a new (fake) TLB entry, as long as the guest can not
658: tell that it's there. */
1.1.1.6 root 659: env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
660: env->tlb->tlb_in_use++;
1.1.1.5 root 661: return;
662: }
663:
664: /* 1k pages are not supported. */
1.1.1.6 root 665: mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1.1.1.5 root 666: if (tlb->V0) {
1.1.1.6 root 667: addr = tlb->VPN & ~mask;
668: #if defined(TARGET_MIPS64)
669: if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
670: addr |= 0x3FFFFF0000000000ULL;
671: }
672: #endif
1.1.1.5 root 673: end = addr | (mask >> 1);
674: while (addr < end) {
675: tlb_flush_page (env, addr);
676: addr += TARGET_PAGE_SIZE;
677: }
678: }
679: if (tlb->V1) {
1.1.1.6 root 680: addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
681: #if defined(TARGET_MIPS64)
682: if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
683: addr |= 0x3FFFFF0000000000ULL;
684: }
685: #endif
1.1.1.5 root 686: end = addr | mask;
1.1.1.7 root 687: while (addr - 1 < end) {
1.1.1.5 root 688: tlb_flush_page (env, addr);
689: addr += TARGET_PAGE_SIZE;
690: }
691: }
692: }
1.1.1.11 root 693: #endif
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