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1.1 root 1: /*
2: * MIPS emulation helpers for qemu.
3: *
4: * Copyright (c) 2004-2005 Jocelyn Mayer
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #include <stdarg.h>
21: #include <stdlib.h>
22: #include <stdio.h>
23: #include <string.h>
24: #include <inttypes.h>
25: #include <signal.h>
26: #include <assert.h>
27:
28: #include "cpu.h"
29: #include "exec-all.h"
30:
31: /* MIPS32 4K MMU emulation */
32: #ifdef MIPS_USES_R4K_TLB
33: static int map_address (CPUState *env, target_ulong *physical, int *prot,
34: target_ulong address, int rw, int access_type)
35: {
36: tlb_t *tlb;
37: target_ulong tag;
38: uint8_t ASID;
39: int i, n;
40: int ret;
41:
42: ret = -2;
43: tag = (address & 0xFFFFE000);
44: ASID = env->CP0_EntryHi & 0x000000FF;
45: for (i = 0; i < MIPS_TLB_NB; i++) {
46: tlb = &env->tlb[i];
47: /* Check ASID, virtual page number & size */
48: if ((tlb->G == 1 || tlb->ASID == ASID) &&
1.1.1.2 ! root 49: tlb->VPN == tag && address < tlb->end2) {
1.1 root 50: /* TLB match */
51: n = (address >> 12) & 1;
52: /* Check access rights */
53: if ((tlb->V[n] & 2) && (rw == 0 || (tlb->D[n] & 4))) {
54: *physical = tlb->PFN[n] | (address & 0xFFF);
55: *prot = PAGE_READ;
56: if (tlb->D[n])
57: *prot |= PAGE_WRITE;
58: return 0;
59: } else if (!(tlb->V[n] & 2)) {
60: return -3;
61: } else {
62: return -4;
63: }
64: }
65: }
66:
67: return ret;
68: }
69: #endif
70:
71: int get_physical_address (CPUState *env, target_ulong *physical, int *prot,
72: target_ulong address, int rw, int access_type)
73: {
74: int user_mode;
75: int ret;
76:
77: /* User mode can only access useg */
78: user_mode = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) ? 1 : 0;
79: #if 0
80: if (logfile) {
81: fprintf(logfile, "user mode %d h %08x\n",
82: user_mode, env->hflags);
83: }
84: #endif
85: if (user_mode && address > 0x7FFFFFFFUL)
86: return -1;
87: ret = 0;
88: if (address < 0x80000000UL) {
89: if (!(env->hflags & MIPS_HFLAG_ERL)) {
90: #ifdef MIPS_USES_R4K_TLB
91: ret = map_address(env, physical, prot, address, rw, access_type);
92: #else
93: *physical = address + 0x40000000UL;
94: *prot = PAGE_READ | PAGE_WRITE;
95: #endif
96: } else {
97: *physical = address;
98: *prot = PAGE_READ | PAGE_WRITE;
99: }
100: } else if (address < 0xA0000000UL) {
101: /* kseg0 */
102: /* XXX: check supervisor mode */
103: *physical = address - 0x80000000UL;
104: *prot = PAGE_READ | PAGE_WRITE;
105: } else if (address < 0xC0000000UL) {
106: /* kseg1 */
107: /* XXX: check supervisor mode */
108: *physical = address - 0xA0000000UL;
109: *prot = PAGE_READ | PAGE_WRITE;
110: } else if (address < 0xE0000000UL) {
111: /* kseg2 */
112: #ifdef MIPS_USES_R4K_TLB
113: ret = map_address(env, physical, prot, address, rw, access_type);
114: #else
115: *physical = address;
116: *prot = PAGE_READ | PAGE_WRITE;
117: #endif
118: } else {
119: /* kseg3 */
120: /* XXX: check supervisor mode */
121: /* XXX: debug segment is not emulated */
122: #ifdef MIPS_USES_R4K_TLB
123: ret = map_address(env, physical, prot, address, rw, access_type);
124: #else
125: *physical = address;
126: *prot = PAGE_READ | PAGE_WRITE;
127: #endif
128: }
129: #if 0
130: if (logfile) {
131: fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
132: access_type, *physical, *prot, ret);
133: }
134: #endif
135:
136: return ret;
137: }
138:
139: #if defined(CONFIG_USER_ONLY)
140: target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
141: {
142: return addr;
143: }
144: #else
145: target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
146: {
147: target_ulong phys_addr;
148: int prot;
149:
150: if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
151: return -1;
152: return phys_addr;
153: }
154:
155: void cpu_mips_init_mmu (CPUState *env)
156: {
157: }
158: #endif /* !defined(CONFIG_USER_ONLY) */
159:
160: int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
161: int is_user, int is_softmmu)
162: {
163: target_ulong physical;
164: int prot;
165: int exception = 0, error_code = 0;
166: int access_type;
167: int ret = 0;
168:
169: if (logfile) {
1.1.1.2 ! root 170: #if 0
1.1 root 171: cpu_dump_state(env, logfile, fprintf, 0);
1.1.1.2 ! root 172: #endif
1.1 root 173: fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
174: __func__, env->PC, address, rw, is_user, is_softmmu);
175: }
1.1.1.2 ! root 176:
! 177: rw &= 1;
! 178:
1.1 root 179: /* data access */
180: /* XXX: put correct access by using cpu_restore_state()
181: correctly */
182: access_type = ACCESS_INT;
183: if (env->user_mode_only) {
184: /* user mode only emulation */
185: ret = -2;
186: goto do_fault;
187: }
188: ret = get_physical_address(env, &physical, &prot,
189: address, rw, access_type);
190: if (logfile) {
191: fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
192: __func__, address, ret, physical, prot);
193: }
194: if (ret == 0) {
195: ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot,
196: is_user, is_softmmu);
197: } else if (ret < 0) {
198: do_fault:
199: switch (ret) {
200: default:
201: case -1:
202: /* Reference to kernel address from user mode or supervisor mode */
203: /* Reference to supervisor address from user mode */
204: if (rw)
205: exception = EXCP_AdES;
206: else
207: exception = EXCP_AdEL;
208: break;
209: case -2:
210: /* No TLB match for a mapped address */
211: if (rw)
212: exception = EXCP_TLBS;
213: else
214: exception = EXCP_TLBL;
215: error_code = 1;
216: break;
217: case -3:
218: /* TLB match with no valid bit */
219: if (rw)
220: exception = EXCP_TLBS;
221: else
222: exception = EXCP_TLBL;
223: error_code = 0;
224: break;
225: case -4:
226: /* TLB match but 'D' bit is cleared */
227: exception = EXCP_LTLBL;
228: break;
229:
230: }
231: /* Raise exception */
232: env->CP0_BadVAddr = address;
233: env->CP0_Context = (env->CP0_Context & 0xff800000) |
1.1.1.2 ! root 234: ((address >> 9) & 0x007ffff0);
1.1 root 235: env->CP0_EntryHi =
236: (env->CP0_EntryHi & 0x000000FF) | (address & 0xFFFFF000);
237: env->exception_index = exception;
238: env->error_code = error_code;
239: ret = 1;
240: }
241:
242: return ret;
243: }
244:
245: void do_interrupt (CPUState *env)
246: {
247: target_ulong pc, offset;
248: int cause = -1;
249:
250: if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
251: fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
252: __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
253: }
254: if (env->exception_index == EXCP_EXT_INTERRUPT &&
255: (env->hflags & MIPS_HFLAG_DM))
256: env->exception_index = EXCP_DINT;
257: offset = 0x180;
258: switch (env->exception_index) {
259: case EXCP_DSS:
260: env->CP0_Debug |= 1 << CP0DB_DSS;
261: /* Debug single step cannot be raised inside a delay slot and
262: * resume will always occur on the next instruction
263: * (but we assume the pc has always been updated during
264: * code translation).
265: */
266: env->CP0_DEPC = env->PC;
267: goto enter_debug_mode;
268: case EXCP_DINT:
269: env->CP0_Debug |= 1 << CP0DB_DINT;
270: goto set_DEPC;
271: case EXCP_DIB:
272: env->CP0_Debug |= 1 << CP0DB_DIB;
273: goto set_DEPC;
274: case EXCP_DBp:
275: env->CP0_Debug |= 1 << CP0DB_DBp;
276: goto set_DEPC;
277: case EXCP_DDBS:
278: env->CP0_Debug |= 1 << CP0DB_DDBS;
279: goto set_DEPC;
280: case EXCP_DDBL:
281: env->CP0_Debug |= 1 << CP0DB_DDBL;
282: goto set_DEPC;
283: set_DEPC:
1.1.1.2 ! root 284: if (env->hflags & MIPS_HFLAG_BMASK) {
1.1 root 285: /* If the exception was raised from a delay slot,
286: * come back to the jump
287: */
288: env->CP0_DEPC = env->PC - 4;
1.1.1.2 ! root 289: env->hflags &= ~MIPS_HFLAG_BMASK;
1.1 root 290: } else {
291: env->CP0_DEPC = env->PC;
292: }
293: enter_debug_mode:
294: env->hflags |= MIPS_HFLAG_DM;
295: /* EJTAG probe trap enable is not implemented... */
296: pc = 0xBFC00480;
297: break;
298: case EXCP_RESET:
299: #ifdef MIPS_USES_R4K_TLB
300: env->CP0_random = MIPS_TLB_NB - 1;
301: #endif
302: env->CP0_Wired = 0;
303: env->CP0_Config0 = MIPS_CONFIG0;
304: #if defined (MIPS_CONFIG1)
305: env->CP0_Config1 = MIPS_CONFIG1;
306: #endif
307: #if defined (MIPS_CONFIG2)
308: env->CP0_Config2 = MIPS_CONFIG2;
309: #endif
310: #if defined (MIPS_CONFIG3)
311: env->CP0_Config3 = MIPS_CONFIG3;
312: #endif
313: env->CP0_WatchLo = 0;
314: env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
315: goto set_error_EPC;
316: case EXCP_SRESET:
317: env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
318: (1 << CP0St_SR);
319: env->CP0_WatchLo = 0;
320: goto set_error_EPC;
321: case EXCP_NMI:
322: env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
323: (1 << CP0St_NMI);
324: set_error_EPC:
1.1.1.2 ! root 325: if (env->hflags & MIPS_HFLAG_BMASK) {
1.1 root 326: /* If the exception was raised from a delay slot,
327: * come back to the jump
328: */
329: env->CP0_ErrorEPC = env->PC - 4;
330: } else {
331: env->CP0_ErrorEPC = env->PC;
332: }
1.1.1.2 ! root 333: env->hflags = MIPS_HFLAG_ERL;
1.1 root 334: pc = 0xBFC00000;
335: break;
336: case EXCP_MCHECK:
337: cause = 24;
338: goto set_EPC;
339: case EXCP_EXT_INTERRUPT:
340: cause = 0;
341: if (env->CP0_Cause & (1 << CP0Ca_IV))
342: offset = 0x200;
343: goto set_EPC;
344: case EXCP_DWATCH:
345: cause = 23;
346: /* XXX: TODO: manage defered watch exceptions */
347: goto set_EPC;
348: case EXCP_AdEL:
349: case EXCP_AdES:
350: cause = 4;
351: goto set_EPC;
352: case EXCP_TLBL:
353: case EXCP_TLBF:
354: cause = 2;
355: if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
356: offset = 0x000;
357: goto set_EPC;
358: case EXCP_IBE:
359: cause = 6;
360: goto set_EPC;
361: case EXCP_DBE:
362: cause = 7;
363: goto set_EPC;
364: case EXCP_SYSCALL:
365: cause = 8;
366: goto set_EPC;
367: case EXCP_BREAK:
368: cause = 9;
369: goto set_EPC;
370: case EXCP_RI:
371: cause = 10;
372: goto set_EPC;
373: case EXCP_CpU:
374: cause = 11;
1.1.1.2 ! root 375: env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
1.1 root 376: goto set_EPC;
377: case EXCP_OVERFLOW:
378: cause = 12;
379: goto set_EPC;
380: case EXCP_TRAP:
381: cause = 13;
382: goto set_EPC;
383: case EXCP_LTLBL:
384: cause = 1;
385: goto set_EPC;
386: case EXCP_TLBS:
387: cause = 3;
388: if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
389: offset = 0x000;
390: goto set_EPC;
391: set_EPC:
392: if (env->CP0_Status & (1 << CP0St_BEV)) {
393: pc = 0xBFC00200;
394: } else {
395: pc = 0x80000000;
396: }
397: env->hflags |= MIPS_HFLAG_EXL;
398: pc += offset;
399: env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
1.1.1.2 ! root 400: if (env->hflags & MIPS_HFLAG_BMASK) {
1.1 root 401: /* If the exception was raised from a delay slot,
402: * come back to the jump
403: */
404: env->CP0_EPC = env->PC - 4;
405: env->CP0_Cause |= 0x80000000;
1.1.1.2 ! root 406: env->hflags &= ~MIPS_HFLAG_BMASK;
1.1 root 407: } else {
408: env->CP0_EPC = env->PC;
409: env->CP0_Cause &= ~0x80000000;
410: }
411: break;
412: default:
413: if (logfile) {
414: fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
415: env->exception_index);
416: }
417: printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
418: exit(1);
419: }
420: env->PC = pc;
421: if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
422: fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
423: " S %08x C %08x A %08x D %08x\n",
424: __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
425: env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
426: env->CP0_DEPC);
427: }
428: env->exception_index = EXCP_NONE;
429: }
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