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1.1 root 1: /*
2: * MIPS emulation helpers for qemu.
3: *
4: * Copyright (c) 2004-2005 Jocelyn Mayer
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #include <stdarg.h>
21: #include <stdlib.h>
22: #include <stdio.h>
23: #include <string.h>
24: #include <inttypes.h>
25: #include <signal.h>
26: #include <assert.h>
27:
28: #include "cpu.h"
29: #include "exec-all.h"
30:
31: /* MIPS32 4K MMU emulation */
32: #ifdef MIPS_USES_R4K_TLB
33: static int map_address (CPUState *env, target_ulong *physical, int *prot,
34: target_ulong address, int rw, int access_type)
35: {
36: tlb_t *tlb;
37: target_ulong tag;
38: uint8_t ASID;
39: int i, n;
40: int ret;
41:
42: ret = -2;
43: tag = (address & 0xFFFFE000);
44: ASID = env->CP0_EntryHi & 0x000000FF;
45: for (i = 0; i < MIPS_TLB_NB; i++) {
46: tlb = &env->tlb[i];
47: /* Check ASID, virtual page number & size */
48: if ((tlb->G == 1 || tlb->ASID == ASID) &&
1.1.1.2 root 49: tlb->VPN == tag && address < tlb->end2) {
1.1 root 50: /* TLB match */
51: n = (address >> 12) & 1;
52: /* Check access rights */
1.1.1.3 ! root 53: if (!(n ? tlb->V1 : tlb->V0))
! 54: return -3;
! 55: if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
1.1 root 56: *physical = tlb->PFN[n] | (address & 0xFFF);
57: *prot = PAGE_READ;
1.1.1.3 ! root 58: if (n ? tlb->D1 : tlb->D0)
1.1 root 59: *prot |= PAGE_WRITE;
60: return 0;
61: }
1.1.1.3 ! root 62: return -4;
1.1 root 63: }
64: }
65:
66: return ret;
67: }
68: #endif
69:
70: int get_physical_address (CPUState *env, target_ulong *physical, int *prot,
71: target_ulong address, int rw, int access_type)
72: {
73: int user_mode;
74: int ret;
75:
76: /* User mode can only access useg */
77: user_mode = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) ? 1 : 0;
78: #if 0
79: if (logfile) {
80: fprintf(logfile, "user mode %d h %08x\n",
81: user_mode, env->hflags);
82: }
83: #endif
84: if (user_mode && address > 0x7FFFFFFFUL)
85: return -1;
86: ret = 0;
87: if (address < 0x80000000UL) {
88: if (!(env->hflags & MIPS_HFLAG_ERL)) {
89: #ifdef MIPS_USES_R4K_TLB
90: ret = map_address(env, physical, prot, address, rw, access_type);
91: #else
92: *physical = address + 0x40000000UL;
93: *prot = PAGE_READ | PAGE_WRITE;
94: #endif
95: } else {
96: *physical = address;
97: *prot = PAGE_READ | PAGE_WRITE;
98: }
99: } else if (address < 0xA0000000UL) {
100: /* kseg0 */
101: /* XXX: check supervisor mode */
102: *physical = address - 0x80000000UL;
103: *prot = PAGE_READ | PAGE_WRITE;
104: } else if (address < 0xC0000000UL) {
105: /* kseg1 */
106: /* XXX: check supervisor mode */
107: *physical = address - 0xA0000000UL;
108: *prot = PAGE_READ | PAGE_WRITE;
109: } else if (address < 0xE0000000UL) {
110: /* kseg2 */
111: #ifdef MIPS_USES_R4K_TLB
112: ret = map_address(env, physical, prot, address, rw, access_type);
113: #else
114: *physical = address;
115: *prot = PAGE_READ | PAGE_WRITE;
116: #endif
117: } else {
118: /* kseg3 */
119: /* XXX: check supervisor mode */
120: /* XXX: debug segment is not emulated */
121: #ifdef MIPS_USES_R4K_TLB
122: ret = map_address(env, physical, prot, address, rw, access_type);
123: #else
124: *physical = address;
125: *prot = PAGE_READ | PAGE_WRITE;
126: #endif
127: }
128: #if 0
129: if (logfile) {
130: fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
131: access_type, *physical, *prot, ret);
132: }
133: #endif
134:
135: return ret;
136: }
137:
138: #if defined(CONFIG_USER_ONLY)
139: target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
140: {
141: return addr;
142: }
143: #else
144: target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
145: {
146: target_ulong phys_addr;
147: int prot;
148:
149: if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
150: return -1;
151: return phys_addr;
152: }
153:
154: void cpu_mips_init_mmu (CPUState *env)
155: {
156: }
157: #endif /* !defined(CONFIG_USER_ONLY) */
158:
159: int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
160: int is_user, int is_softmmu)
161: {
162: target_ulong physical;
163: int prot;
164: int exception = 0, error_code = 0;
165: int access_type;
166: int ret = 0;
167:
168: if (logfile) {
1.1.1.2 root 169: #if 0
1.1 root 170: cpu_dump_state(env, logfile, fprintf, 0);
1.1.1.2 root 171: #endif
1.1 root 172: fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
173: __func__, env->PC, address, rw, is_user, is_softmmu);
174: }
1.1.1.2 root 175:
176: rw &= 1;
177:
1.1 root 178: /* data access */
179: /* XXX: put correct access by using cpu_restore_state()
180: correctly */
181: access_type = ACCESS_INT;
182: if (env->user_mode_only) {
183: /* user mode only emulation */
184: ret = -2;
185: goto do_fault;
186: }
187: ret = get_physical_address(env, &physical, &prot,
188: address, rw, access_type);
189: if (logfile) {
190: fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
191: __func__, address, ret, physical, prot);
192: }
193: if (ret == 0) {
194: ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot,
195: is_user, is_softmmu);
196: } else if (ret < 0) {
197: do_fault:
198: switch (ret) {
199: default:
200: case -1:
201: /* Reference to kernel address from user mode or supervisor mode */
202: /* Reference to supervisor address from user mode */
203: if (rw)
204: exception = EXCP_AdES;
205: else
206: exception = EXCP_AdEL;
207: break;
208: case -2:
209: /* No TLB match for a mapped address */
210: if (rw)
211: exception = EXCP_TLBS;
212: else
213: exception = EXCP_TLBL;
214: error_code = 1;
215: break;
216: case -3:
217: /* TLB match with no valid bit */
218: if (rw)
219: exception = EXCP_TLBS;
220: else
221: exception = EXCP_TLBL;
222: error_code = 0;
223: break;
224: case -4:
225: /* TLB match but 'D' bit is cleared */
226: exception = EXCP_LTLBL;
227: break;
228:
229: }
230: /* Raise exception */
231: env->CP0_BadVAddr = address;
232: env->CP0_Context = (env->CP0_Context & 0xff800000) |
1.1.1.2 root 233: ((address >> 9) & 0x007ffff0);
1.1 root 234: env->CP0_EntryHi =
235: (env->CP0_EntryHi & 0x000000FF) | (address & 0xFFFFF000);
236: env->exception_index = exception;
237: env->error_code = error_code;
238: ret = 1;
239: }
240:
241: return ret;
242: }
243:
244: void do_interrupt (CPUState *env)
245: {
246: target_ulong pc, offset;
247: int cause = -1;
248:
249: if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
250: fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
251: __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
252: }
253: if (env->exception_index == EXCP_EXT_INTERRUPT &&
254: (env->hflags & MIPS_HFLAG_DM))
255: env->exception_index = EXCP_DINT;
256: offset = 0x180;
257: switch (env->exception_index) {
258: case EXCP_DSS:
259: env->CP0_Debug |= 1 << CP0DB_DSS;
260: /* Debug single step cannot be raised inside a delay slot and
261: * resume will always occur on the next instruction
262: * (but we assume the pc has always been updated during
263: * code translation).
264: */
265: env->CP0_DEPC = env->PC;
266: goto enter_debug_mode;
267: case EXCP_DINT:
268: env->CP0_Debug |= 1 << CP0DB_DINT;
269: goto set_DEPC;
270: case EXCP_DIB:
271: env->CP0_Debug |= 1 << CP0DB_DIB;
272: goto set_DEPC;
273: case EXCP_DBp:
274: env->CP0_Debug |= 1 << CP0DB_DBp;
275: goto set_DEPC;
276: case EXCP_DDBS:
277: env->CP0_Debug |= 1 << CP0DB_DDBS;
278: goto set_DEPC;
279: case EXCP_DDBL:
280: env->CP0_Debug |= 1 << CP0DB_DDBL;
281: goto set_DEPC;
282: set_DEPC:
1.1.1.2 root 283: if (env->hflags & MIPS_HFLAG_BMASK) {
1.1 root 284: /* If the exception was raised from a delay slot,
285: * come back to the jump
286: */
287: env->CP0_DEPC = env->PC - 4;
1.1.1.2 root 288: env->hflags &= ~MIPS_HFLAG_BMASK;
1.1 root 289: } else {
290: env->CP0_DEPC = env->PC;
291: }
292: enter_debug_mode:
293: env->hflags |= MIPS_HFLAG_DM;
294: /* EJTAG probe trap enable is not implemented... */
295: pc = 0xBFC00480;
296: break;
297: case EXCP_RESET:
298: #ifdef MIPS_USES_R4K_TLB
299: env->CP0_random = MIPS_TLB_NB - 1;
300: #endif
301: env->CP0_Wired = 0;
302: env->CP0_Config0 = MIPS_CONFIG0;
303: #if defined (MIPS_CONFIG1)
304: env->CP0_Config1 = MIPS_CONFIG1;
305: #endif
306: #if defined (MIPS_CONFIG2)
307: env->CP0_Config2 = MIPS_CONFIG2;
308: #endif
309: #if defined (MIPS_CONFIG3)
310: env->CP0_Config3 = MIPS_CONFIG3;
311: #endif
312: env->CP0_WatchLo = 0;
313: env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
314: goto set_error_EPC;
315: case EXCP_SRESET:
316: env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
317: (1 << CP0St_SR);
318: env->CP0_WatchLo = 0;
319: goto set_error_EPC;
320: case EXCP_NMI:
321: env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
322: (1 << CP0St_NMI);
323: set_error_EPC:
1.1.1.2 root 324: if (env->hflags & MIPS_HFLAG_BMASK) {
1.1 root 325: /* If the exception was raised from a delay slot,
326: * come back to the jump
327: */
328: env->CP0_ErrorEPC = env->PC - 4;
1.1.1.3 ! root 329: env->hflags &= ~MIPS_HFLAG_BMASK;
1.1 root 330: } else {
331: env->CP0_ErrorEPC = env->PC;
332: }
1.1.1.2 root 333: env->hflags = MIPS_HFLAG_ERL;
1.1 root 334: pc = 0xBFC00000;
335: break;
336: case EXCP_MCHECK:
337: cause = 24;
338: goto set_EPC;
339: case EXCP_EXT_INTERRUPT:
340: cause = 0;
341: if (env->CP0_Cause & (1 << CP0Ca_IV))
342: offset = 0x200;
343: goto set_EPC;
344: case EXCP_DWATCH:
345: cause = 23;
346: /* XXX: TODO: manage defered watch exceptions */
347: goto set_EPC;
348: case EXCP_AdEL:
349: case EXCP_AdES:
350: cause = 4;
351: goto set_EPC;
352: case EXCP_TLBL:
353: case EXCP_TLBF:
354: cause = 2;
355: if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
356: offset = 0x000;
357: goto set_EPC;
358: case EXCP_IBE:
359: cause = 6;
360: goto set_EPC;
361: case EXCP_DBE:
362: cause = 7;
363: goto set_EPC;
364: case EXCP_SYSCALL:
365: cause = 8;
366: goto set_EPC;
367: case EXCP_BREAK:
368: cause = 9;
369: goto set_EPC;
370: case EXCP_RI:
371: cause = 10;
372: goto set_EPC;
373: case EXCP_CpU:
374: cause = 11;
1.1.1.2 root 375: env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
1.1 root 376: goto set_EPC;
377: case EXCP_OVERFLOW:
378: cause = 12;
379: goto set_EPC;
380: case EXCP_TRAP:
381: cause = 13;
382: goto set_EPC;
383: case EXCP_LTLBL:
384: cause = 1;
385: goto set_EPC;
386: case EXCP_TLBS:
387: cause = 3;
388: if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
389: offset = 0x000;
390: goto set_EPC;
391: set_EPC:
392: if (env->CP0_Status & (1 << CP0St_BEV)) {
393: pc = 0xBFC00200;
394: } else {
395: pc = 0x80000000;
396: }
397: env->hflags |= MIPS_HFLAG_EXL;
398: pc += offset;
399: env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
1.1.1.2 root 400: if (env->hflags & MIPS_HFLAG_BMASK) {
1.1 root 401: /* If the exception was raised from a delay slot,
402: * come back to the jump
403: */
404: env->CP0_EPC = env->PC - 4;
405: env->CP0_Cause |= 0x80000000;
1.1.1.2 root 406: env->hflags &= ~MIPS_HFLAG_BMASK;
1.1 root 407: } else {
408: env->CP0_EPC = env->PC;
409: env->CP0_Cause &= ~0x80000000;
410: }
411: break;
412: default:
413: if (logfile) {
414: fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
415: env->exception_index);
416: }
417: printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
418: exit(1);
419: }
420: env->PC = pc;
421: if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
422: fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
423: " S %08x C %08x A %08x D %08x\n",
424: __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
425: env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
426: env->CP0_DEPC);
427: }
428: env->exception_index = EXCP_NONE;
429: }
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