Diff for /qemu/target-mips/mips-defs.h between versions 1.1.1.1 and 1.1.1.2

version 1.1.1.1, 2018/04/24 16:37:52 version 1.1.1.2, 2018/04/24 16:44:07
Line 6 Line 6
 /* If we want to use host float regs... */  /* If we want to use host float regs... */
 //#define USE_HOST_FLOAT_REGS  //#define USE_HOST_FLOAT_REGS
   
 enum {  #define MIPS_R4Kc 0x00018000
     MIPS_R4Kc = 0x00018000,  #define MIPS_R4Kp 0x00018300
     MIPS_R4Kp = 0x00018300,  
 };  
   
 /* Emulate MIPS R4Kc for now */  /* Emulate MIPS R4Kc for now */
 #define MIPS_CPU MIPS_R4Kc  #define MIPS_CPU MIPS_R4Kc
Line 19  enum { Line 17  enum {
 #define TARGET_LONG_BITS 32  #define TARGET_LONG_BITS 32
 /* real pages are variable size... */  /* real pages are variable size... */
 #define TARGET_PAGE_BITS 12  #define TARGET_PAGE_BITS 12
 /* Uses MIPS R4Kx ehancements to MIPS32 architecture */  /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
 #define MIPS_USES_R4K_EXT  #define MIPS_USES_R4K_EXT
 /* Uses MIPS R4Kc TLB model */  /* Uses MIPS R4Kc TLB model */
 #define MIPS_USES_R4K_TLB  #define MIPS_USES_R4K_TLB
 #define MIPS_TLB_NB 16  #define MIPS_TLB_NB 16
 /* Have config1, runs in big-endian mode, uses TLB */  /* basic FPU register support */
 #define MIPS_CONFIG0                                            \  #define MIPS_USES_FPU 1
 ((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) |  \  /* Define a implementation number of 1.
  (1 << CP0C0_BE) | (0x001 << CP0C0_MT) | (0x010 << CP0C0_K0))   * Define a major version 1, minor version 0.
    */
   #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
   /* Have config1, uses TLB */
   #define MIPS_CONFIG0_1                                          \
   ((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) |          \
    (1 << CP0C0_MT) | (2 << CP0C0_K0))
   #ifdef TARGET_WORDS_BIGENDIAN
   #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
   #else
   #define MIPS_CONFIG0 MIPS_CONFIG0_1
   #endif
 /* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,  /* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
  * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,   * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
  * no performance counters, watch registers present, no code compression,   * no performance counters, watch registers present, no code compression,
  * EJTAG present, no FPU   * EJTAG present, FPU enable bit depending on MIPS_USES_FPU
  */   */
 #define MIPS_CONFIG1                                            \  #define MIPS_CONFIG1                                            \
 ((15 << CP0C1_MMU) |                                            \  ((15 << CP0C1_MMU) |                                            \
  (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \   (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \
  (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \   (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \
  (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) |          \   (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) |          \
  (1 << CP0C1_EP) | (0 << CP0C1_FP))   (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP))
 #elif defined (MIPS_CPU == MIPS_R4Kp)  #elif (MIPS_CPU == MIPS_R4Kp)
 /* 32 bits target */  /* 32 bits target */
 #define TARGET_LONG_BITS 32  #define TARGET_LONG_BITS 32
 /* real pages are variable size... */  /* real pages are variable size... */
 #define TARGET_PAGE_BITS 12  #define TARGET_PAGE_BITS 12
 /* Uses MIPS R4Kx ehancements to MIPS32 architecture */  /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
 #define MIPS_USES_R4K_EXT  #define MIPS_USES_R4K_EXT
 /* Uses MIPS R4Km FPM MMU model */  /* Uses MIPS R4Km FPM MMU model */
 #define MIPS_USES_R4K_FPM  #define MIPS_USES_R4K_FPM
Line 52  enum { Line 61  enum {
 #error "MIPS CPU not defined"  #error "MIPS CPU not defined"
 /* Remainder for other flags */  /* Remainder for other flags */
 //#define TARGET_MIPS64  //#define TARGET_MIPS64
 //define MIPS_USES_FPU  //#define MIPS_USES_FPU
 #endif  #endif
   
 #endif /* !defined (__QEMU_MIPS_DEFS_H__) */  #endif /* !defined (__QEMU_MIPS_DEFS_H__) */

Removed from v.1.1.1.1  
changed lines
  Added in v.1.1.1.2


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