Diff for /qemu/target-mips/mips-defs.h between versions 1.1.1.2 and 1.1.1.3

version 1.1.1.2, 2018/04/24 16:44:07 version 1.1.1.3, 2018/04/24 16:46:32
Line 14 Line 14
   
 #if (MIPS_CPU == MIPS_R4Kc)  #if (MIPS_CPU == MIPS_R4Kc)
 /* 32 bits target */  /* 32 bits target */
 #define TARGET_LONG_BITS 32  #undef MIPS_HAS_MIPS64
   //#define MIPS_HAS_MIPS64 1
 /* real pages are variable size... */  /* real pages are variable size... */
 #define TARGET_PAGE_BITS 12  #define TARGET_PAGE_BITS 12
 /* Uses MIPS R4Kx enhancements to MIPS32 architecture */  /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
Line 22 Line 23
 /* Uses MIPS R4Kc TLB model */  /* Uses MIPS R4Kc TLB model */
 #define MIPS_USES_R4K_TLB  #define MIPS_USES_R4K_TLB
 #define MIPS_TLB_NB 16  #define MIPS_TLB_NB 16
   #define MIPS_TLB_MAX 128
 /* basic FPU register support */  /* basic FPU register support */
 #define MIPS_USES_FPU 1  #define MIPS_USES_FPU 1
 /* Define a implementation number of 1.  /* Define a implementation number of 1.
  * Define a major version 1, minor version 0.   * Define a major version 1, minor version 0.
  */   */
 #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)  #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
 /* Have config1, uses TLB */    /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
 #define MIPS_CONFIG0_1                                          \       uncached coherency */
 ((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) |          \  #define MIPS_CONFIG0_1                                            \
  (1 << CP0C0_MT) | (2 << CP0C0_K0))    ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) |      \
      (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
      (0x2 << CP0C0_K0))
 #ifdef TARGET_WORDS_BIGENDIAN  #ifdef TARGET_WORDS_BIGENDIAN
 #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))  #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
 #else  #else
 #define MIPS_CONFIG0 MIPS_CONFIG0_1  #define MIPS_CONFIG0 MIPS_CONFIG0_1
 #endif  #endif
 /* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,  /* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
  * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,     2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
  * no performance counters, watch registers present, no code compression,     no coprocessor2 attached, no MDMX support attached,
  * EJTAG present, FPU enable bit depending on MIPS_USES_FPU     no performance counters, watch registers present,
  */     no code compression, EJTAG present, FPU enable bit depending on
 #define MIPS_CONFIG1                                            \     MIPS_USES_FPU */
 ((15 << CP0C1_MMU) |                                            \  #define MIPS_CONFIG1_1                                            \
  (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \  ((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) |              \
  (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \   (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) |      \
  (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) |          \   (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) |      \
  (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP))   (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
    (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP))
   #ifdef MIPS_USES_FPU
   #define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (1 << CP0C1_FP))
   #else
   #define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (0 << CP0C1_FP))
   #endif
   /* Have config3, no tertiary/secondary caches implemented */
   #define MIPS_CONFIG2                                              \
   ((1 << CP0C2_M))
   /* No config4, no DSP ASE, no large physaddr,
      no external interrupt controller, no vectored interupts,
      no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
   #define MIPS_CONFIG3                                              \
   ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
    (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
    (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
 #elif (MIPS_CPU == MIPS_R4Kp)  #elif (MIPS_CPU == MIPS_R4Kp)
 /* 32 bits target */  /* 32 bits target */
 #define TARGET_LONG_BITS 32  #undef MIPS_HAS_MIPS64
 /* real pages are variable size... */  /* real pages are variable size... */
 #define TARGET_PAGE_BITS 12  #define TARGET_PAGE_BITS 12
 /* Uses MIPS R4Kx enhancements to MIPS32 architecture */  /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
Line 59 Line 79
 #define MIPS_USES_R4K_FPM  #define MIPS_USES_R4K_FPM
 #else  #else
 #error "MIPS CPU not defined"  #error "MIPS CPU not defined"
 /* Remainder for other flags */  /* Reminder for other flags */
 //#define TARGET_MIPS64  //#undef MIPS_HAS_MIPS64
 //#define MIPS_USES_FPU  //#define MIPS_USES_FPU
 #endif  #endif
   
   #ifdef MIPS_HAS_MIPS64
   #define TARGET_LONG_BITS 64
   #else
   #define TARGET_LONG_BITS 32
   #endif
   
 #endif /* !defined (__QEMU_MIPS_DEFS_H__) */  #endif /* !defined (__QEMU_MIPS_DEFS_H__) */

Removed from v.1.1.1.2  
changed lines
  Added in v.1.1.1.3


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