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Annotation of qemu/target-mips/mips-defs.h, revision 1.1.1.2

1.1       root        1: #if !defined (__QEMU_MIPS_DEFS_H__)
                      2: #define __QEMU_MIPS_DEFS_H__
                      3: 
                      4: /* If we want to use 64 bits host regs... */
                      5: //#define USE_64BITS_REGS
                      6: /* If we want to use host float regs... */
                      7: //#define USE_HOST_FLOAT_REGS
                      8: 
1.1.1.2 ! root        9: #define MIPS_R4Kc 0x00018000
        !            10: #define MIPS_R4Kp 0x00018300
1.1       root       11: 
                     12: /* Emulate MIPS R4Kc for now */
                     13: #define MIPS_CPU MIPS_R4Kc
                     14: 
                     15: #if (MIPS_CPU == MIPS_R4Kc)
                     16: /* 32 bits target */
                     17: #define TARGET_LONG_BITS 32
                     18: /* real pages are variable size... */
                     19: #define TARGET_PAGE_BITS 12
1.1.1.2 ! root       20: /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
1.1       root       21: #define MIPS_USES_R4K_EXT
                     22: /* Uses MIPS R4Kc TLB model */
                     23: #define MIPS_USES_R4K_TLB
                     24: #define MIPS_TLB_NB 16
1.1.1.2 ! root       25: /* basic FPU register support */
        !            26: #define MIPS_USES_FPU 1
        !            27: /* Define a implementation number of 1.
        !            28:  * Define a major version 1, minor version 0.
        !            29:  */
        !            30: #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
        !            31: /* Have config1, uses TLB */
        !            32: #define MIPS_CONFIG0_1                                          \
        !            33: ((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) |          \
        !            34:  (1 << CP0C0_MT) | (2 << CP0C0_K0))
        !            35: #ifdef TARGET_WORDS_BIGENDIAN
        !            36: #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
        !            37: #else
        !            38: #define MIPS_CONFIG0 MIPS_CONFIG0_1
        !            39: #endif
1.1       root       40: /* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
                     41:  * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
                     42:  * no performance counters, watch registers present, no code compression,
1.1.1.2 ! root       43:  * EJTAG present, FPU enable bit depending on MIPS_USES_FPU
1.1       root       44:  */
                     45: #define MIPS_CONFIG1                                            \
                     46: ((15 << CP0C1_MMU) |                                            \
                     47:  (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \
                     48:  (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \
                     49:  (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) |          \
1.1.1.2 ! root       50:  (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP))
        !            51: #elif (MIPS_CPU == MIPS_R4Kp)
1.1       root       52: /* 32 bits target */
                     53: #define TARGET_LONG_BITS 32
                     54: /* real pages are variable size... */
                     55: #define TARGET_PAGE_BITS 12
1.1.1.2 ! root       56: /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
1.1       root       57: #define MIPS_USES_R4K_EXT
                     58: /* Uses MIPS R4Km FPM MMU model */
                     59: #define MIPS_USES_R4K_FPM
                     60: #else
                     61: #error "MIPS CPU not defined"
                     62: /* Remainder for other flags */
                     63: //#define TARGET_MIPS64
1.1.1.2 ! root       64: //#define MIPS_USES_FPU
1.1       root       65: #endif
                     66: 
                     67: #endif /* !defined (__QEMU_MIPS_DEFS_H__) */

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