Annotation of qemu/target-mips/mips-defs.h, revision 1.1.1.3

1.1       root        1: #if !defined (__QEMU_MIPS_DEFS_H__)
                      2: #define __QEMU_MIPS_DEFS_H__
                      3: 
                      4: /* If we want to use 64 bits host regs... */
                      5: //#define USE_64BITS_REGS
                      6: /* If we want to use host float regs... */
                      7: //#define USE_HOST_FLOAT_REGS
                      8: 
1.1.1.2   root        9: #define MIPS_R4Kc 0x00018000
                     10: #define MIPS_R4Kp 0x00018300
1.1       root       11: 
                     12: /* Emulate MIPS R4Kc for now */
                     13: #define MIPS_CPU MIPS_R4Kc
                     14: 
                     15: #if (MIPS_CPU == MIPS_R4Kc)
                     16: /* 32 bits target */
1.1.1.3 ! root       17: #undef MIPS_HAS_MIPS64
        !            18: //#define MIPS_HAS_MIPS64 1
1.1       root       19: /* real pages are variable size... */
                     20: #define TARGET_PAGE_BITS 12
1.1.1.2   root       21: /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
1.1       root       22: #define MIPS_USES_R4K_EXT
                     23: /* Uses MIPS R4Kc TLB model */
                     24: #define MIPS_USES_R4K_TLB
                     25: #define MIPS_TLB_NB 16
1.1.1.3 ! root       26: #define MIPS_TLB_MAX 128
1.1.1.2   root       27: /* basic FPU register support */
                     28: #define MIPS_USES_FPU 1
                     29: /* Define a implementation number of 1.
                     30:  * Define a major version 1, minor version 0.
                     31:  */
                     32: #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
1.1.1.3 ! root       33:   /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
        !            34:      uncached coherency */
        !            35: #define MIPS_CONFIG0_1                                            \
        !            36:   ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) |      \
        !            37:    (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
        !            38:    (0x2 << CP0C0_K0))
1.1.1.2   root       39: #ifdef TARGET_WORDS_BIGENDIAN
                     40: #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
                     41: #else
                     42: #define MIPS_CONFIG0 MIPS_CONFIG0_1
                     43: #endif
1.1.1.3 ! root       44: /* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
        !            45:    2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
        !            46:    no coprocessor2 attached, no MDMX support attached,
        !            47:    no performance counters, watch registers present,
        !            48:    no code compression, EJTAG present, FPU enable bit depending on
        !            49:    MIPS_USES_FPU */
        !            50: #define MIPS_CONFIG1_1                                            \
        !            51: ((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) |              \
        !            52:  (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) |      \
        !            53:  (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) |      \
        !            54:  (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
        !            55:  (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP))
        !            56: #ifdef MIPS_USES_FPU
        !            57: #define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (1 << CP0C1_FP))
        !            58: #else
        !            59: #define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (0 << CP0C1_FP))
        !            60: #endif
        !            61: /* Have config3, no tertiary/secondary caches implemented */
        !            62: #define MIPS_CONFIG2                                              \
        !            63: ((1 << CP0C2_M))
        !            64: /* No config4, no DSP ASE, no large physaddr,
        !            65:    no external interrupt controller, no vectored interupts,
        !            66:    no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
        !            67: #define MIPS_CONFIG3                                              \
        !            68: ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
        !            69:  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
        !            70:  (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
1.1.1.2   root       71: #elif (MIPS_CPU == MIPS_R4Kp)
1.1       root       72: /* 32 bits target */
1.1.1.3 ! root       73: #undef MIPS_HAS_MIPS64
1.1       root       74: /* real pages are variable size... */
                     75: #define TARGET_PAGE_BITS 12
1.1.1.2   root       76: /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
1.1       root       77: #define MIPS_USES_R4K_EXT
                     78: /* Uses MIPS R4Km FPM MMU model */
                     79: #define MIPS_USES_R4K_FPM
                     80: #else
                     81: #error "MIPS CPU not defined"
1.1.1.3 ! root       82: /* Reminder for other flags */
        !            83: //#undef MIPS_HAS_MIPS64
1.1.1.2   root       84: //#define MIPS_USES_FPU
1.1       root       85: #endif
                     86: 
1.1.1.3 ! root       87: #ifdef MIPS_HAS_MIPS64
        !            88: #define TARGET_LONG_BITS 64
        !            89: #else
        !            90: #define TARGET_LONG_BITS 32
        !            91: #endif
        !            92: 
1.1       root       93: #endif /* !defined (__QEMU_MIPS_DEFS_H__) */

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